DETAILED ACTION
Applicants’ response filed 7/31/2026 has been considered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-6, 9, 11-15, 19-25, 27-29, 31 and 32 are pending.
Specification and drawings are accepted.
IDSs have been considered. PTO-1449 are attached.
Application is pending.
Allowable Subject Matter
Claims 27-29 and 31-32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6, 9, 11-15 and 19-25 are rejected under 35 U.S.C. 103 as being unpatentable over Ho et al. USPN 12,456,068B1 (herein: D1) in view of Ronagh et al. USPN 12,353,965B2 (herein: D2).
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As per claim 1, D1 substantially teaches (i.e., abstract and Figure 2 above) classical superconducting circuit functioning (i.e., Figure 2 and col., 4, lines 45-54) comprising for a decoder of quantum error correcting codes (i.e., Figure 2, reference number 208 and cols. 5, 7, lines 10-15), wherein the decoder comprises a plurality of nodes, a plurality of interconnects between nodes of the plurality of nodes for distributing pulses between the nodes (i.e., Figure 2, reference number 208 has plurality of nodes and interconnects), and a plurality of weights representative of the parameters (i.e., Figure 2 and col. 7, lines 45-57), wherein each node of the plurality of nodes comprises: a receiver section to receive at least one pulse comprising a magnetic flux, current, or voltage (i.e., Figure 2, reference number 208 having inputs and cols. 4-7); a processing core to process the received pulse (i.e., Figure 2, reference number 208 processing the inputs and cols. 4-7); and a transmitter section to transmit the processed pulse (i.e., Figure 2, reference number 208 outputting and cols. 4-7).
D1 does not explicitly teach a cryogenic temperatures and a function approximator as stated in the present application. However D2 teaches in an analogous art (i.e., abstract) methods and systems for using one or more artificial intelligence (AI) procedures (such as one or more machine learning (ML) or reinforcement learning (RL) procedures) implemented on a classical computer to perform a heuristic through interaction with a computation performed using a classical or non-classical computer (such as a quantum computer). Particularly D2 teaches (i.e., col. 2) a system for performing a computation using artificial intelligence (AI), may comprise: (a) at least one computer configured to perform a computation comprising one or more tunable parameters and one or more non-tunable parameters and output a report indicative of the computation, the computer comprising: (i) one or more registers, wherein the one or more registers are configured to perform the computation; (ii) a measurement unit configured to measure a state of at least one of the one or more registers to determine a representation of the state of the one or more registers, thereby determining a representation of the computation; and (b) at least one AI control unit configured to control the computation, to perform at least one AI procedure to determine one or more tunable parameters corresponding to the computation, and to direct the tunable parameters to the computer, wherein the at least one artificial intelligence (AI) control unit comprises one or more AI control unit parameters. The computer may comprise a hybrid computing system comprising: (a) at least one non-classical computer configured to perform the computation, comprising: (i) the one or more registers; and (ii) the measurement unit; and (b) the AI control unit. The at least one non-classical computer may comprise at least one quantum computer; wherein the one or more registers comprises one or more qubits, the one or more qubits configured to perform the computation; wherein the measurement unit is configured to measure a state of at least one of the one or more qubits to determine a representation of the state of the at least one of the one or more qubits, thereby determining a representation of the computation; wherein the measurement unit is further configured to provide the representation of the computation to the AI control unit. The measurement unit may be configured to measure the state of at least one of the one or more qubits to obtain syndrome data representative of partial information about a current state of the computation and to provide the syndrome data to the AI control unit. The one or more registers may comprise computation registers and syndrome registers; wherein the computation registers comprise one or more computation qubits, the one or more computation qubits configured to perform the computation; wherein the syndrome registers comprise one or more syndrome qubits different from the one or more computation qubits, wherein the one or more syndrome qubits are quantum mechanically entangled with the one or more computation qubits and wherein the one or more syndrome qubits are not for performing the computation; and wherein the measurement unit is configured to measure a state of the one or more syndrome qubits to determine a representation of a state of the one or more computation qubits, thereby determining the representation of the computation. The computation may comprise quantum computation. The quantum computation may comprise adiabatic quantum computation. The quantum computation may comprise quantum approximate optimization algorithm (QAOA). The quantum computation may comprise variational quantum algorithm. The quantum computation may comprise error correction on a quantum register. The quantum computation may comprise a fault tolerant quantum computation gadget. The computation may comprise classical computation. The computation may comprise at least one member selected from the group consisting of: simulated annealing, simulated quantum annealing, parallel tempering, parallel tempering with Isoenergetic cluster moves, diffusion Monte Carlo, population annealing and quantum Monte Carlo. The at least one quantum computer may be configured to perform one or more quantum operations comprising at least one member selected from the group consisting of: preparation of initial states of the one or more qubits; implementation of one or more single qubit quantum gates on the one or more qubits; implementation of one or more multi-qubit quantum gates on the one or more qubits; and adiabatic evolution from an initial to a final Hamiltonian using one or more qubits. The representation of the state of the one or more computation qubits may be correlated with the state of the one or more syndrome qubits. The measurement unit may be configured to measure the state of the one or more syndrome qubits during an evolution of the one or more computation qubits during the computation. The at least one non-classical computer may comprise an integrated photonic coherent Ising machine computer. The at least one non-classical computer may comprise a network of optic parametric pulses. The at least one AI procedure may comprise at least one machine learning (ML) procedure. The at least one ML procedure may comprise at least one ML training procedure. The at least one ML procedure may comprise at least one ML inference procedure. The at least one AI procedure may comprise at least one reinforcement learning (RL) procedure. The at least one AI procedure may be configured to modify the tunable parameters during the computation, thereby providing one or more modified tunable parameters. The one or more modified tunable parameters may be configured to modify the computation during a course of the computation. The at least one AI control unit may comprise at least one member selected from the group consisting of: a tensor processing unit (TPU), a graphical processing unit (GPU), a field-programmable gate array (FPGA), and an application-specific integrated circuit (ASIC). The at least one computer may comprise at least one member selected from the group consisting of: a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC). The at least one AI control unit may be in communication with the at least one computer over a network. The at least one AI control unit may be in communication with the at least computer over a cloud network. The at least one AI control unit may be integrated as a classical processing system operating at deep cryogenic temperatures within a refrigerator system. The one or more tunable parameters and one or more non-tunable parameters may define a next segment of the computation comprising an instruction set from a current representation of the computation. The one or more tunable parameters may comprise an initial temperature of the computation. The one or more tunable parameters may comprise a temperature schedule of the computation. The one or more tunable parameters may comprise a final temperature of the computation. The one or more tunable parameters may comprise a schedule of pumping energy of the network. The one or more tunable parameters may comprise an indication of quantum gates for a segment of quantum computation. The one or more tunable parameters may comprise an indication of a local operations and classical communication (LOCC) channel for a segment of the quantum computation. The AI control unit may comprise a neural network and wherein the one or more AI control unit parameters comprise neural network weights corresponding to the neural network. D2 further teaches (i.e., col. 11) an optimization problem may be solved by storing an approximation of an optimal policy, by storing an approximation of the cumulative reward function, or both. In some cases, RL procedures may store one or more tables of approximate values for such functions. In other cases, RL procedure may utilize one or more “function approximators.” Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to combine the teachings of D2 with D1. This would have been obvious to one having ordinary skill because one of ordinary skill would have recognized that by operating in cryogenic temperatures and having a function approximator would have improved the error correction capability of the system.
As per claim 2, D1 substantially teaches, in view of above rejections, mixed-signal digital and analogue Josephson junction superconducting electronics comprising magnetic junctions and quantum phase slip devices (i.e., Figure 2 and col. 1).
As per claim 3, D2 substantially teaches, in view of above rejections, the Josephson junction superconducting electronics comprises digital and mixed-signal quantum flux families comprising energy efficient rapid single flux quantum (ERSFQ), energy efficient single flux quantum (eSFQ), adiabatic quantum flux parametron (AQFP), reciprocal quantum logic (RQL), rapid single flux quantum (RSFQ), SFQuClass, or superconducting quantum interface device (SQUID, Bi-SQUID, nSQUID) (i.e., Figure 1 and cols. 1, 19-20).
As per claim 4, D1 substantially teaches, in view of above rejections, each node is configured to operate at analog, digital or analog-digital mode (i.e., Figure 2 and col. 3).
As per claim 5, D1 substantially teaches, in view of above rejections, the nodes are arranged in layers, further wherein the receiver section of the nodes in a first layer and the transmitter section in a last layer operate at digital mode; and the nodes in other layers operate at analog mode (i.e., Figures 2, 5 and cols. 10-11).
As per claim 6, D2 substantially teaches, in view of above rejections, one of the interconnects of the plurality of the interconnects comprises at least one member of the group consisting of an analog interconnect, a digital interconnect, a hybrid of analog and digital interconnect, an interconnect operated synchronously, an interconnect operated asynchronously, an electrical interconnect, a magnetic interconnect, a photonic interconnect, a parallel interconnect, a serial interconnect, an electrical interconnect using a Josephson transmission line (JTL), and an electrical interconnect using a passive transmission line (PTL) (i.e., Figure 1 and cols. 13-14).
As per claim 9, D1 substantially teaches, in view of above rejections, at least one weight of the plurality of weights comprises at least one of a fixed coupling or a variable coupling, further wherein the fixed coupling comprises a magnetic coupling, a capacitive coupling, or a resistive coupling and the variable coupling comprises a magnetic coupling, a capacitive coupling, a galvanic coupling, or a resistive coupling (i.e., Figure 2 and cols. 4-5).
As per claim 11, D1 substantially teaches, in view of above rejections, the magnetic coupling comprises a transformer; wherein different coupling strengths are used for different input pulses in the transformer to represent the weights of the plurality of weights; and wherein fixed magnetic coupling is proportional to the weight (i.e., Figure 2 and cols. 4-5).
As per claim 12, D1 substantially teaches, in view of above rejections, the resistive coupling comprises a voltage divider; further wherein different coupling strengths are used for different input pulses in the voltage divider to represent the weights of the plurality of weights; further wherein fixed resistive coupling is proportional to the weight (i.e., Figure 2 and cols. 4-6).
As per claim 13, D2 substantially teaches, in view of above rejections, wherein the weights of the plurality of weights are represented via at least one of generating a number of single flux quantum (SFQ) pulses proportional to the weight, generating pulse rate proportional to the weight, or generating pulses of strength proportional to the weight (i.e., Figure 1, reference number 120 and cols. 19-23).
As per claim 14, D1 substantially teaches, in view of above rejections, superconducting quantum interface device (SQUID); at least one of the number of generated pulses, the pulse rate or the pulses strength is varied by changing a bias current or a critical current of the superconducting quantum interface device (SQUID) (i.e., Figure 2 and cols. 3-4).
As per claim 15, D1 substantially teaches, in view of above rejections, wherein the processing core comprises at least one storage loop for storing the magnetic flux; and the magnetic flux is cleared using a resistor, a SQUID, or a command pulse that could be a clock (i.e., Figure 2 and cols. 3-5).
As per claim 19, D2 substantially teaches, in view of above rejections, the pulses between the nodes are generated using line drivers wherein each the pulse creates at least one pulse (i.e., Figure 1 and cols. 1-3).
As per claim 20, D2 substantially teaches, in view of above rejections, wherein the function approximator for a decoder of quantum error correcting codes comprises a neural network; further wherein the neural network parameters and activations are represented by the decoder nodes and weights; further wherein the neural network activations are implemented using the nodes processing cores (i.e., Figure 4 and cols. 19-24).
As per claim 21, D2 substantially teaches, in view of above rejections, wherein the activations comprise sigmoid or rectified linear unit (ReLU) activation functions (i.e., Figure 1 and cols. 11-14).
As per claim 22, D2 substantially teaches, in view of above rejections, wherein the neural network comprises a recurrent neural network, a deep neural network, a feed forward neural network, a convolutional neural network, a Hopfield network, a Boltzmann machine, or a graphical model (i.e., Figure 1 and cols. 11-12).
As per claim 23, D2 substantially teaches, in view of above rejections, wherein the function approximator for a decoder of quantum error correcting codes comprises at least one member of the group consisting of a neural network, a linear function approximator, a regression unit, a classifier, a decision tree, and a random forest (i.e., Figure 1 and cols. 10-18).
As per claim 24, D2 substantially teaches, in view of above rejections, wherein at least one weight of the plurality of weights is programmable (i.e., Figure 1 and cols. 10-18).
As per claim 25, D2 substantially teaches, in view of above rejections, wherein the function approximator is programmable using an input from a user (i.e., Figure 1 and cols. 10-18).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUJTABA M CHAUDRY whose telephone number is (571)272-3817. The examiner can normally be reached Monday-Friday 9am-5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert DeCady can be reached at 571-272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MUJTABA M. CHAUDRY
Primary Examiner
Art Unit 2112
/MUJTABA M CHAUDRY/Primary Examiner, Art Unit 2112
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