Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to communications filed on 5/1/2026.
Claims 1-4, 7, 9-13 & 16 are pending and presented for examination.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. 202210031486X, filed on 1/12/2022.
Response to Amendment
Claims 1, 2 & 11 have been amended.
Rejections to claims 1, 2 & 11 under 35 USC 112(b) have been withdrawn based on amendments to these claims.
Response to Arguments
Applicant’s arguments, see “Remarks”, filed 5/1/2026, with respect to the rejections of claims 1, 2 & 11 under 35 USC 112(b) have been fully considered and are persuasive. Therefore, these rejections have been withdrawn based on amendments to these claims.
Applicant’s arguments, see “Remarks”, filed 2/2/2026, with respect to the rejections of claims 1-4, 7, 9-13 & 16 under 35 USC 103 have been fully considered but are not persuasive. Applicant submits that these claims are patentable because the cited references of Montalvo et al. (US 11095350), Corman et al. (2019/0334253), Song et al. (US 2018/0048054), Ye et al. (US 2023/0039947) and Zhang et al. (WO 2021/057557), either alone or in combination, fail to disclose all the limitations in these claims. Examiner respectfully disagrees noting that, per 35 U.S.C. 103, a patent for a claimed invention may not be obtained if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains (see §MPEP 2141).
Regarding claim 1, applicant argues that the combination of Montalvo and Corman do not result in the claimed configuration in which the first processing units are connected to the first antennas while simultaneously being shared with the second antennas via differential connections, as specified by claim 1, because Corman at most teaches employing multiple vector generators to produce differential signals but not implemented within distinct transceivers associated with different antenna elements. Examiner respectfully disagrees noting that Corman is only used to teach that the non-differential connections of antennas to transceivers disclosed by Montalvo can be substituted with differential connections of antennas to two different transceivers disclosed by Montalvo (i.e. each vector generator can represent a transceiver disclosed by Montalvo such that pairs of transceivers in Montalvo can provide the differential connections to the M antennas as disclosed in claim 1. Song is used to teach of the sharing of antennas between the non-differential connections and the differential connections, so it is moot that Montalvo in view of Corman fails to teach of the sharing of antennas between the non-differential connections and the differential connections.
Applicant argues that Song at most teaches operating one transmitting antenna and one receiving antenna using the switch unit 103, but does not disclose or suggest a specific configuration in which the number of first antennas exceeds the number of second antennas due to a defined sharing scheme of the first processing units, such that the TX path of one antenna and the RX path of the other antenna are simultaneously selected so as to enable concurrent operation of the antennas in different modes, such that when two first processing units transmit signals via two corresponding first antennas, both first processing units receive signals from a single second antenna. Conversely, when the two first processing units transmit signals via the single second antenna, they receive signals from the two corresponding first antennas, or in other words, the operation of a pair of first antennas is consistently associated with a single second antenna as a result of the claimed connection and sharing scheme. Examiner respectfully disagrees noting that by substituting the DPDT switch of Song into each transceiver of Montalvo such that the first control end of each DPDT switch is connected to the low noise amplifier receive path in the corresponding transceiver, the second control end of each DPDT switch is connected to the power amplifier transmit path in the corresponding transceiver, the common end of the first end and second end of the DPDT switch is connected to a corresponding antenna of the N non-differential antennas and the common end of the third end and fourth end of the DPDT switch is connected to a corresponding antenna of the M differential antennas, the configuration of claim 1 is realized.
Based on the above discussion, examiner maintains rejection of amended claim 1 under 35 USC 103 based on Montalvo in view of Corman and Song.
Regarding claim 11, applicant submits that this claim is patentable due to similar amendments and arguments as made for claim 1. Examiner respectfully disagrees and for the same reasons as discussed above, examiner maintains rejection of amended claim 11 under 35 USC 103 based on Montalvo in view of Corman and Song.
Regarding claims 2-4, 7, 9, 10, 12, 13 & 16, applicant submits that these claims is patentable due to amendments and arguments made for claims 1 & 11 and due to their dependency on claims 1 or 11. Examiner respectfully disagrees and for the same reasons as discussed above, examiner maintains rejections of claims 2-4, 7, 9, 10, 12, 13 & 16 under 35 USC 103.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4, 7, 11-13 & 16 are rejected under 35 U.S.C. 103 as being unpatentable over Montalvo et al. (US 11095350)(herein after “Montalvo”) in view of Corman et al. (US 2019/0334253)(herein after “Corman”), and further in view of Song et al. (US 2018/0048054)(herein after “Song”).
Regarding claim 1, Montalvo discloses a millimeter wave antenna circuit (Fig 2, fig 3 & col 2, lines 3-10 disclose a system configured to implement per-antenna beamforming. Col 4, lines 33-59 discloses that the per-antenna beamforming may take the form of an entirely hardware, software or combined hardware and software embodiment that may be a circuit. Fig 6 & col 13, lines 37-51 disclose that the per carrier beamforming may take on any frequency depending on the wireless technology of the RF system. Col 1, lines 14-16 disclose that RF systems transmit and receive electromagnetic waves in the RF range between 3 kHz and 300 GHz (i.e. including millimeter wave between 30 GHz and 300 GHz).), comprising:
a first antenna array (Fig 2, col 7, lines 50-67 & col 8, lines 1-9 disclose an antenna array 250 that may be broken up into multiple “antenna cells” 260-1 through 260-N, each consisting of an array of K antenna elements. Antenna cell 260-1 represents a first antenna array consisting of antenna elements 11 through 1K.);
a second antenna array (Fig 2, col 7, lines 50-67 & col 8, lines 1-9 disclose one example where antenna array 250 is broken up into N columns and K rows. An alternative antenna array 250 example would be an antenna array broken up into a first antenna array consisting of antenna elements 11 through 1K, a second antenna array consisting of antenna elements 21 through N1, and K-1 more antenna arrays consisting of antenna elements 22 through N2, 23 through N3,…, and 2K through NK.); and
a processor (Fig 7 & col 16, lines 4-11 disclose processing system 700, including processor 702. Fig 2, col 16, lines 57-67 disclose that any of the processing elements (e.g. the transceivers of transceiver array 230) that can communicate with processing system 700 should be construed as being encompassed within a broad “processor”. Thus, each transceiver of transceiver array 230 can represent part of the broad “processor” (i.e. a processing unit). For the purpose of this review, the transceivers of transceiver array will be termed “transceiver processing units”, and the processing system 700 plus the transceiver processing units comprise the broad “processor”.);
wherein the first antenna array comprises N first antennas, and the second antenna array comprises M second antennas, wherein N is greater than M (Fig 2, col 7, lines 50-67 & col 8, lines 1-9 disclose a first antenna array consisting of antenna cell 260-1 comprising K first elements. Based on the second array example discussed above, the second antenna array comprises N-1 second antennas consisting of antenna elements 21 through N1. In a scenario where, for example, N=5 and K=5, then the first antenna array consists of K=5 antennas which is greater than the second antenna array consisting of N-1=4 antenna elements.);
wherein the processor comprises a plurality of first processing units (Fig 7 & col 16, lines 4-11 and Fig 2, col 16, lines 57-67 disclose a broad “processor” comprising a plurality of first transceiver processing units of transceiver array 230, each making up part of the broad “processor”.), each of the N first antennas is connected to a first processing unit in the plurality of first processing units in a one-to-one correspondence (Fig 2. & col 8, lines 27-51 disclose that each of the K first antennas 11 through 1K are connected to a designated/different/respective (i.e. in one-to-one correspondence with) first transceiver processing unit 11 through 1K, of the plurality of first processing units of transceiver array 230.), each of the M second antennas is connected to different first processing units in the plurality of first processing units (Fig 2. & col 8, lines 27-51 disclose that each of the N-1 second antennas 21 through N1 are connected to different designated first transceiver processing units 21 through N1, of the plurality of first transceiver processing units of transceiver array 230.), and each first processing unit in the plurality of first processing units comprises a power amplifier (Fig 2 & col 9, lines 4-23 and fig 5, col 12, lines 11-18 disclose that each of the first transceiver processing units, of the plurality of transceiver processing units in transceiver array 230, in transceiver cells 240 may include a power amplifier.), a low noise amplifier (Fig 4, col 10, lines 40-51 disclose that each transceiver processing units may include a low-noise amplifier between antenna element 450 and ADC 436.), and a switch (Fig 4, col 9, lines 51-61 disclose that each transceiver processing unit may include a switch.);
wherein the processor is configured to send a first signal to the first antenna array by using one first processing unit connected to one of the N first antennas (Fig 2, fig 4 & col 9, lines 24-67 and col 10, lines 1-39 disclose transceiver processing unit 11 of fig 2 as part of the broad “processor” is configured to output a first phase and amplitude adjusted signal that is provided to antenna 11 of the first antenna array consisting of K antennas 11 through 1K. (i.e. one of the K first antennas).);
wherein the processor is configured to send a second signal to the second antenna array using one first processing unit connected to one of the M second antennas (Fig 2, fig 4 & col 9, lines 24-67 and col 10, lines 1-39 disclose that a transceiver processing unit (e.g. transceiver processing unit 21 of fig 2) as part of the broad “processor” is configured to output a phase and amplitude adjusted signal that is provided to antenna 21 of the second antenna array consisting of N-1 antennas 21 through N1. (i.e. one of the N-1 second antennas.).);
wherein the first antenna array is configured to radiate a first millimeter wave signal based on the first signal (Col 8, lines 10-26 disclose that any plurality of antenna elements of antenna array 250 may be configured to transmit RF signals. Fig 6 & col 18, lines 29-55 disclose an example where a first RF signal is wirelessly transmitted by antenna element 11 based on a first signal C1 (e.g. a first antenna array consisting of antenna elements 11 through 1K is configured to radiate a first RF signal based on first phase and amplitude adjusted signal that is provided to antenna 11). Fig 6 & col 13, lines 37-51 disclose that first signal C1 may be of any frequency (e.g. including being a first millimeter wave signal between 30 GHz and 300 GHz).);
wherein the second antenna array is configured to radiate a second millimeter wave signal based on the second signal (Col 8, lines 10-26 disclose that any plurality of antenna elements of antenna array 250 may be configured to transmit RF signals. Fig 6 & col 18, lines 29-55 disclose an example where a second RF signal is wirelessly transmitted by an antenna element (e.g. antenna element 21) based on a second signal C1 (e.g. a first antenna array consisting of antenna elements 21 through N1 is configured to radiate a second RF signal based on second phase and amplitude adjusted signal that is provided to antenna 21). Fig 6 & col 13, lines 37-51 disclose that second signal C1 may be of any frequency (e.g. including being a second millimeter wave signal between 30 GHz and 300 GHz).),
wherein each first processing unit in the plurality of first processing units comprises a transmitting path and a receiving path, each transmitting path comprises a corresponding power amplifier, each receiving path comprises a corresponding low noise amplifier (Fig 2, fig 4 and col 9, lines 36-41 & col 10, lines 29-36 & lines 44-51 disclose that each channel of each transceiver array 230 comprises a TX path including a power amplifier and an Rx path including a low noise amplifier.).
Montalvo fails to disclose wherein the connecting of each of the M second antennas is a differential connection to two different first processing units.
However, Corman teaches wherein the connecting of each of the M second antennas is a differential connection to two different first processing units (Fig 12 & [0115] disclose a phased array antenna 1200 where antenna element 1201 is differentially fed with two signals that are 180 degrees out of phase.).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to substitute the single connections of each of the M second antennas to different first processing units, where the processor sends the second signal to the second antenna array using one first processing unit connected to one of the M second antennas, as disclosed by Montalvo, with the differential feeding connections of two signals to an antenna element, as taught by Corman, resulting in connections of each of the M second antennas to two different first processing units, where the processor sends the second signal to the second array through differential feeding by using two different first processing units connected to one of the M second antennas. The motivation to do so would be to have an antenna circuit where pairs of designated transceiver process units adjust an input signal to produce two output signals that are 180 degrees out-of-phase to differentially feed into corresponding antenna elements of an antenna array to reduce common noise or interference present in the two transmit paths of paired transceivers.
Montalvo fails to disclose but Song further teaches wherein a switch is a double-pole double throw switch(Fig 2 & [0024]-[0025] disclose a double pole double throw switch.); and
when the switch in each first processing unit of the plurality of processing units is in a first switch-on state, each corresponding power amplifier in each corresponding transmitting path is connected to a corresponding first antenna and each corresponding low noise amplifier in each corresponding receiving path is connected to a corresponding second antenna (Fig 2 & [0025] disclose that, within the double pole double throw (DPDT) switch, when a first control end is coupled with a first end and a second control end is coupled with a fourth end (i.e. the DPDT switch is in a first switch-on state), then a first antenna is coupled to a transmit end (i.e. a transmitting path including a power amplifier) and a second antenna is coupled to a receive end (i.e. a receiving path including a low noise amplifier).), when the switch in each first processing unit of the plurality of first processing units is in a second switch-on state, each corresponding power amplifier in each corresponding transmitting path is connected to the corresponding second antenna and each corresponding low noise amplifier in each corresponding receiving path is connected to the corresponding first antenna (Fig 2 & [0025] disclose that, within the double pole double throw (DPDT) switch, when a first control end is coupled with a second end and a second control end is coupled with a third end (i.e. the DPDT switch is in a second switch-on state), then the first antenna is coupled to the receive end (i.e. a receiving path including a low noise amplifier) and the second antenna is coupled to the transmit end (i.e. a transmitting path including a power amplifier).);
wherein when the switch in each first processing unit of the plurality of first processing units is in the first switch-on state, the processor is configured to send the first signal to the first antenna array and receive a fifth signal from the second antenna array (Fig 2 & [0025] disclose that when the DPDT switch has a first control end that is coupled with a first end and a second control end that is coupled with a fourth end, then the first antenna operates as a transmitting antenna (i.e. sends a first signal) and a the second antenna operates as a receiving antenna (i.e. receives a fifth signal). Note that although Song only teaches of a single transceiver path with two antennas, Song is only used to teach how the switches disclosed by Montalvo could be substituted by DPDT switches in Song to connect to two different antennas and perform the switching as discussed above. Substituting each switch in Montalvo with the DPDT switch in Song, and placing all the DPDT switches in the first switch-on sate discloses how the processor in Montalvo can be configured to send the first signal to the first antenna array and receive a fifth signal from the second antenna array.); and
wherein when the switch in each first processing unit of the plurality of first processing units is in the second switch-on state, the processor is configured to send the second signal to the second antenna array and receive a sixth signal from the first antenna array (Fig 2 & [0025] disclose that when the DPDT switch has a first control end that is coupled with a second end and a second control end that is coupled with a third end, then the second antenna operates as a transmitting antenna (i.e. sends a second signal) and a the first antenna operates as a receiving antenna (i.e. receives a sixth signal). Note that although Song only teaches of a single transceiver path with two antennas, Song is only used to teach how the switches disclosed by Montalvo could be substituted by DPDT switches in Song to connect to two different antennas and perform the switching as discussed above. Substituting each switch in Montalvo with the DPDT switch in Song, and placing all the DPDT switches in the second switch-on sate discloses how the processor in Montalvo can be configured to send the second signal to the second antenna array and receive a sixth signal from the first antenna array.).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to have a millimeter wave antenna circuit, comprising:
a first antenna array; a second antenna array; and a processor; wherein the first antenna array comprises N first antennas, and the second antenna array comprises M second antennas, wherein N is greater than M; wherein the processor comprises a plurality of first processing units, each of the N first antennas is connected to a first processing unit in the plurality of first processing units in a one-to-one correspondence, each of the M second antennas is connected to different first processing units in the plurality of first processing units, and each first processing unit in the plurality of first processing units comprises a power amplifier, a low noise amplifier, and a switch; wherein the processor is configured to send a first signal to the first antenna array by using one first processing unit connected to one of the N first antennas; wherein the processor is configured to send a second signal to the second antenna array using one first processing unit connected to one of the M second antennas; wherein the first antenna array is configured to radiate a first millimeter wave signal based on the first signal; wherein the second antenna array is configured to radiate a second millimeter wave signal based on the second signal, wherein each first processing unit in the plurality of first processing units comprises a transmitting path and a receiving path, each transmitting path comprises a corresponding power amplifier, each receiving path comprises a corresponding low noise amplifier, as disclosed by Montalvo, wherein a switch is a double-pole double throw switch; and when the switch in each first processing unit of the plurality of first processing units is in a first switch-on state, each corresponding power amplifier in each corresponding transmitting path is connected to a corresponding first antenna and each corresponding low noise amplifier in each corresponding receiving path is connected to a corresponding second antenna, when the switch in each first processing unit of the plurality of first processing units is in a second switch-on state, each corresponding power amplifier in each corresponding transmitting path is connected to the corresponding second antenna and each corresponding low noise amplifier in each corresponding receiving path is connected to the corresponding first antenna, wherein when the switch in each first processing unit of the plurality of first processing units is in the first switch-on state the processor is configured to send the first signal to the first antenna array and receive a fifth signal from the second antenna array; and wherein when the switch in each first processing unit of the plurality of first processing units is in the second switch-on state, the processor is configured to send the second signal to the second antenna array and receive a sixth signal from the first antenna array, as further taught by Song. The motivation to do so would be to have a millimeter wave antenna circuit with a double pole double throw switch control switching between a first array of antennas transmitting a first signal and a second array of antennas receiving and low noise amplifying a second signal, or second array of antennas transmitting a second signal and a first array of antennas receiving and low noise amplifying a first signal so that only one antenna array is transmitting or receiving at any point in time which could allow for a single shared high power amplifier transmit chain and a single LNA receive chain for the first and second antenna arrays.
Regarding claim 2, Montalvo in view of Corman and Song disclose the millimeter wave antenna circuit according to claim 1.
Montalvo discloses wherein each first processing unit in the plurality of first processing units further comprises a corresponding phase shifter, and each phase shifter is configured to adjust a phase of an input signal received by the corresponding first processing unit (Fig 2, Fig 4 & Col 9, lines 24-67 and col 10, lines 1-5 disclose details of the transceiver processing units of transceiver array 230 (i.e. the each first processing units). Each first transceiver processing unit of the plurality of transceiver processing units in transceiver array 230 comprises a digital TX adjuster 432 that may be configured to receive an input signal and generate an output signal by adjusting/modifying the phase of the input signal (i.e. a phase shifter) received by the first transceiver processing unit.);
wherein the processor is configured to obtain a third signal by using the corresponding phase shifter in a first target processing unit (Fig 2, fig 5, fig 6 & col 14, lines 36-62 disclose that a broad “processor” including transceiver processing unit 11 (i.e. a first target transceiver processing unit) can be configured to output a third signal that phase adjusts an input signal to transceiver processing unit 11.).);
wherein the processor is configured to obtain a fourth signal by using the corresponding phase shifter in a second target processing unit (Fig 2, fig 5, fig 6 & col 14, lines 36-62 disclose that a broad “processor” including transceiver processing unit 12 (i.e. a second target processing unit) can be configured to output a fourth signal that phase adjusts an input signal to transceiver processing unit 12.).); and
wherein the first target processing unit is one of the two different first processing units, and the second target processing unit is the other of the two different first processing units (Fig 2, fig 5, fig 6 & col 14, lines 36-62 disclose that first target transceiver processing unit 12 is one of two different first transceiver processing units (i.e. first transceiver processing unit 11 and first transceiver processing unit 12) and second target transceiver processing unit 12 is the other of the two different first transceiver processing units.).
Montalvo fails to disclose wherein the phase is opposite between the third signal and the fourth signal; and wherein the second signal is a differential signal obtained by combining the third signal and the fourth signal.
However, Corman teaches wherein the phase is opposite between the third signal and the fourth signal (Fig 12 & [0115] disclose a phased array antenna 1200 where antenna element 1201 is differentially fed with two signals (i.e. a third signal and a fourth signal) that are 180 degrees out of phase.); and
wherein the second signal is a differential signal obtained by combining the third signal and the fourth signal (Fig 1 & [0004] and Fig 12 & [0115] disclose two differentially fed signals (i.e. third signal and fourth signal) may be combined (i.e. forming a second signal).).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to have two transceiver processing units, each capable of providing a different phase shift to an input signal, that produce two different output signals (i.e. third and fourth signals), as disclosed by Montalvo, wherein the phase shift difference applied by the two transceiver processing units is 180 degrees and the two output signals are combined to form a combined output signal (i.e. a second signal), as taught by Corman. The motivation to do so would be to have an antenna circuit where pairs of designated transceiver processing units adjust an input signal to produce two output signals that are 180 degrees out-of-phase that can be combined to form a differentially combined signal to feed into corresponding antenna elements of an antenna array to reduce common noise or interference present in the two transmit paths of paired transceivers.
Regarding claim 3, Montalvo in view of Corman and Song disclose the millimeter wave antenna circuit according to claim 1.
Montalvo discloses wherein a first processing unit connected to the first antenna array is one of the two different first processing units (Fig 2, fig 5, fig 6 & col 14, lines 36-62 disclose that first target transceiver processing unit 11 is one of two different first transceiver processing units (i.e. first transceiver processing unit 11 and first transceiver processing unit 12) that is connected to antenna element 11 of the first antenna array.).
Regarding claim 4, Montalvo in view of Corman and Song disclose the millimeter wave antenna circuit according to claim 3.
Montalvo fails to disclose wherein the processor is configured to send the first signal to the first antenna array in a first time period and send the second signal to the second antenna array in a second time period.
However, Corman teaches wherein the processor is configured to send the first signal to the first antenna array in a first time period and send the second signal to the second antenna array in a second time period ([0284] discloses a satellite system where only 4 colors are transmitted at a first time while 6 colors are transmitted at a second time. This scenario may be accomplished by sending a first signal to a first antenna array of the satellite in a first time period and sending a second signal to a second array of the satellite in a second time period.).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to have the millimeter wave antenna circuit of claim 3, as disclosed by Montalvo in view of Corman, wherein the processor is configured to send the first signal to the first antenna array in a first time period and send the second signal to the second antenna array in a second, as taught by Corman. The motivation to do so would be to have an antenna circuit for a satellite systems that can transmit a first beam from a first antenna array covering a first geographical area during a first time period, and then send a second beam from a second antenna array covering a second geographical area so that the satellite system can track users that move from the first geographical area to the second geographical area over time.
Regarding claim 7, Montalvo in view of Corman and Song disclose the millimeter wave antenna circuit according to claim 4.
Montalvo discloses wherein a quantity of the plurality of first processing units is greater than or equal to N and greater than or equal to 2*M (Fig 2, col 7, lines 50-67 & col 8, lines 1-9 disclose one example where antenna array 250 is broken up into N columns and K rows. An alternative antenna array 250 example would be antenna array broken up into a first antenna array consisting of antenna elements 11 through 1K (i.e. K first antennas), a second antenna array consisting of antenna elements 21 through N1 (i.e. N-1 second antennas), and K-1 more antenna arrays consisting of antenna elements 22 through N2, 23 through N3,…, and 2K through NK. Fig 2. & col 8, lines 27-51 disclose that each antenna element is connected to a designated/different/respective (i.e. in one-to-one correspondence with) first transceiver processing unit. Thus, there are a total of N*K antennas and first transceiver processing units. For scenarios where N=3 and K=3, there would be N*K=9 total antennas and first transceiver processing units. Thus, 9 total first transceiver processing units is greater than K=3 first antennas and is also greater than 2*(N-1)=4 second antennas.).
Regarding claim 11, Montalvo discloses a millimeter wave antenna circuit (Fig 2, fig 3 & col 2, lines 3-10 disclose a system configured to implement per-antenna beamforming. Col 4, lines 33-59 discloses that the per-antenna beamforming may take the form of an entirely hardware, software or combined hardware and software embodiment that may be a circuit. Fig 6 & col 13, lines 37-51 disclose that the per carrier beamforming may take on any frequency depending on the wireless technology of the RF system. Col 1, lines 14-16 disclose that RF systems transmit and receive electromagnetic waves in the RF range between 3 kHz and 300 GHz (i.e. including millimeter wave between 30 GHz and 300 GHz).), comprising:
a first antenna array (Fig 2, col 7, lines 50-67 & col 8, lines 1-9 disclose an antenna array 250 that may be broken up into multiple “antenna cells” 260-1 through 260-N, each consisting of an array of K antenna elements. Antenna cell 260-1 represents a first antenna array consisting of antenna elements 11 through 1K.);
a second antenna array (Fig 2, col 7, lines 50-67 & col 8, lines 1-9 disclose one example where antenna array 250 is broken up into N columns and K rows. An alternative antenna array 250 example would be an antenna array broken up into a first antenna array consisting of antenna elements 11 through 1K, a second antenna array consisting of antenna elements 21 through N1, and K-1 more antenna arrays consisting of antenna elements 22 through N2, 23 through N3,…, and 2K through NK.); and
a processor (Fig 7 & col 16, lines 4-11 disclose processing system 700, including processor 702. Fig 2, col 16, lines 57-67 disclose that any of the processing elements (e.g. the transceivers of transceiver array 230) that can communicate with processing system 700 should be construed as being encompassed within a broad “processor”. Thus, each transceiver of transceiver array 230 can represent part of the broad “processor” (i.e. a processing unit). For the purpose of this review, the transceivers of transceiver array will be termed “transceiver processing units”, and the processing system 700 plus the transceiver processing units comprise the broad “processor”.); wherein:
the first antenna array comprises N first antennas, and the second antenna array comprises M second antennas, wherein N is greater than M (Fig 2, col 7, lines 50-67 & col 8, lines 1-9 disclose a first antenna array consisting of antenna cell 260-1 comprising K first elements. Based on the second array example discussed above, the second antenna array comprises N-1 second antennas consisting of antenna elements 21 through N1. In a scenario where, for example, N=5 and K=5, then the first antenna array consists of K=5 antennas which is greater than the second antenna array consisting of N-1=4 antenna elements.);
the processor comprises a plurality of first processing units (Fig 7 & col 16, lines 4-11 and Fig 2, col 16, lines 57-67 disclose a broad “processor” comprising a plurality of first transceiver processing units of transceiver array 230, each making up part of the broad “processor”.), each of the N first antennas is connected to a first processing unit in the plurality of first processing units in a one-to-one correspondence (Fig 2. & col 8, lines 27-51 disclose that each of the K first antennas 11 through 1K are connected to a designated/different/respective (i.e. in one-to-one correspondence with) first transceiver processing unit 11 through 1K, of the plurality of first processing units of transceiver array 230.), each of the M second antennas is connected to different first processing units in the plurality of first processing units (Fig 2. & col 8, lines 27-51 disclose that each of the N-1 second antennas 21 through N1 are connected to different designated first transceiver processing units 21 through N1, of the plurality of first transceiver processing units of transceiver array 230.), and each first processing unit in the plurality of first processing units comprises a power amplifier (Fig 2 & col 9, lines 4-23 and fig 5, col 12, lines 11-18 disclose that each of the first transceiver processing units, of the plurality of transceiver processing units in transceiver array 230, in transceiver cells 240 may include a power amplifier.), a low noise amplifier (Fig 4, col 10, lines 40-51 disclose that each transceiver processing units may include a low-noise amplifier between antenna element 450 and ADC 436.), a switch (Fig 4, col 9, lines 51-61 disclose that each transceiver processing unit may include a switch.) and a phase shifter, and the phase shifter is configured to adjust a phase of an input signal received by the first processing unit (Fig 2, Fig 4 & Col 9, lines 24-67 and col 10, lines 1-5 disclose details of the transceiver processing units of transceiver array 230 (i.e. the each first processing units). Each first transceiver processing unit of the plurality of transceiver processing units in transceiver array 230 comprises a digital TX adjuster 432 that may be configured to receive an input signal and generate an output signal by adjusting/modifying the phase of the input signal (i.e. a phase shifter) received by the first transceiver processing unit.);
the processor is configured to send a first signal to the first antenna array by using one first processing unit connected to one of the N first antennas (Fig 2, fig 4 & col 9, lines 24-67 and col 10, lines 1-39 disclose transceiver processing unit 11 of fig 2 as part of the broad “processor” is configured to output a first phase and amplitude adjusted signal that is provided to antenna 11 of the first antenna array consisting of K antennas 11 through 1K. (i.e. one of the K first antennas).);
the processor is configured to send a second signal to the second antenna array using one first processing unit connected to one of the M second antennas (Fig 2, fig 4 & col 9, lines 24-67 and col 10, lines 1-39 disclose that a transceiver processing unit (e.g. transceiver processing unit 21 of fig 2) as part of the broad “processor” is configured to output a phase and amplitude adjusted signal that is provided to antenna 21 of the second antenna array consisting of N-1 antennas 21 through N1. (i.e. one of the N-1 second antennas.).);
wherein each first processing unit in the plurality of first processing units comprises a transmitting path and a receiving path, each transmitting path comprises a corresponding power amplifier, each receiving path comprises a corresponding low noise amplifier (Fig 2, fig 4 and col 9, lines 36-41 & col 10, lines 29-36 & lines 44-51 disclose that each channel of each transceiver array 230 comprises a TX path including a power amplifier and an Rx path including a low noise amplifier.);
wherein the processor sending comprises: the processor obtaining a third signal by using the phase shifter in a first target processing unit (Fig 2, fig 5, fig 6 & col 14, lines 36-62 disclose that a broad “processor” including transceiver processing unit 11 (i.e. a first target transceiver processing unit) can be configured to output a third signal that phase adjusts an input signal to transceiver processing unit 11.);
the processor obtaining a fourth signal by using the phase shifter in a second target processing unit (Fig 2, fig 5, fig 6 & col 14, lines 36-62 disclose that a broad “processor” including transceiver processing unit 12 (i.e. a second target processing unit) can be configured to output a fourth signal that phase adjusts an input signal to transceiver processing unit 12.); and
wherein the first target processing unit is one of the two different first processing units, and the second target processing unit is the other of the two different first processing units (Fig 2, fig 5, fig 6 & col 14, lines 36-62 disclose that first target transceiver processing unit 12 is one of two different first transceiver processing units (i.e. first transceiver processing unit 11 and first transceiver processing unit 12) and second target transceiver processing unit 12 is the other of the two different first transceiver processing units.);
wherein the first antenna array is configured to radiate a first millimeter wave signal based on the first signal (Col 8, lines 10-26 disclose that any plurality of antenna elements of antenna array 250 may be configured to transmit RF signals. Fig 6 & col 18, lines 29-55 disclose an example where a first RF signal is wirelessly transmitted by antenna element 11 based on a first signal C1 (e.g. a first antenna array consisting of antenna elements 11 through 1K is configured to radiate a first RF signal based on first phase and amplitude adjusted signal that is provided to antenna 11). Fig 6 & col 13, lines 37-51 disclose that first signal C1 may be of any frequency (e.g. including being a first millimeter wave signal between 30 GHz and 300 GHz).); and
wherein the second antenna array is configured to radiate a second millimeter wave signal based on the second signal (Col 8, lines 10-26 disclose that any plurality of antenna elements of antenna array 250 may be configured to transmit RF signals. Fig 6 & col 18, lines 29-55 disclose an example where a second RF signal is wirelessly transmitted by an antenna element (e.g. antenna element 21) based on a second signal C1 (e.g. a first antenna array consisting of antenna elements 21 through N1 is configured to radiate a second RF signal based on second phase and amplitude adjusted signal that is provided to antenna 21). Fig 6 & col 13, lines 37-51 disclose that second signal C1 may be of any frequency (e.g. including being a second millimeter wave signal between 30 GHz and 300 GHz).);
Montalvo fails to disclose wherein the connecting of each of the M second antennas is a differential connection to two different first processing units; and wherein the processor sending, through differential feeding, the second signal to the second antenna array by using two different first processing units connected to one of the M second antennas comprises: wherein a phase is opposite between the third signal and the fourth signal; and wherein the second signal is a differential signal obtained by combining the third signal and the fourth signal.
However, Corman teaches wherein the connecting of each of the M second antennas is a differential connection to two different first processing units; and wherein the processor sending, through differential feeding, the second signal to the second antenna array by using two different first processing units connected to one of the M second antennas comprises: wherein a phase is opposite between the third signal and the fourth signal (Fig 12 & [0115] disclose a phased array antenna 1200 where antenna element 1201 is differentially fed with two signals that are 180 degrees out of phase.); and wherein the second signal is a differential signal obtained by combining the third signal and the fourth signal (Fig 1 & [0004] and Fig 12 & [0115] disclose two differentially fed signals (i.e. third signal and fourth signal) may be combined (i.e. forming a second signal).).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to substitute the single connections of each of the M second antennas to different first processing units, where the processor sends the second signal to the second antenna array using one first processing unit connected to one of the M second antennas, as disclosed by Montalvo, with the differential feeding connections of two signals with opposite phases combined to form the second signal sent to the second antenna array, as taught by Corman, resulting in connections of each of the M second antennas to two different first processing units, where the processor sends the second signal to the second array through differential feeding by using two different first processing units connected to one of the M second antennas. The motivation to do so would be to have an antenna circuit where pairs of designated transceiver process units adjust an input signal to produce two output signals that are 180 degrees out-of-phase to differentially feed into corresponding antenna elements of an antenna array to reduce common noise or interference present in the two transmit paths of paired transceivers.
Montalvo fails to disclose but Song further teaches wherein a switch is a double-pole double throw switch (Fig 2 & [0024]-[0025] disclose a double pole double throw switch.); and
when the switch in each first processing unit of the plurality of first processing units is in a first switch-on state, each corresponding power amplifier in each corresponding transmitting path is connected to a corresponding first antenna and each corresponding low noise amplifier in each corresponding receiving path is connected to a corresponding second antenna (Fig 2 & [0025] disclose that, within the double pole double throw (DPDT) switch, when a first control end is coupled with a first end and a second control end is coupled with a fourth end (i.e. the DPDT switch is in a first switch-on state), then the a first antenna is coupled to a transmit end (i.e. a transmitting path including a power amplifier) and a second antenna is coupled to a receive end (i.e. a receiving path including a low noise amplifier).),
when the switch in each first processing unit of the plurality of first processing units is in a second switch-on state, each corresponding power amplifier in each corresponding transmitting path is connected to the corresponding second antenna and each corresponding low noise amplifier in each corresponding receiving path is connected to the corresponding first antenna (Fig 2 & [0025] disclose that, within the double pole double throw (DPDT) switch, when a first control end is coupled with a second end and a second control end is coupled with a third end (i.e. the DPDT switch is in a second switch-on state), then the first antenna is coupled to the receive end (i.e. a receiving path including a low noise amplifier) and the second antenna is coupled to a transmit end (i.e. a transmitting path including a power amplifier).);
wherein when the switch in each first processing unit of the plurality of first processing units is in the first switch-on state, the processor is configured to send the first signal to the first antenna array and receive a fifth signal from the second antenna array (Fig 2 & [0025] disclose that when the DPDT switch has a first control end that is coupled with a first end and a second control end that is coupled with a fourth end, then the first antenna operates as a transmitting antenna (i.e. sends a first signal) and a the second antenna operates as a receiving antenna (i.e. receives a fifth signal). Note that although Song only teaches of a single transceiver path with two antennas, Song is only used to teach how the switches disclosed by Montalvo could be substituted by DPDT switches in Song to connect to two different antennas and perform the switching as discussed above. Substituting each switch in Montalvo with the DPDT switch in Song, and placing all the DPDT switches in the first switch-on sate discloses how the processor in Montalvo can be configured to send the first signal to the first antenna array and receive a fifth signal from the second antenna array.);
wherein when the switch in each first processing unit of the plurality of first processing units is in the second switch-on state, the processor is configured to send the second signal to the second antenna array and receive a sixth signal from the first antenna array (Fig 2 & [0025] disclose that when the DPDT switch has a first control end that is coupled with a second end and a second control end that is coupled with a third end, then the second antenna operates as a transmitting antenna (i.e. sends a second signal) and a the first antenna operates as a receiving antenna (i.e. receives a sixth signal). Note that although Song only teaches of a single transceiver path with two antennas, Song is only used to teach how the switches disclosed by Montalvo could be substituted by DPDT switches in Song to connect to two different antennas and perform the switching as discussed above. Substituting each switch in Montalvo with the DPDT switch in Song, and placing all the DPDT switches in the second switch-on sate discloses how the processor in Montalvo can be configured to send the second signal to the second antenna array and receive a sixth signal from the first antenna array.).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to have a millimeter wave antenna circuit, comprising:
a first antenna array; a second antenna array; and a processor; wherein the first antenna array comprises N first antennas, and the second antenna array comprises M second antennas, wherein N is greater than M; wherein the processor comprises a plurality of first processing units, each of the N first antennas is connected to a first processing unit in the plurality of first processing units in a one-to-one correspondence, each of the M second antennas is connected to different first processing units in the plurality of first processing units, and each first processing unit in the plurality of first processing units comprises a power amplifier, a low noise amplifier, and a switch; wherein the processor is configured to send a first signal to the first antenna array by using one first processing unit connected to one of the N first antennas; wherein the processor is configured to send a second signal to the second antenna array using one first processing unit connected to one of the M second antennas; wherein the first antenna array is configured to radiate a first millimeter wave signal based on the first signal; wherein the second antenna array is configured to radiate a second millimeter wave signal based on the second signal, wherein each first processing unit in the plurality of first processing units comprises a transmitting path and a receiving path, each transmitting path comprises a corresponding power amplifier, each receiving path comprises a corresponding low noise amplifier, as disclosed by Montalvo, wherein a switch is a double-pole double throw switch; and when the switch in each first processing unit of the plurality of first processing units is in a first switch-on state, each corresponding power amplifier in each corresponding transmitting path is connected to a corresponding first antenna and each corresponding low noise amplifier in each corresponding receiving path is connected to a corresponding second antenna, when the switch in each first processing unit of the plurality of first processing units is in a second switch-on state, each corresponding power amplifier in each corresponding transmitting path is connected to the corresponding second antenna and each corresponding low noise amplifier in each corresponding receiving path is connected to the corresponding first antenna, wherein when the switch in each first processing unit of the plurality of first processing units is in the first switch-on state the processor is configured to send the first signal to the first antenna array and receive a fifth signal from the second antenna array; and wherein when the switch in each first processing unit of the plurality of first processing units is in the second switch-on state, the processor is configured to send the second signal to the second antenna array and receive a sixth signal from the first antenna array, as further taught by Song. The motivation to do so would be to have a millimeter wave antenna circuit with a double pole double throw switch control switching between a first array of antennas transmitting a first signal and a second array of antennas receiving and low noise amplifying a second signal, or second array of antennas transmitting a second signal and a first array of antennas receiving and low noise amplifying a first signal so that only one antenna array is transmitting or receiving at any point in time which could allow for a single shared high power amplifier transmit chain and a single LNA receive chain for the first and second antenna arrays.
Regarding claim 12, Montalvo in view of Corman and Song disclose the millimeter wave antenna circuit according to claim 11.
Montalvo discloses wherein a first processing unit connected to the first antenna array is one of the two different first processing units (Fig 2, fig 5, fig 6 & col 14, lines 36-62 disclose that first target transceiver processing unit 11 is one of two different first transceiver processing units (i.e. first transceiver processing unit 11 and first transceiver processing unit 12) that is connected to antenna element 11 of the first antenna array.).
Regarding claim 13, Montalvo in view of Corman and Song disclose the millimeter wave antenna circuit according to claim 12
Montalvo fails to disclose wherein the processor is configured to send the first signal to the first antenna array in a first time period and send the second signal to the second antenna array in a second time period.
However, Corman teaches wherein the processor is configured to send the first signal to the first antenna array in a first time period and send the second signal to the second antenna array in a second time period ([0284] discloses a satellite system where only 4 colors are transmitted at a first time while 6 colors are transmitted at a second time. This scenario may be accomplished by sending a first signal to a first antenna array of the satellite in a first time period and sending a second signal to a second array of the satellite in a second time period.).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to have the millimeter wave antenna circuit of claim 12, as disclosed by Montalvo in view of Corman, wherein the processor is configured to send the first signal to the first antenna array in a first time period and send the second signal to the second antenna array in a second, as taught by Corman. The motivation to do so would be to have an antenna circuit for a satellite systems that can transmit a first beam from a first antenna array covering a first geographical area during a first time period, and then send a second beam from a second antenna array covering a second geographical area so that the satellite system can track users that move from the first geographical area to the second geographical area over time.
Regarding claim 16, The millimeter wave module antenna circuit according to claim 13.
Montalvo discloses wherein a quantity of the plurality of first processing units is greater than or equal to N and greater than or equal to 2*M (Fig 2, col 7, lines 50-67 & col 8, lines 1-9 disclose one example where antenna array 250 is broken up into N columns and K rows. An alternative antenna array 250 example would be antenna array broken up into a first antenna array consisting of antenna elements 11 through 1K (i.e. K first antennas), a second antenna array consisting of antenna elements 21 through N1 (i.e. N-1 second antennas), and K-1 more antenna arrays consisting of antenna elements 22 through N2, 23 through N3,…, and 2K through NK. Fig 2. & col 8, lines 27-51 disclose that each antenna element is connected to a designated/different/respective (i.e. in one-to-one correspondence with) first transceiver processing unit. Thus, there are a total of N*K antennas and first transceiver processing units. For scenarios where N=3 and K=3, there would be N*K=9 total antennas and first transceiver processing units. Thus, 9 total first transceiver processing units is greater than K=3 first antennas and is also greater than 2*(N-1)=4 second antennas.).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Montalvo et al. (US 11095350)(herein after “Montalvo”) in view of Corman et al. (US 2019/0334253)(herein after “Corman”) and Song et al. (US 2018/0048054)(herein after “Song”), as applied to claim 1, and further in view of Ye et al. (US 2023/0039947)(herein after “Ye”).
Regarding claim 9, Montalvo in view of Corman and Song disclose the millimeter wave antenna circuit according to claim 1.
Montalvo fails to disclose a terminal device, comprising: a body, wherein one side of the body comprises a display, and the other side of the body comprises a backplate, and the display and the backplate are connected through a middle frame; and wherein the display, the backplate, and the middle frame form an accommodating cavity, and the millimeter wave module antenna circuit according to claim 1 is disposed in the accommodating cavity,
However, Ye further teaches a terminal device, comprising: a body, wherein one side of the body comprises a display, and the other side of the body comprises a backplate, and the display and the backplate are connected through a middle frame (Fig 1, [0001], [0035]-[0037] disclose a display device (i.e. terminal device) comprising a display screen shell (i.e. a body) with display panel 300 on one side, backplate 500 on the other side, and display panel 300 and backplate 500 are connected through middle frame 100.); and wherein the display, the backplate, and the middle frame form an accommodating cavity, and circuitry is disposed in the accommodating cavity (fig 1 & [0042]-[0043] disclose a receiving cavity 240 within the display screen shell formed by display panel 300, backplate 500 and middle frame 100 where an infrared circuit board is disposed.).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to have the millimeter wave antenna circuit according to claim 1, as disclosed by Montalvo in view of Corman and Song, disposed in the accommodating cavity of a terminal device, comprising: a body, wherein one side of the body comprises a display, and the other side of the body comprises a backplate, and the display and the backplate are connected through a middle frame; and wherein the display, the backplate, and the middle frame form an accommodating cavity, as further taught by Ye. The motivation to do so would be to have display a device designed to accommodate an millimeter wave antenna circuit for providing connectivity with a 5G base station system that could be used as part of an outdoor device (e.g. kiosk) that is within line-of-site of the 5G base station system.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Montalvo et al. (US 11095350)(herein after “Montalvo”) in view of Corman et al. (US 2019/0334253)(herein after “Corman”) and Song et al. (US 2018/0048054)(herein after “Song”) and Ye et al. (US 2023/0039947)(herein after “Ye”), as applied to claim 9, and further in view of Zhang et al. (WO 2021/057557)(herein after “Zhang”).
Regarding claim 10, Montalvo in view of Corman and Song and Ye disclose the terminal device according to claim 9.
Montalvo fails to disclose wherein the first antenna array is disposed in a plane in which the backplate is located, and the second antenna array is disposed in any plane in which the middle frame is located; or wherein the first antenna array and the second antenna array are respectively disposed in two different planes in which the middle frame is located.
However, Zhang further teaches wherein the first antenna array is disposed in a plane in which the backplate is located, and the second antenna array is disposed in any plane in which the middle frame is located; or wherein the first antenna array and the second antenna array are respectively disposed in two different planes in which the middle frame is located (Fig 2, [0089] & [0093] disclose four element antenna radiators (i.e. four element antenna arrays) where a second antenna radiator is located on a back cover 70 (i.e. backplate) in one horizontal plane and third antenna radiator may be located on a middle frame 30 in a different horizontal plane.).
Therefore, it would have been obvious to someone having ordinary skill in the art prior to the effective filing date of the claimed invention to have the terminal device of claim 9, as disclosed by Montalvo in view of Corman and Song and Ye, wherein the first antenna array is disposed in a plane in which the backplate is located, and the second antenna array is disposed in any plane in which the middle frame is located; or wherein the first antenna array and the second antenna array are respectively disposed in two different planes in which the middle frame is located, as further taught by Zhang. The motivation to do so would be to have a display device designed to accommodate two different four element antenna radiators located in different horizontal planes in order, to reduce interference between antenna radiators, providing connectivity with a 5G base station system that could be used as part of an outdoor device (e.g. kiosk) that is within line-of-site of the 5G base station system.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Desclos et al. (US 7123209) discloses Low-Profile, Multi-Frequency Differential Antenna Structures.
Huang et al. (US 2022/0085512) discloses an Antenna Element and Electronic Device.
Gurbuz et al. (US 2021/0104821) discloses a Low-Complexity Full-Duplex Radio System with Enhanced Digital Self-Interference Cancellation
Gao et al. (US 2015/0334726) discloses a Wireless Communication Method Utilizing a Large-Scale Antenna Array.
Casas et al. (US 2004/0174299) discloses Wireless Communication and Beam Forming with Passive Beamformers.
Garfinkle et al. (US 7474263) discloses an Electronically Scanned Antenna. Hosoda et al. (US 2020/0266772) discloses a Power Amplifier Circuit and Antenna Device.
Yu et al. (US 2018/0309186) discloses an Antenna Array Suitable for 5G Mobile Terminal Devices.
Applicant's amendment necessitated the new grounds of rejections presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JAMES P SEYMOUR/Examiner, Art Unit 2419
/Nishant Divecha/Supervisory Patent Examiner, Art Unit 2419
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