DETAILED ACTION
Response to Arguments
Applicant’s arguments, with respect to the drawing objection have been fully considered and are persuasive. The drawing objection has been withdrawn.
Applicant’s arguments in regard to claim 15 12/29/2025 have been fully considered and are persuasive. Therefore, the 35 U.S.C 112(b) rejection has been withdrawn.
Applicant’s arguments regarding claim 1 filed 12/29/2025 have been fully considered but are not persuasive.
Applicant argues Ding et al. (CN 110265583 A; hereinafter “Ding) fails to teach the following:
“wherein the third isolation pattern and the planarization layer are provided in a same layer and with a same material”.
The Examiner respectfully disagrees with this assertion. Applicant argues “the protection pattern 1035 cannot be considered as an isolation pattern, and is an independent layer covered on the separation pillar instead”. In response to Applicant's arguments, intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable to performing the intended use, and then it meets the claim. As the protective pattern 1035 is constructed of polyimide a known insulating material and would further serve to isolate the underlying structure from any element placed above it. Therefore the Examiner maintains that a protection pattern 1035 functions as a third isolation pattern as described in the claims.
Further, the Examiner respectfully disagrees with the assertion Qin et al. (WO2021036411A1; hereinafter “Qin”) does not teach the limitation the third isolation pattern and the planarization layer are provided in a same layer and with a same material. While no reason was specified the examiner notes that the elements mapped as the third isolation pattern and the planarization layer in Qin are both formed from the passivation layer 14.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 9, 11 and 13-16 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In regard to claim 9, the limitation states “and then forming a third isolation pattern by etching the first isolation layer” in lines 10-11. This limitation directly contradict information found in the instant application specification that states “a third isolation layer is formed in a patterning process of forming the planarization layer, and the first isolation pattern is formed by etching the first isolation layer” in paragraph 17. Therefore, the current explanation of the manufacturing method of the third isolation layer in the specification does not clearly reflect the method as described in the claim limitation.
Claims 11 and 13-16 are rejected due to depending on claim 9.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9, 1 1, 13-14, and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Qin et al. (WO2021036411A1; hereinafter “Qin”), wherein US 2021/0408511 A1 is used as a translation.
In regard to claim 9, Qin teaches a preparation method of a light-emitting panel, comprising:
providing a substrate (a substrate 10 is provided in step 110) (Fig. 2, Fig. 3 and paragraphs 30), wherein the substrate has a light-emitting area and an isolation area adjacent to the light-emitting area (a display region 1a and a non-display region 20 is shown on the substrate in Fig. 4) (Fig. 4 and paragraph 29);
forming a first isolation pattern (a second metal layer 102 formed and etched in the non-display region 20) and a second isolation pattern (a third metal layer 103 formed and etched in the non-display region 20) sequentially on one side of the substrate and in the isolation area (the second and third metal layers 102 and 103 are shown disposed on one another Fig. 4) (Fig. 4 and paragraph 44), wherein an orthographic projection of the first isolation pattern on the substrate is located within an orthographic projection of the second isolation pattern on the substrate (the orthographic projections of the second and third metal layers 102 and 103 are located within one another as shown in Fig. 4);
forming a third isolation layer (the passivation layer 14 formed in the supporting portion 401) and on one side of the second isolation pattern away from the substrate (as shown in Fig. 16 the passivation layer 14 formed in the supporting portion 401 is disposed on the topside of the metal layer 103) (Fig. 4, Fig. 16 and paragraph 58), and then forming a fourth isolation pattern (the layer of the partitioning portion 402 formed in the same process as the first electrode 15) on one side of the third isolation layer away from the substrate, and then forming a third isolation pattern by etching the third isolation layer (the supporting portion 211 is etched to form the second isolation structure 40 which contains the supporting portion 401) (Fig. 5, Fig. 6 and paragraph 52),
wherein an orthographic projection of the third isolation pattern on the substrate is located within an orthographic projection of the fourth isolation pattern on the substrate (due to the layering of components the orthographic projections of the passivation layer 14 formed in the supporting portion 401 and the layer of the partitioning portion 402 formed in the same process as the first electrode 15 are within one another) (Fig. 16), and the orthographic projection of the third isolation pattern on the substrate is located within the orthographic projection of the second isolation pattern on the substrate (due to the layering of components the orthographic components of the orthographic projections of the passivation layer 14 formed in the supporting portion 401 and third metal layer 103 formed and etched in the non-display region 20 are within one another) (Fig. 16), wherein the preparation method further comprises:
forming an active layer (a semiconductor layer 19) (Fig. 4 and paragraph 74), a gate insulation layer (a gate insulating layer 21) and a gate electrode (a gate electrode 22) on one side of the substrate and in the light-emitting area (the gate insulating layer 21 and gate electrode 22 are shown on the substrate 10 and in the display region 1a) (Fig. 1 and paragraph 41), wherein the gate insulation layer is located between the active layer and the gate electrode (the gate insulation layer 21 is shown between the semiconductor layer 19 and the gate electrode 22 in Fig. 4);
forming an interlayer dielectric layer (a capacitor insulating layer 32) on one side of the active layer or the gate electrode away from the substrate (Fig. 4 and paragraph 41), and forming a first via hole on the interlayer dielectric layer (through holes are penetrating through the gate insulating layer 21 and the capacitor insulating layer 32) (paragraph 41), wherein the first via hole is connected to the active layer (the through holes are for the first through third metal layers 101-103 and therefore would be connected to the semiconductor layer 19) (Fig. 4 and paragraph 41);
forming a source electrode (a source electrode 23) and a drain electrode (a drain electrode 24 ) on one side of the interlayer dielectric layer away from the substrate (the source and drain electrode are formed on the topside of the capacitor insulating layer 32 as shown in Fig. 4) (Fig. 4 and paragraph 44), wherein the source electrode and the drain electrode are connected to the active layer through the first via hole (the through holes are for the first through third metal layers 101-103 and therefore would also house the source and drain electrodes 23 and 24) (Fig. 4 and paragraph 44);
forming a planarization layer (a passivation layer 14) on one side of the source electrode and the drain electrode away from the substrate (the passivation layer 14 is disposed on the source electrode 23, the drain electrode 24 is formed on the source electrode 23 and the drain electrode 24) (Fig. 11 and paragraph 75), and forming a second via hole on the planarization layer, wherein the second via hole is connected to the source electrode or the drain electrode (passivation layer 14 has a through holes exposing the drain electrodes 24, and the first electrodes 15) (Fig. 5 and paragraph 77);
forming a first electrode (a first electrode 15) on one side of the planarization layer away from the substrate (Fig. 11 and paragraph 77), wherein the first electrode is connected to the source electrode or the drain electrode through the second via hole (the first electrodes 15 are formed on the passivation layer 14 and the through hole is filled) (Fig. 11 and paragraph 77);
forming a pixel definition layer on one side of the first electrode away from the substrate (a pixel definition layer 16 is disposed on the first electrodes 15) (Fig.7 and paragraph 78), wherein the third isolation layer is formed in a patterning process of forming the planarization layer (the passivation layer 14 forms separate portions in 1a the display region 1a and the supporting portion 401 as the two regions are separated but and contain the same material and layers) (Fig. 16 and paragraph 58).
In regard to claim 11, Qin teaches wherein the first isolation layer and the second isolation pattern are sequentially formed in a patterning process of forming the source electrode and the drain electrode (the second and third metal layers 102 and 103 are form the source and drain electrodes as well as the layers mapped as the first and second isolation layers within the device) (Fig. 3, Fig. 4 and paragraphs 39 and 44).
In regard to claim 13, Qin teaches wherein a sixth isolation pattern (a first metal layer 101 formed in the non-display region 20) is further formed in the patterning process of forming the source electrode and the drain electrode (the first metal layer 101 is used in the source and drain electrodes) (Fig. 4 and paragraph 39 and 44), and the sixth isolation pattern is provided between the substrate and the first isolation pattern (the first metal layer 101 is shown between the second metal layer 102 and the substrate 10 in Fig. 4), and the orthographic projection of the first isolation pattern on the substrate is located within an orthographic projection of the sixth isolation pattern on the substrate (due to the layering of the components the orthographic projections of the first and second metal layers 101 and 102 are shown within one another in Fig. 4).
In regard to claim 14, Qin teaches wherein the fourth isolation pattern is formed in a patterning process of forming the first electrode (the layer of the partitioning portion 402 and a plurality of first electrodes 15 are formed in a same procedure) (Fig. 16 and paragraph 58).
The preparation method of the light-emitting panel according to claim 14, wherein after forming the first electrode and the fourth isolation pattern, the preparation method further comprises: forming a protective layer on the side of the first electrode away from the substrate and on sidewalls of the interlayer dielectric layer, the planarization layer and the first electrode; forming the third isolation pattern by ashing the third isolation layer, so that the orthographic projection of the third isolation pattern on the substrate is located within the orthographic projection of the fourth isolation pattern on the substrate, and the orthographic projection of the third isolation pattern on the substrate is located within the orthographic projection of the second isolation pattern on the substrate
In regard to claim 16, Qin teaches wherein, in the patterning process of forming the pixel definition layer, a fifth isolation pattern (a portion of the pixel definition layer 16 in the tensile stress layer 403 and the pixel definition layer 16) is formed on one side of the fourth isolation layer away from the substrate (the portion of the pixel definition layer 16 in the tensile stress layer 403 and the pixel definition layer 16 are formed in a same procedure) (Fig. 16 and paragraph 58), an orthographic projection of the fifth isolation pattern on the substrate is located within the orthographic projection of the fourth isolation pattern on the substrate (due to the layering of components the orthographic projections of portion of the pixel definition layer 16 in the tensile stress layer 403 and the layer of the partitioning portion 402 formed with plurality of first electrodes 15 are within one another) (Fig. 16), or the orthographic projection of the fourth isolation pattern on the substrate is located within an orthographic projection of the fifth isolation pattern on the substrate.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Deng et al. (CN 110444690 A; hereinafter “Deng”) wherein US 2022/0013601 A1 is used as a translation, in view of Ding et al. (CN 110265583 A; hereinafter “Ding), wherein US 20210028249 A1 is used as a translation.
In regard to claim 1, Deng teaches a light-emitting panel (a display substrate) (Fig .3 and paragraph 28), having a light-emitting area (a display region 101) and an isolation area adjacent to the light-emitting area (the area containing one isolation wall 103 functions as the isolation area) (Fig. 3 and paragraph 28), wherein the light-emitting panel comprises:
a substrate (a base substrate 100) (Fig. 3 and paragraph 28);
a barrier structure (an isolation wall 103) (Fig. 3 and paragraph 28), disposed on one side of the substrate and located in the isolation area (the isolation wall 103 is shown on the topside of the substrate in the aforementioned isolation area) (Fig. 3 and paragraph 28); the barrier structure comprises: a first isolation pattern (a first layer 111 at the bottom of the isolation well 103) (Fig. 3 and paragraph 28), a second isolation pattern (a bottom layer of a second layer 112 that consists of two layers) (Fig. 3 and paragraph 28), a third isolation pattern (an upper layer of the second layer 112 that consists of two layers) and a fourth isolation pattern (the first layer 111 above the second layer 112 that consist of 2 layers) stacked in sequence (Fig. 11 and paragraph 28), the first isolation pattern is closer to the substrate than the fourth isolation pattern (as shown in Fig. 3 first layer 111 at the bottom of the isolation well 103 is closer to the substrate 100 than the first layer 111 above the second layer 112 that consist of 2 layers); an orthographic projection of the first isolation pattern on the substrate is located within an orthographic projection of the second isolation pattern on the substrate (the orthographic projections of the first layer 111 at the bottom of the isolation well is within the orthographic projection of the bottom layer of a second layer 112 that consists of two layers as shown in Fig. 3), and an orthographic projection of the third isolation pattern on the substrate is located within an orthographic projection of the fourth isolation pattern on the substrate (the upper layer of the second layer 112 that consists of two layers orthographic projection is shown with the orthographic projection of the first layer 111 above the second layer 112 that consist of 2 layers in Fig. 3), and the orthographic projection of the third isolation pattern on the substrate is located within the orthographic projection of the second isolation pattern on the substrate (the orthographic projection of the upper layer of the second layer 112 that consists of two layers is shown within the orthographic projection of the lower layer of the second layer 112 that consists of two layers in Fig. 3), each of sub-pixels comprises a thin film transistor (a thin film transistor structure) and a light-emitting unit (the sub-pixel regions contain an anode layer 125, and a pixel definition layer 126, and an organic light emitting material layer 127 in the display region 101 functions as the light emitting unit) (Fig. 3 and paragraphs 43-44), the thin film transistor comprises a gate electrode, a gate insulation layer, an active layer, a source electrode, a drain electrode and a planarization layer (the thin film transistor structure includes an active layer, a first gate insulating layer, a first gate, a source/drain, and a planarization layer 124) (Fig. 3 and paragraphs 37 and 43), the light-emitting unit comprises a first electrode, a pixel definition layer, a light-emitting layer (the sub-pixel regions contain an anode layer 125, and a pixel definition layer 126, and an organic light emitting material layer 127 in the display region 101 functions as the light emitting unit) (Fig. 3 and paragraphs 43-44).
However, Deng does not explicitly teach wherein, in the light-emitting area, the light-emitting panel comprises: a plurality of pixel units arranged in an array, each of the pixel units comprises at least three sub-pixels, wherein the third isolation pattern and the planarization layer are provided in a same layer and with a same material. the light-emitting unit comprises the first electrode, the pixel definition layer, the light-emitting layer and a second electrode, wherein the third isolation pattern and the planarization layer are provided in a same layer and with a same material.
Ding teaches a display panel (a display panel as taught in Fig. 2A) (Fig. 2A and paragraph 39), wherein, in a light-emitting area (a pixel region 101) (Fig. 2A and paragraph 55), the light-emitting panel comprises: a plurality of pixel units (a grouping of four sub-pixel regions 1010 function as pixel unit) arranged in an array (the pixel units are arranged in an array as shown in annotated Fig. 3A below), each of the pixel units comprises at least three sub-pixels (the pixel units comprise a group of four sub-pixel regions 1010 as shown in annotated Fig. 3A below), a light-emitting unit (a light-emitting device 1011) comprises a first electrode (an anode 1012) (Fig. 2A and paragraph 127), a pixel definition layer (a pixel defining structure 18) (Fig. 2A and paragraph 126), a light-emitting layer (a light-emitting function layer 1014) and a second electrode (cathode 1013) (Fig. 2A and paragraph 68), wherein a third isolation pattern (a protection pattern 1035) and a planarization layer (a planarization layer 160 ) are provided in a same layer and with a same material (the planarization layer 160 may be disposed in the same layer as the protection pattern 1035 and formed of the same material) (Fig. 2A and paragraph 116).
It would have been obvious to one skilled in the art to combine the teachings of Deng with the teachings of Ding to have the light-emitting area with a light-emitting panel that comprises a plurality of pixel units arranged in an array, each of the pixel units comprises at least three sub-pixels, the light-emitting unit comprises a first electrode, a pixel definition layer, a light-emitting layer and a second electrode since this layout is well known within the art to allow for a display device with a multi-colored display. Further, It would have been obvious to combine the teachings of Ding with the teachings of Deng to have the first isolation pattern, the second isolation pattern and the sixth isolation pattern are provided in a same layer and with a same material as the source electrode and the drain electrode since this layout is known to simplify the manufacturing process due to having fewer deposition and etching steps. Also, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
PNG
media_image1.png
682
893
media_image1.png
Greyscale
In regard to claim 2, Deng teaches wherein the barrier structure further comprises: a fifth isolation pattern (a second layer 112 consisting of one layer above the first layer 111) disposed on one side of the fourth isolation pattern away from the substrate (the second layer 112 consisting of one layer is above the first layer 111 as shown in Fig. 3), wherein an orthographic projection of the fifth isolation pattern on the substrate is located within the orthographic projection of the fourth isolation patter on the substrate (as shown in Fig. 3 the second layer 112 consisting of one layer above the first layer 111 is within the orthographic projection of the first layer 111 under it), or the orthographic projection of the fourth isolation pattern on the substrate is located within an orthographic projection of the fifth isolation pattern on the substrate.
In regard to claim 3, Deng teaches wherein the barrier structure further comprises:
a sixth isolation pattern disposed between the substrate and the first isolation pattern (the layer shown under the first layer 111 at the bottom of the isolation wall 103 in Fig. 3), wherein the orthographic projection of the first isolation pattern on the substrate is located within an orthographic projection of the sixth isolation patter on the substrate (the orthographic projection of the first layer 111 at the bottom of the isolation wall 103 is within the orthographic projection of the layer underneath it as shown in Fig. 3).
In regard to claim 5, Deng doesn’t explicitly teach wherein the first isolation pattern, the second isolation pattern and the sixth isolation pattern are provided in a same layer and with a same material as the source electrode and the drain electrode.
Ding teaches teach wherein the first isolation pattern (a middle layer of a separation pillar transition structure 104) (Fig. 11B and paragraph 154), a second isolation pattern and a sixth isolation pattern (the bottom and top layers of the separation pillar transition structure 104) are provided in a same layer and with a same material as the source electrode and the drain electrode (as shown in Fig. 11A and 12B the separation pillar transition structure 104 is formed of the same material and located in the same layer as the a source 142 and a drain 143) (Fig. 11A, Fig. 11B and paragraphs 158-159).
It would be obvious to combine the teachings of Ding with the teachings of Deng to have the first isolation pattern, the second isolation pattern and the sixth isolation pattern are provided in a same layer and with a same material as the source electrode and the drain electrode since this layout is known to simplify the manufacturing process due to having fewer deposition and etching steps. Further it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
In regard to claim 17, Deng teaches light-emitting apparatus (a mobile phone) comprising the light-emitting panel according to claim 1 (paragraph 48).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Deng in view of Ding as applied to claim 1 above, and further in view of Ban et al. (CN 109920818 A; hereinafter “Ban”), wherein US 2022/0376207 A1 is used as a translation.
In regard to claim 7, Deng in view of Ding don’t explicitly teach wherein the fourth isolation pattern and the first electrode are provided in a same layer and with a same material.
Ban teaches a display panel (paragraph 25), wherein a fourth isolation pattern (a first electrode layer 18) and a first electrode (a third electrode layer 28) are provided in a same layer and with a same material (a first electrode layer 18 covering the surface of the barrier body 114 and a third electrode layer 28 on the first flattening layer 17 are formed from the same material in the same step) (Fig. 1B, Fig. 4G and paragraphs 92).
It would have been obvious to one skilled in the art to combine the teachings of Deng in view of Deng with the teachings of Ban to have the fourth isolation pattern and the first electrode are provided in a same layer and with a same material since this layout is known to simplify the manufacturing process due to having fewer deposition and etching steps. Further it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Deng in view of Ding as applied to claim 1 above, and further in view of Qin et al. (WO2021036411A1; hereinafter “Qin”), wherein US 2021/0408511 A1 is used as a translation.
In regard to claim 8, Deng in view of Ding doesn’t explicitly teach wherein the fifth isolation pattern and the pixel definition layer are provided in a same layer and with a same material.
Qin teaches a display panel (a display panel 100) (Fig. 1 and paragraph 29), wherein a fifth isolation pattern (a tensile stress layer 403 in a second isolation structure 40) and a pixel definition layer (a pixel definition layer 16) are provided in a same layer and with a same material (the tensile stress layer 403 and a pixel definition layer 16 are formed in a same procedure from the same material) (Fig. 7 and paragraphs 58 and 63).
It would be obvious to one skilled in the art to combine the teachings of Deng in view of Ding with the teachings of Qin to have the fifth isolation pattern and the pixel definition layer are provided in a same layer and with a same material since this layout is known to simplify the manufacturing process due to having fewer deposition and etching steps. Further it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893