Prosecution Insights
Last updated: April 19, 2026
Application No. 18/276,215

MOUNTING STRUCTURE FOR CHIP COMPONENT

Final Rejection §102
Filed
Aug 07, 2023
Examiner
YASMEEN, NISHATH
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Koa Corporation
OA Round
2 (Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
2y 8m
To Grant
86%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
355 granted / 464 resolved
+8.5% vs TC avg
Moderate +10% lift
Without
With
+9.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
21 currently pending
Career history
485
Total Applications
across all art units

Statute-Specific Performance

§103
59.1%
+19.1% vs TC avg
§102
19.2%
-20.8% vs TC avg
§112
18.3%
-21.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 464 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statements (IDS) submitted on 8/7/2023, 2/27/2025 are being considered by the examiner. Status of Claims This office action is in response to “Claims filed on 12/22/2025”. Applicant's amendments of claims 1,5; cancellation of claims 4 and 3 and submission of new claim 6-7 with the same reply have been entered by the Examiner. Upon entry of the amendments, claims 1, 2, 5-7 are pending wherein claims 1 and 6 are independent. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Note applicable to all claims being rejected in this Office action: Examiner notes that the limitations "overlap", "layer", "portion" “above” are being interpreted broadly in accordance with MPEP. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. The claim presently discloses a structural limitation (i.e. overlap, layer, portion, contact) that is taught by prior art of record, therefore, the limitation is considered met by the prior art of record. Additionally, Merriam Webster dictionary defines the above limitations as “to occupy the same area in part”, “one thickness lying over or under another”, “an often limited part of a whole/ a part of a whole” “in or to a higher place than” respectively. Further note the limitation “contact” is being interpreted to include "direct contact" (no intermediate materials, elements or space disposed there between) and "indirect contact" (intermediate materials, elements or space disposed there between). Claim(s) 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Onodera et al US 2019/0237261 A1 hereinafter Onodera). Regarding Claim 1, Onodera discloses in Fig 10: A chip component mounting structure, comprising a chip component (C1) being provided with: a pair of back surface electrodes (E2) formed at both ends, respectively, in a longitudinal direction of a back surface of a rectangular parallelepiped insulating substrate (3); and end surface electrodes (E1) formed at the both ends, respectively, in the longitudinal direction of the insulating substrate and connected to the back surface electrodes, respectively, the chip component being mounted on a pair of lands (PE1, PE2) provided on a circuit board with the pair of back surface electrodes facing downward (See Fig 10), and the end face electrodes and the back surface electrodes being connected to the corresponding lands via solder (SF), wherein a distance between the pair of facing back surface electrodes is set to be shorter than a separation distance between the pair of lands, each of the back surface electrodes (E2) is provided with a thick portion of which a top portion faces toward each of the corresponding lands (PE1, PE2: See Fig 10). and portions of the back surface electrodes are disposed with protruding inwardly from the corresponding lands, respectively (See Fig 10 where electrodes E2 extend inward from PE1 and PE2) and the top portion of the thick portion is located directly above an inner end of each of the corresponding lands (PE1/PE2) [0081-0083]. See mark-up below showing a magnified version of Fig 10 of Onodera illustrating the top portion of the thick portion and note above for the definition of “portion” being interpreted per MPEP 2111 and 2111.01. Based on the definition, the top portion of the thick portion is being arbitrarily chosen to satisfy the claimed limitation. Note that the claim does not specify further structural details to narrow down the positional relationship between the landing pads and the top portion. PNG media_image1.png 676 784 media_image1.png Greyscale Regarding Claim 2, Onodera discloses in Fig 10: The chip component mounting structure according to claim 1, wherein each of the back surface electrodes (E2) is made of a resin material containing conductive particles formed in a thick film on the back surface of the insulating substrate (3) [0053-0054]. Allowable Subject Matter Claims 6-7 are allowed. The following is an examiner’s statement of reasons for allowance: With respect to claim 6, the primary reason for allowance is that the claim has been amended to include previously indicated allowable subject matter from claim 5. The prior art of record either singularly or in combination fails to teach or suggest the limitation “wherein each of the back surface electrodes includes a first electrode portion having a rectangular shape in plan view and located inwardly and away from an end face of the insulating substrate, and a plurality of second electrode portions separated and arranged on portions, respectively, in a short direction of the insulating substrate with a cutout portion, which is positioned between the end face of the insulating substrate and the first electrode portion, being interposed therebetween, and the thick portion is formed in the first electrode portion”. as recited in claim 6 in combination with the remaining features. Dependent claim 7 is allowed due to it’s dependency. The most relevant prior art references, (US 2019/0237261 A1 Al to Onodera et al. in Fig 10 substantially teaches the limitations of the claim 6, with the exception of the limitations described in the preceding paragraph. Onodera does not disclose the cutouts in the back electrode layer as claimed. Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 5, the primary reason for indication of allowable subject matter is that the prior art of record either singularly or in combination fails to teach or suggest the limitation “wherein each of the back surface electrodes includes a first electrode portion having a rectangular shape in plan view and located inwardly and away from an end face of the insulating substrate; and a plurality of second electrode portions extending from an end face in a short direction of the first electrode portion to the end face of the insulating substrate respectively, a cutout portion, from which the back surface of the insulating substrate is exposed, is formed between the plurality of second electrode portions, and the thick portion is formed in the first electrode portion.”. as recited in claim 5 in combination with the remaining features. The most relevant prior art references, (US 2019/0237261 A1 Al to Onodera et al. in Fig 10 substantially teaches the limitations of the claim 5, with the exception of the limitations described in the preceding paragraph. Onodera does not disclose the cutouts in the back electrode layer as claimed. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NISHATH YASMEEN whose telephone number is (571)270-7564. The examiner can normally be reached Mon-Fri 9AM-6PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NISHATH YASMEEN/Primary Examiner, Art Unit 2811
Read full office action

Prosecution Timeline

Aug 07, 2023
Application Filed
Sep 26, 2025
Non-Final Rejection — §102
Dec 22, 2025
Response Filed
Jan 21, 2026
Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
86%
With Interview (+9.8%)
2y 8m
Median Time to Grant
Moderate
PTA Risk
Based on 464 resolved cases by this examiner. Grant probability derived from career allow rate.

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