Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement filed 8/8/2023 has been considered by the examiner. Drawings The drawings filed 8/8/2023 are approved by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim s 1-3 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tadmor et al (United States Patent Application Publication No. 2021/0037149) . With respect to claim 1, Tadmor et al disclose: An electronic device [ taught by figure 1, figure 3 and figure 5 ] comprising circuitry [ taught by figure 5 ] , the circuitry comprising a mix driver for providing a modulation signal to pixels of a time of flight pixel chip [ taught by the modulation control signals (SG1 and SG2) being applied to transistors (46 and 56) ] , and at least one Save and Share current circuitry connected to the mix driver [ taught by floating diffusion region (60) ] , wherein the Save and Share current circuitry is configured to save charge provided by a power supply and to transfer the saved charge to the pixels of the time of flight pixel chip [ paragraph [0037] states , “… Pixel circuitry 162 may include floating diffusion region 60 having an associated charge storage capacity (e.g., having capacitance C subFD relative to voltage terminal 50 ). As an example, floating diffusion region 60 may be implemented as a doped semiconductor region (e.g., a region in a silicon substrate that is doped by ion plantation, impurity diffusion, or other doping processes). Storage gates 46 and 56 may temporarily store (portions of) image charge generated at photodiode 40 prior to transferring the stored portions of image charge to floating diffusion region 60 for readout …” ] . Claim 15 is anticipated by the subject matter of Tadmor et al, as applied to claim1. With respect to claim 2, Tadmor et al discloses: wherein the at least one Save and Share current circuitry is configured to save charge provided by a power supply in a first phase of a charging phase [ met by the operation of the reset transistor (62); paragraph [0038] states , “… A reset transistor 62 may couple floating diffusion region 60 to a voltage terminal 52 such as a supply voltage source. As an example, when control signal RST is asserted, floating diffusion region 60 may be reset to a reset voltage level (e.g., the supply voltage level) …” ] , and to share the saved charge to the pixel chip in a second phase of the charging phase [ met by the operation of the transfer transistors (48 and 5 8 ); paragraph [ 0038] states, “… During readout operations, each transfer transistor (when activated by control signals TX 1 or TX 2 ) may transfer a charge portion stored at the corresponding storage gate to floating diffusion region 60 for readout …” ] . Claim 3 is met by the subject matter of Tadmor et al, as applied to claim 2, because paragraph [0036] teaches that the control signals applied to storage gates (48 and 58) are inverted. Allowable Subject Matter Claims 4-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Any inquiry concerning this communication should be directed to MARK HELLNER at telephone number (571)272-6981 . Examiner interviews are available via a variety of formats. See MPEP § 713.01. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. /MARK HELLNER/ Primary Examiner, Art Unit 3645