Office Action Predictor
Last updated: April 15, 2026
Application No. 18/276,647

COLUMN SIGNAL PROCESSING UNIT AND SOLID-STATE IMAGING DEVICE

Final Rejection §102
Filed
Aug 10, 2023
Examiner
GILES, NICHOLAS G
Art Unit
2639
Tech Center
2600 — Communications
Assignee
Sony Semiconductor Solutions Corporation
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
2y 5m
To Grant
92%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
683 granted / 834 resolved
+19.9% vs TC avg
Moderate +10% lift
Without
With
+9.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
25 currently pending
Career history
859
Total Applications
across all art units

Statute-Specific Performance

§101
4.0%
-36.0% vs TC avg
§103
39.2%
-0.8% vs TC avg
§102
24.4%
-15.6% vs TC avg
§112
23.8%
-16.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 834 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments The rejection of claims 1-3 and 7 have been withdrawn in view of the amendments to claim 1. No arguments were received for unamended independent claim 12. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 12-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koifman et al (U.S. Pub. No. 20160225807). Regarding claim 12, Koifman discloses: A solid-state imaging device, comprising: a plurality of pixel circuits (column of pixels 20, par. 80), wherein each pixel circuit is configured to generate a pixel output signal with an amplitude related to an intensity of detected light (photodiode 21 (photodiodes create photocurrent based on the amount of received photons), par. 50), and wherein the pixel circuits are connected to a data signal line (source of select transistor 27 of pixel 20 is coupled via output conductor 29 to readout circuit 12 and charge accelerator 40, par. 51, and Figs. 5 and 6); and a column signal processing unit, wherein the column signal processing unit comprises: a current control circuit electrically connected between the data signal line and a supply reference potential (capacitor 42 (and first switch 44) between column line 29 and fixed bias 43 (that may also be a ground connection), par. 53, 54, 82, and Fig. 5), and a feedback circuit configured to reduce a capacitive load of the data signal line (charge accelerator 40 performing a feedback operation and acting as a negative capacitance circuit, par. 56, 64, and Fig. 5), wherein a feedback path of the feedback circuit comprises a feedback capacitor and a delay element electrically connected in series (buffer capacitor 48 and amplifier 46, where in Fig. 5 it can be seen that the capacitor 48 and amplifier 46 are wired in series, par. 63, 78, and Fig. 5), and wherein the delay element is configured to increase a time delay in the feedback path (amplifier 46 that outputs an output signal that is responsive to the change of the output conductor voltage, par. 63). Regarding claim 13, Koifman further discloses: a sensor controller (controller 50, par. 65), wherein the feedback circuit comprises a first switch (switch 47, par. 54 and Fig. 5), and wherein the delay element and the first switch are electrically connected in parallel (switch 47 and amplifier 46 are in parallel, Fig. 5), and wherein the sensor controller is configured to generate and output a first control signal for the first switch (controller 50 may be configured to control the operation of device 10 including switches, par. 65). Regarding claim 14, Koifman further discloses: sensor controller is configured to generate and output the first control signal in response to a synchronization signal (during the sampling operation, switch 47 is open(disconnected) using control signals, par. 57, 65). Regarding claim 15, Koifman further discloses: column signal processing unit is configured to use a synchronization signal as the first control signal (during the sampling operation, the switch 47 is open (disconnected) using control signals, par. 57, 65). Allowable Subject Matter Claims 1-11 and 16 are allowed. Regarding claim 1, no prior art could be located that teaches or fairly suggests a feedback circuit configured to reduce a capacitive load of the data signal line, wherein a feedback path of the feedback circuit comprises a series connection of (i) a feedback capacitor including two conductive materials separated by a non-conductive material and (ii) a delay element, and wherein the delay element is configured to increase a time delay in the feedback path, in combination with the rest of the limitations of the claim. Claims 2-11 and 16 depend on claim 1 and therefore are allowed. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. /NICHOLAS G GILES/ Primary Examiner, Art Unit 2639
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Prosecution Timeline

Aug 10, 2023
Application Filed
Aug 16, 2025
Non-Final Rejection — §102
Oct 06, 2025
Interview Requested
Oct 16, 2025
Applicant Interview (Telephonic)
Oct 16, 2025
Examiner Interview Summary
Nov 20, 2025
Response Filed
Jan 23, 2026
Final Rejection — §102
Mar 27, 2026
Response after Non-Final Action

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
92%
With Interview (+9.7%)
2y 5m
Median Time to Grant
Moderate
PTA Risk
Based on 834 resolved cases by this examiner. Grant probability derived from career allow rate.

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