DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 and 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shuai (CN110224680A; please refer to US2022/0321078A1 as an equivalent translation).
Claim 1. A method for preparing a piezoelectric transducer, the method comprising:
providing a carrier wafer (see Fig. 9(5) and [0166]) and preparing a bottom acoustic reflection layer (see [0167]) on the carrier wafer;
providing a piezoelectric wafer (Fig. 9(1) and [0160]) and preparing a top acoustic reflection layer (see [0163]) on the piezoelectric wafer, wherein both the top acoustic reflection layer and the bottom acoustic reflection layer are configured to confine acoustic vibrations1;
combining (see Fig. 9(7) and [0168]-[0169]) a side of the bottom acoustic reflection layer away from the carrier wafer and a side of the top acoustic reflection layer away from the piezoelectric wafer; and
thinning the piezoelectric wafer (see [0169]), thereby achieving the piezoelectric transducer.
Claim 2. The method according to claim 1, wherein the step of providing the piezoelectric wafer and preparing the top acoustic reflection layer on the piezoelectric wafer comprises substeps of:
providing the piezoelectric wafer, and preparing a bottom electrode layer (see Fig. 9(1) and [0160]) on the piezoelectric wafer; and
providing the top acoustic reflection layer (Fig. 9(3) and [0163]) covering the bottom electrode layer on the piezoelectric wafer.
Claim 3. The method according to claim 1, wherein the bottom acoustic reflection layer comprises one or more bottom high acoustic impedance layers (see [0167]) and one or more bottom low acoustic impedance layers [0167], the sum of the number of the one or more bottom high acoustic impedance layers and the number of the one or more bottom low acoustic impedance layers is an odd number (see [0167]), the step of providing the carrier wafer and preparing the bottom acoustic reflection layer on the carrier wafer comprises substeps of:
providing the carrier wafer, and
alternately preparing the one or more bottom high acoustic impedance layers and the one or more bottom low acoustic impedance layers on a side of the carrier wafer (see “[g]rowing a high acoustic impedance reflecting layer above the said substrate, then growing a low acoustic impedance reflecting layer on the previous high acoustic impedance reflecting layer, repeating the operation for 1-2 cycles, and at last growing a high acoustic impedance reflecting layer on the low acoustic impedance reflecting layer” in [0167]).
Claim 4. The method according to claim 3, wherein the top acoustic reflection layer comprises a top low acoustic impedance layer (see [0163]), and the step of providing the piezoelectric wafer and preparing the top acoustic reflection layer on the piezoelectric wafer comprises substeps of:
providing the piezoelectric wafer, and
preparing the top low acoustic impedance layer on the piezoelectric wafer (see “growing a low acoustic impedance reflecting layer on one side of the said piezoelectric material” in [0163]).
Claim 5. The method according to claim 3, wherein the top acoustic reflection layer comprises one or more top low acoustic impedance layers and one or more top high acoustic impedance layers (see [0163] and footnote 2), the sum of the number of the top high acoustic impedance layers and the number of the top low acoustic impedance layer is an odd number2, and the step of providing the piezoelectric wafer and preparing the top acoustic reflection layer on the piezoelectric wafer comprises substeps of:
providing a piezoelectric wafer, and
alternately preparing the one or more top low acoustic impedance layers and the one or more top high acoustic impedance layers on the piezoelectric wafer (see [0163]).
Claim 6. The method according to claim 5, wherein in the bottom acoustic reflection layer, the farthest from the carrier wafer is one bottom low acoustic impedance layer (see footnote 2), and in the top acoustic reflection layer, the farthest from the piezoelectric wafer is one top low acoustic impedance layer (see footnote 2); or
in the bottom acoustic reflection layer, the farthest from the carrier wafer is one bottom high acoustic impedance layer, and
in the top acoustic reflection layer, the farthest from the piezoelectric wafer is one top high acoustic impedance layer.
Claim 8. The method according to claim 1, wherein the step of combining the side of the bottom acoustic reflection layer away from the carrier wafer and the side of the top acoustic reflection layer away from the piezoelectric wafer comprises substeps of:
providing a bonding interface layer (see Fig. 9(4), 9(6), [0165] and [0168]), and
combining the side of the bottom acoustic reflection layer away from the carrier wafer and the side of the top acoustic reflection layer away from the piezoelectric wafer through the bonding interface layer (see [0168]).
Claim 9. The method according to claim 1, wherein the step of providing the piezoelectric wafer and preparing the top acoustic reflection layer on the piezoelectric wafer comprises substeps of:
providing the piezoelectric wafer, implanting ions into the piezoelectric wafer (see [0174]), and preparing the top acoustic reflection layer on the ion implanted piezoelectric wafer (see [0177]).
Claim 10. A piezoelectric transducer, prepared according to the method of claim 1. See rejection of claim 1.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shuai in view of Nakatsuka (US2009/0102319A1).
Shuai discloses the claimed invention, except for the claimed planarizing.
Nakatsuka shows it is known to planarize acoustic layers, after adding to an acoustic stack when forming an acoustic miror. See “the planarizing process is performed in order to eliminate steps on a surface of the laminated high acoustic impedance layer 51 (FIG. 12A, process F). Next, a low acoustic impedance layer 52 is laminated on the planarized high acoustic impedance layer 51 (FIG. 12B, process G). By repeatedly performing the processes F and G, an acoustic mirror layer 50 is formed (FIG. 12B, process H).” in [0114] and refer to Figs. 12A and 12B.
One of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to planarize the various high and low acoustic impedance layers, including the final layer on the piezoelectric layer and on the carrier wafer, to ensure a smooth surface of each of the planarized layers, with predictable results.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US20030199105 discloses a method for making piezoelectric resonator and surface acoustic wave device using hydrogen implant layer splitting (relevant to claim 9).
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/LIVIUS R. CAZAN/Primary Examiner, Art Unit 3729
1 This is an inherent function of acoustic reflecting layers, as they reflect acoustic vibrations.
2 As per [0163], the top acoustic reflection layer includes an alternating sequence of low- and high acoustic impedance layers, starting with a low acoustic impedance layer. However, the corresponding bonding layer is made from SiO2 (see [0165]), which is a low acoustic impedance material (see [0163]). Therefore, the sum of the number of the top high acoustic impedance layers and the number of the top low acoustic impedance layer is an odd number. Similarly, the bonding layer in the bottom acoustic reflection layer, the farthest from the carrier wafer is SiO2 (see [0168]), i.e. a low acoustic impedance layer.
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