Prosecution Insights
Last updated: August 18, 2026
Application No. 18/278,253

PRINTED WIRING BOARD

Final Rejection §103
Filed
Aug 22, 2023
Priority
Jul 09, 2021 — JP 2021-114335 +1 more
Examiner
SAWYER, STEVEN T
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sumitomo Electric Industries Ltd.
OA Round
4 (Final)
72%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
755 granted / 1042 resolved
+4.5% vs TC avg
Strong +30% interview lift
Without
With
+30.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
39 currently pending
Career history
1074
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
64.2%
+24.2% vs TC avg
§102
24.0%
-16.0% vs TC avg
§112
9.8%
-30.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1042 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Magera et al. (US PG. Pub. 2008/0121420) in view of Koyanagi (US Patent 6803528). Regarding claim 1 – Magera teaches a printed wiring board (figs. 1-3) comprising: a base (110 [paragraph 0025] Magera states, “insulating dielectric core 110”) having a first surface (top surface) and a second surface (bottom surface) positioned opposite to the first surface (see fig. 3), wherein a through hole (140 [paragraph 0023] Magera states, “aperture 140”) reaching the second surface (bottom surface) from the first surface (top surface) is formed in the base (110), wherein a first opening (upper opening) being an open end of the through hole (140) is formed in the first surface (top surface) of the base (110), wherein a second opening (lower opening) being an open end of the through hole (140) is formed in the second surface (bottom surface) of the base (110), the printed wiring board further comprising a conductor layer (350/340 [paragraph 0023] Magera states, “copper 340, 350 is also plated on the walls of the mechanically drilled aperture 140”) disposed at least inside the through hole (140), the conductor layer (350/340) extending from the first surface (top surface) to the second surface (bottom surface), wherein the base (110) includes a first protrusion (see protrusion that narrows the through hole 140 at the first surface) protruding from an edge portion of the first opening (see annotated figure 3 below), wherein the first opening (upper opening adjacent to the protrusion) has a first opening width in a first cross section passing through the first protrusion and a center of the first opening and taken along a thickness direction of the base (see annotated figure 3 below), wherein the second opening (opening at the second surface) has a second opening width in the first cross section, wherein the first opening width is smaller than the second opening width (claimed structure shown in annotated figure 3 below), wherein the first protrusion includes a first conductor layer (130 [paragraph 0025] Magera states, “metal foil 120, 130 such as copper”), and wherein the first conductor layer (130) extends to a region adjacent to, but not beyond, the first opening at the first surface (top surface) of the base (110; claimed structure shown in figure 3 and annotated figure 3 below). Magera fails to teach a first conductor layer including a material differing from a material of the conductor layer, wherein the material of the first conductive layer includes chromium. Koyanagi teaches a printed wiring board (figs. 3 & 5d [title] Koyanagi states, “multi-layer Double-sided Wiring Board”) having a first conductor layer (fig. 3, 14 [column 3 lines 19-21] Koyanagi states, “interface layer 14 is simply interposed between the insulating layer 10 and the lower conductive layer 12”) and a conductor layer (12 [column 3-4, lines 66-1] Koyanagi states, “The upper and lower conductive layers are 5 .mu.m to 50 .mu.m in thickness, and the material is preferably copper”) wherein the first conductor layer (14 [column 3 lines 63-66] Koyanagi states, “the interface layer is 10 nm to 500 nm, and preferably 150 nm, and the material is a single-element or a composite material containing Co, Ni, Zi, or Cr, and a material containing Cr is particularly preferable”) including a material differing from a material of the conductor layer (layer 12 is made of copper, layer 14 includes Cr), wherein the material of the first conductive layer (14) includes chromium (chromium Cr as quoted above). It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the printed wiring board having a first conductor layer on the first protrusion but not extending beyond the first opening and a conductor layer extending from the first to second surface of the base within the through hole as taught by Magera with the first conductor layer includes chromium and is a different material than that of the conductor layer as taught by Koyanagi because Koyanagi states, “it is practiced to deposit an interface layer containing a dissimilar metal such as Cr, Ni, or the like by sputtering on the film prior to the copper sputtering, thereby increasing the peel strength between the base and lead finished product” [column 1 lines 47-51]. PNG media_image1.png 809 966 media_image1.png Greyscale Regarding claim 5 - Magera in view of Koyanagi teach the printed wiring board according to claim 1, wherein the material of the first conductive layer (Koyanagi; fig. 14) further includes nickel ([column 3 lines 63-66] Koyanagi states, “the interface layer is 10 nm to 500 nm, and preferably 150 nm, and the material is a single-element or a composite material containing Co, Ni, Zi, or Cr, and a material containing Cr is particularly preferable”). Allowable Subject Matter Claims 10, 13 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to claim(s) 1 and 5 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN T SAWYER/ Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Show 1 earlier event
Jul 28, 2025
Non-Final Rejection mailed — §103
Oct 27, 2025
Response Filed
Nov 18, 2025
Final Rejection mailed — §103
Jan 14, 2026
Request for Continued Examination
Jan 29, 2026
Response after Non-Final Action
Feb 06, 2026
Non-Final Rejection mailed — §103
May 05, 2026
Response Filed
May 27, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12701662
WIRING SUBSTRATE, METHOD OF TRIMMING SAME, AND MULTI-LAYERED WIRING BOARD
3y 1m to grant Granted Aug 04, 2026
Patent 12695180
CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF
3y 2m to grant Granted Jul 28, 2026
Patent 12693710
ELECTRONIC DEVICE
2y 10m to grant Granted Jul 28, 2026
Patent 12689196
ELECTRICAL DEVICE ALIGNMENTS
3y 11m to grant Granted Jul 21, 2026
Patent 12690141
WIRING BOARD STRUCTURE
2y 4m to grant Granted Jul 21, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
72%
Grant Probability
99%
With Interview (+30.5%)
2y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 1042 resolved cases by this examiner. Grant probability derived from career allowance rate.

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