Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-10 are pending. This action is in response to Applicant’s Response filed 3/09/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 6, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Rash (US 9,703,562) in view of Bugnion (US 20130151824).
As per claim 1, Rash discloses a method for live migration of a virtual machine, comprising:
trapping an exception when an instruction of an instruction set that is not possessed by a destination host but possessed by a source host is executed in a virtual machine on the destination host (Column 6, lines 13-34 “The post-decode instruction processor logic includes an embodiment of emulation mode aware instruction processor logic 120. As shown, the emulation mode aware instruction processor logic may be coupled with, or otherwise aware of, the emulation mode 118. In some embodiments, the emulation mode aware instruction processor logic may be operable to process at least some of the decoded versions of the instructions 114 differently in at least some ways when the processor is in the emulation mode than when the processor is not in the emulation mode. There are various different ways in which the processing may be different. In some embodiments, fault or error handling may be performed differently when in the emulation mode as compared to when not in the emulation mode. In other embodiments, access to certain types of resources and/or information, such as, for example, secure, privileged, or otherwise access controlled resources and/or information, may be handled differently when in the emulation mode than when not in the emulation mode. For example, access to the resources and/or information may be allowed when in the emulation mode but not allowed when not in the emulation mode.”);
intercepting the exception and analyzing an interrupt context of the exception by a kernel-based virtual machine module in the destination host (Column 11, lines 19-41 “In some embodiments, the emulation mode aware exceptional condition handler logic 420 may also provide an indication of the address (e.g., the instruction pointer) of the instruction being emulated (i.e., the one that caused the second instance 403-2 to be sent to the decode logic 405). For example, in some embodiments, the address 446 of the instruction being emulated may be stored on the top of a stack 447. Storing the address of a given instruction that is being emulated on the stack, instead of one of the instructions that are being used to emulate that given instruction, may cause the return from the exception handler to return to the emulated instruction, instead of to one of the instructions that are being used to emulate that emulated instruction. If instead, the return from the exception handler were to one of the instructions that are being used to emulate that instruction, this may potentially cause a problem. For example, software (e.g., an application, operating system, etc.) may not know of the instructions that are being used to emulate that given instruction and may not recognize the associated address. The operating system may perceive that control flow is being transferred to an unknown, illegal, risky, or not allowed location, and may potentially attempt to prevent the transfer.”);
acquiring and decoding data of the instruction according to instruction address information in the interrupt context (Column 11, lines 42-67 “In some embodiments, the set of instructions 414 may monitor the error status 444 and/or the error code 445. For example, in some embodiments, the instructions 414 may read the error status 444 and the error code 445 from the emulation communication registers 443 to learn of the exceptional condition and about the exceptional condition. When the error status 444 indicates an exceptional condition, in some embodiments, the set of instructions 414 may take the exceptional condition 449. For example, one or more of the instructions 414 may be executed to check the error status and transfer control to the exceptional condition handler if an error is indicated. In some embodiments, this may include the set of instructions 414 transferring control to the exceptional condition handler 441. In some embodiments, information about the exceptional condition (e.g., the error code 445) may be provided to the exceptional condition handler 441. In some embodiments, the emulated instruction address 446 may also be provided to the exceptional condition handler 441 and/or may be at least preserved on the top of the stack. The emulated instruction address 446 may be used by the exceptional condition handler 441 upon return from handling the exceptional condition. Advantageously, by storing the address of the instruction being emulated on the stack, the operating system or other error handler routine may think it is the instruction that is emulated that caused the error.”); and
emulating an execution process of the instruction by using an instruction set possessed by the destination host (Column 12, lines 1-24 “In some embodiments, the emulation logic may include logic to test and report whether memory access in the instruction will work correctly, or the type of exceptional condition that may result. For example, a special instruction may be included to test a memory address with emulated access rights to see if the memory address is valid (e.g., if the page is present) and whether the program has sufficient access rights to read and/or modify that memory location. If any tests fail, the emulation logic may pass control to the proper interrupt handler with a return address as if the instruction being emulated had directly passed control to the exception handler. As another example, a state machine may perform a conditional memory transaction which indicates whether the memory operation would be valid. This may be used to determine when a memory operation may be performed assuming no exception will result. This may also be used to determine how many bytes of an instruction stream or a string of instruction information may be safely read without exceptions. For example, this may be used to test and determine whether or not an instruction length may be read or if part of the instruction length would cause a page fault. The emulation logic may include logic to deal with instructions that span multiple pages and/or when a page is not in memory.”).
Rash does not expressly disclose but Bungion discloses comprising:
emulating a process of decoding the instruction in a user space by using a decoding tool and generating emulation instruction(s) (Paragraph 161 “Although complex, this general decoding of the instruction stream and reconstruction of the control flow is less complex than having to rely on the interpretation of the instruction sequence until the first TC-synchronization boundary is detected. This decoding approach is particularly advantageous compared with an interpreter on architectures such as the x86, where, due to the complexity of the instruction set, a complete interpreter is a very large piece of software. Nonetheless, as is mentioned above, software interpretation or hardware-based single-stepping are valid alternatives to the method preferred in this invention, namely, the use of INT instructions.”); and
transplanting the emulation instructions in the user space to the kernel-based virtual machine module in the destination host (Paragraph 21 “In the preferred embodiment of the invention, processing of a sensed asynchronous exception is delayed by a) temporarily replacing with a trap generation instruction the initial target instructions in each of the translated target instruction sequences that correspond to target instruction sequences that possibly immediately follow the current target instruction sequence; b) resuming execution of the current target instruction sequence from the point at which the asynchronous exception was sensed; c) restoring each of the temporarily replaced instructions with their original content after completion of the processing of the sensed asynchronous exception; and d) upon reaching the trap generation instruction, forwarding and processing the sensed asynchronous exception. Alternative methods embodiments of the invention may use to process a sensed asynchronous exception include simulating or single-stepping execution of the remaining target instructions.”).
Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to modify the method of Rash to include the teachings of Bugnion because it allows for instruction translation while still maintaining separation between user and kernel space. In this way, the combination benefits from the increased code portability and security.
As per claim 3, Rash further discloses wherein the step of emulating the execution process of the instruction by using the instruction set of the destination host, further comprising:
establishing a test case library (Column 12, lines 1-24); and
after transplanting the emulation instructions in the user space to the kernel-based virtual machine module in the destination host, and performing regression test on the test case library (Column 12, lines 1-24).
As per claim 4, Rash further discloses wherein the source host is a higher-generation processor than the destination host (Column 15, lines 16-38 “In some embodiments, instruction emulation may be used to help provide different meanings for a given opcode of an instruction. In some embodiments, the given opcode of the instruction may be interpreted with different meanings. In some embodiments, multiple opcode definitions may be supported for the given opcode. For example, the given opcode may be interpreted with a meaning that a software program having the instruction intends. By way of example, in some embodiments, an older or legacy software program may indicate that instructions with the given opcode are to have an older, legacy, or deprecated meaning, and a newer software program may indicate that instructions with the given opcode are to have a newer meaning. In some embodiments, the older or deprecated meaning may be emulated, whereas the newer meaning may be decoded into control signals and executed on the processors pipeline directly. Advantageously, in some embodiments, this may help to allow earlier recapture and reuse of opcodes being deprecated while still providing backward compatibility that allows older programs to still run with a deprecated opcode while allowing the deprecated opcode to also be used for newer programs with a different meaning to help improve performance.”).
As per claim 6, it is an apparatus claim having similar limitations as cited in claim 1 and is thus rejected under the same rationale.
As per claim 8, it is an apparatus claim having similar limitations as cited in claim 3 and is thus rejected under the same rationale.
As per claim 9, it is an apparatus claim having similar limitations as cited in claim 4 and is thus rejected under the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 5, 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Rash in view of Bungion in further view of Opferman (US 2019/0042258).
As per claim 2, Rash further discloses further comprising:
creating a processor feature map in the destination host according to emulation results (Column 28, lines 12-22 “In some cases, an instruction converter may be used to convert an instruction from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction to one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on processor, off processor, or part on and part off processor.”);
creating a virtual machine on the source host based on the processor feature map (Column 28, lines 12-22).
Rash does not expressly disclose but Opferman discloses live-migrating the virtual machine on the source host to the destination host (Paragraphs 32-33 “the OS determines whether to migrate the faulting thread or emulate the faulting instruction. In 230, the OS invokes an emulation module to emulate the faulting instruction. Alternatively, in 240, the OS migrates the faulting thread to a core that supports the faulting instruction.”).
Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to modify the method of Rash to include the teachings of Opferman because it provides for the purpose of ensuring that instructions of different architectures can be executed by a single execution pipeline. In this way, the combination benefits from the instruction translation that occurs by ensuring a seamless operation.
As per claim 5, Rash does not expressly disclose but Opferman discloses wherein the instruction set possessed by the destination host is AVX2, and the instruction set possessed by the source host is AVX512 (Table 1 and Table 2 refer to AVX2 and AVX512.).
Therefore it would have been obvious to one of ordinary skill in the art at the time of filing to modify the method of Rash to include the teachings of Opferman because it provides for the purpose of ensuring that instructions of different architectures can be executed by a single execution pipeline. In this way, the combination benefits from the instruction translation that occurs by ensuring a seamless operation.
As per claim 7, it is an apparatus claim having similar limitations as cited in claim 2 and is thus rejected under the same rationale.
As per claim 10, it is an apparatus claim having similar limitations as cited in claim 5 and is thus rejected under the same rationale.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY A MUDRICK whose telephone number is (571)270-3374. The examiner can normally be reached 9am-5pm Central Time.
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/TIMOTHY A MUDRICK/Primary Examiner, Art Unit 2198 4/25/2026
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