DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10, 11-12, 14, 15 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Norman et al. (US PG. Pub. 2020/0099541) in view of Chen et al. (US PG. Pub. 2009/0045904).
Regarding claim 10 – Norman teaches an arrangement for determining a unique printed circuit board identifier (fig. 3), via which an electronic component (2 [paragraph 0050] Norman states, “two devices 1, 2 are to be bound together (e.g. smart phone and a SIM card)”) which is fitted to a printed circuit board ([paragraph 0064] Norman states, “In case the first device 1 and the second device 2 are mounted on the same printed circuit board (PCB) it is possible to keep the electrical properties of the two buses under control”) is uniquely linked to the printed circuit board (see paragraph 0064), the arrangement comprising: at least one physical unclonable functions unit (4 [paragraph 0050] Norman states, “second PUF part 4 (PUF 2)”) having ring oscillators ([paragraph 0040] Norman states, “Most PUF Integrated Circuits (ICs) developed up to now can be divided into two categories: delay-based (e.g., ring oscillator PUFs and arbiter PUFs)”) which, by reference to frequencies of the ring oscillators, determines the unique printed circuit board identifier ([paragraph 0039] Norman states, “PUFs have been proposed as a low-cost cryptographic primitive for device identification”), said PUF unit (4) being arranged in the electronic component (device 2); and delay elements ([paragraph 0040] Norman states, “the former (delay-based PUFs and specifically arbiter PUFs) are used for describing various embodiments”) which are fitted to the printed circuit board (the delay element will be fitted to device 1/device 2 that is fitted to the printed circuit board), an oscillator loop ([paragraph 0068] Norman states, “the PUF output response RES1 size is made equal to the input challenge R1 size and the verification is run in a loop a predetermined number of times, by applying the computed response as the challenge at the next loop iteration”) of each respective ring oscillator (discussed above) of the PUF unit (4) being formed from a delay element (claimed structural features discussed above).
Norman fails to teach delay elements are used which are fitted to the printed circuit board, wherein the delay elements are formed as printed conductors which are routed on the printed circuit board; wherein each delay element comprises first sections which are routed on a first conductive layer of the printed circuit board, and comprises second sections which are routed on a second conductive layer of the printed circuit board; wherein the first sections of a respective delay element which are routed on the first conductive layer of the printed circuit board and the second sections of a respective delay element which are routed on the second conductive layer of the printed circuit board are connected via electrical through-contacts; and wherein two delay elements are each arranged on the printed circuit board such that, at least one point, the respective first sections of the two respective delay elements overlap or intersect with the respective second sections of the two respective delay elements.
Chen teaches delay elements (figs. 7A-7B shows the equivalent structure of a “delay element”) formed as printed conductors (upper and lower conductors as shown in figure 7A) which are routed on the printed circuit board (410 [paragraph 0038] Chen states, “dielectric substrates 410”); wherein each delay element comprises first sections (upper conductors shown in figure 7A) which are routed on a first conductive layer (top conductive layer) of the printed circuit board, and comprises second sections (lower conductors shown in figure 7A) which are routed on a second conductive layer (bottom conductive layer) of the printed circuit board; wherein the first sections of a respective delay element which are routed on the first conductive layer of the printed circuit board and the second sections of a respective delay element which are routed on the second conductive layer of the printed circuit board are connected via electrical through-contacts (see via shown connecting the first and second sections); and wherein two delay elements are each arranged on the printed circuit board such that, at least one point, the respective first sections of the two respective delay elements overlap or intersect with the respective second sections of the two respective delay elements (claimed structure shown in figures 7A and 7B).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the arrangement for determining a unique printed circuit board identifier having delay elements as taught by Norman with the delay elements being a conductive first/top and second/bottom sections that are connected through vias on a circuit board and overlap at one point as taught by Chen because Chen states, “the embedded stereographic inductor can concentrate electromagnetic field distribution in the central region of the inter-helix spiral coil, thereby reducing electromagnetic radiation and energy loss and improving quality factor” [paragraph 0034]. This particular delay element structure will reduce energy loss.
Regarding claim 11 – Norman in view of Chen teach the arrangement as claimed in claim 10, wherein the electrical through contacts (Chen; figs. 7A-7B, see via shown connecting the first and second sections) which are respectively employed by two delay elements (the electrical through contacts are connected to elements 440 & 430 that are considered the two delay elements) are arranged adjacently on the printed circuit board (410; claimed structure shown in figure 7A).
Regarding claim 12 – Norman in view of Chen teach the arrangement as claimed in claim 10, wherein the arrangement is configured to determine and permanently save ([paragraph 0138] Norman states, “The second device 2 may be configured to perform the above steps e.g. by comprising processing circuitry 90 and memory 91, the memory 91 containing instructions executable by the processing circuitry 90”) the printed circuit board identifier in the electronic component (2) during a linking phase ([paragraph 0064] Norman states, “In case the first device 1 and the second device 2 are mounted on the same printed circuit board (PCB) it is possible to keep the electrical properties of the two buses under control. It is also possible, e.g., by multilayer PCBs to have a stable aging of the buses during the life-time of the product and have the buses protected from environmental influences”).
Regarding claim 14 – Norman in view of Chen teach the arrangement as claimed in claim 10, further comprising: a memory unit (Norman; [paragraph 0040] Norman states, “Most PUF Integrated Circuits (ICs) developed up to now can be divided into two categories: delay-based (e.g., ring oscillator PUFs and arbiter PUFs) and memory-based (e.g., SRAM (Static Random-Access Memory) PUFs)”) in which the printed circuit board identifier is permanently saved (the SRAM will “permanently save” the identifier).
Regarding claim 15 – Norman in view of Chen teach the arrangement as claimed in claim 14, wherein the memory unit (Norman; [paragraph 0040] Norman states, “Most PUF Integrated Circuits (ICs) developed up to now can be divided into two categories: delay-based (e.g., ring oscillator PUFs and arbiter PUFs) and memory-based (e.g., SRAM (Static Random-Access Memory) PUFs)”) is configured to be activatable to permanently save the printed circuit board identifier (this function will be performed by the SRAM).
It has been held that the recitation that an element is “capable of” performing a function is not a positive limitation but only requires the ability to so perform. It does not constitute a limitation in any patentable sense. In re Hutchinson, 69 USPQ 138.
Regarding claim 20 – Norman in view of Chen teach the assembly as claimed in claim 10, wherein the electronic component (Norman; fig. 3, 2) comprises an application-specific integrated circuit ([paragraph 0037] Norman states, “A PUF is a physical entity embodied in a physical device (e.g. an integrated circuit (IC) or chip”).
Claim(s) 10, 11, 14, 15 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lewis et al. (US PG. Pub. 2013/0276151) in view of Chen et al.
Regarding claim 10 – Lewis teaches an arrangement for determining a unique printed circuit board identifier (fig. 13 [paragraph 0078] Lewis states, “The present invention provides a mechanism whereby the measurement of arbitrary structures provides better identification and quantifies the difference (between two structures)”), via which an electronic component (fig. 13, 530 [paragraph 0119] Lewis states, “integrated circuits 530, 532, and 534”) which is fitted to a printed circuit board (520/522 [paragraph 0122] Lewis states, “printed circuit boards 520, 522”) is uniquely linked to the printed circuit board (520/522), the arrangement comprising: at least one physical unclonable functions unit (543 [paragraph 0119 & 0122] Lewis states, “FIG. 13 illustrates an AUF 500 that includes elements external to the integrated circuit that serve as the base for the PUF…The careful routing of conductor 543 provides the ability to detect changes in the chassis/packaging 510 as well as detecting the placement of printed circuit boards 520, 522”) having ring oscillators (523 [paragraph 0122] Lewis states, “ring oscillator 523”) which, by reference to frequencies of the ring oscillators, determines the unique printed circuit board identifier ([paragraph 0105] Lewis states, “Each time these four ring oscillators 105, 106, 107, 108 are implemented identically (that is, as a ring oscillator structure) in a different integrated circuit, the difference between the count output values (after compensation) will be unique”), said PUF unit (543) being arranged in the electronic component (530); and delay elements (532 [paragraph 0121] Lewis states, “The delay elements 550, 552, 554”) which are fitted to the printed circuit board (520/522), an oscillator loop (see oscillator loop shown in figure 7) of each respective ring oscillator (523) of the PUF unit (543) being formed from a delay element (figure 7 shows the claimed feature of the oscillator loop that will be present in figure 13; additionally figure 13 shows a loop structure including a delay element 550).
Lewis fails to teach wherein the delay elements are formed as printed conductors which are routed on the printed circuit board; wherein each delay element comprises first sections which are routed on a first conductive layer of the printed circuit board, and comprises second sections which are routed on a second conductive layer of the printed circuit board; wherein the first sections of a respective delay element which are routed on the first conductive layer of the printed circuit board and the second sections of a respective delay element which are routed on the second conductive layer of the printed circuit board are connected via electrical through-contacts; and wherein two delay elements are each arranged on the printed circuit board such that, at least one point, the respective first sections of the two respective delay elements overlap or intersect with the respective second sections of the two respective delay elements.
Chen teaches the delay elements (figs. 7A-7B shows the equivalent structure of a “delay element”) are formed as printed conductors (upper and lower conductors as shown in figure 7A) which are routed on the printed circuit board (410 [paragraph 0038] Chen states, “dielectric substrates 410”); wherein each delay element comprises first sections (upper conductors shown in figure 7A) which are routed on a first conductive layer (top conductive layer) of the printed circuit board, and comprises second sections (lower conductors shown in figure 7A) which are routed on a second conductive layer (bottom conductive layer) of the printed circuit board; wherein the first sections of a respective delay element which are routed on the first conductive layer of the printed circuit board and the second sections of a respective delay element which are routed on the second conductive layer of the printed circuit board are connected via electrical through-contacts (see via shown connecting the first and second sections); and wherein two delay elements are each arranged on the printed circuit board such that, at least one point, the respective first sections of the two respective delay elements overlap or intersect with the respective second sections of the two respective delay elements (claimed structure shown in figures 7A and 7B).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the arrangement for determining a unique printed circuit board identifier having delay elements as taught by Lewis with the delay elements being a conductive first/top and second/bottom sections that are connected through vias on a circuit board and overlap at one point as taught by Chen because Chen states, “the embedded stereographic inductor can concentrate electromagnetic field distribution in the central region of the inter-helix spiral coil, thereby reducing electromagnetic radiation and energy loss and improving quality factor” [paragraph 0034]. This particular delay element structure will reduce energy loss.
Regarding claim 11 – Lewis in view of Chen teach the arrangement as claimed in claim 10, wherein the electrical through contacts (Chen; figs. 7A-7B, see via shown connecting the first and second sections) which are respectively employed by two delay elements (the electrical through contacts are connected to elements 440 & 430 that are considered the two delay elements) are arranged adjacently on the printed circuit board (410; claimed structure shown in figure 7A).
Regarding claim 14 – Lewis in view of Chen teach the arrangement as claimed in claim 10, further comprising: a memory unit (Lewis; fig. 17, memory based AUF Cell) in which the printed circuit board identifier is permanently saved ([paragraph 0131] Lewis states, “numerous memory based AUF cells 3100 would then be operated as described for the ring oscillator based and Arithmetic based AUF cells such that one or more cell 3200 would be dedicated as a reference cell for compensation purposes and one or more cells 3300 could be selected a minuend for result scaling”).
Regarding claim 15 – Lewis in view of Chen teach the arrangement as claimed in claim 14, wherein the memory unit (Lewis; fig. 17, memory based AUF Cell) is configured to be activatable to permanently save the printed circuit board identifier ([paragraph 0131] Lewis states, “numerous memory based AUF cells 3100 would then be operated as described for the ring oscillator based and Arithmetic based AUF cells such that one or more cell 3200 would be dedicated as a reference cell for compensation purposes and one or more cells 3300 could be selected a minuend for result scaling”).
It has been held that the recitation that an element is “capable of” performing a function is not a positive limitation but only requires the ability to so perform. It does not constitute a limitation in any patentable sense. In re Hutchinson, 69 USPQ 138.
Regarding claim 20 – Lewis in view of Chen teach the arrangement as claimed in claim 10, wherein the electronic component (Lewis; fig. 530) comprises an application-specific integrated circuit ([paragraph 0121] Lewis states, “These integrated circuits 530, 532, 534 may be digital, analog, power electronics, or optical in nature or identified by some other technology”; digital, analog, power or optical is considered “application-specific”).
Allowable Subject Matter
Claims 13 and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 1/16/2026 have been fully considered but they are not persuasive.
Applicant argues regarding the secondary reference Chen (US PG. Pub. 2009/0045904) in the rejection of claim 10, “This publication provides no teaching or suggestion that the inductor devices disclosed therein can be used as delay elements formed as printed conductors routed on a printed circuit board. Applicants believe the inductor devices of Chen constitute fundamentally different devices from the delay element described in applicants’ published application…Applicants’ field of endeavor is directed to application-specific integrated circuits (ASICs). The field of endeavor of Chen, in contrast, is directed to inductor design and fabrication. Chen fails the first prong of the test…Applicants’ claimed invention addresses the problem of how to determine a unique printed circuit board identifier, which has nothing to do fabricating inter-helix inductor devices and Chen therefore fails both prongs of the test because Chen is not in same filed of endeavor of applicants’ claimed invention, nor is Chen reasonably pertinent to the problem addressed by applicants’ claimed invention” [REMARKS page 6-7].
Examiner disagrees. In response to applicant's argument that Chen is nonanalogous art, it has been held that a prior art reference must either be in the field of the inventor’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992).
In this case, the instant application is directed (and claimed) specifically to a printed circuit board (see claim 10) with a first section routed on a first conductive layer and a second section routed on a second conductive layer and connected via electrical through-contacts. Chen in figure 7A also shows a circuit structure with the equivalently instant claimed structure. Both the instant application and Chen are directed to physical circuit structures. Applicant has not pointed out explicitly how the prior art reference Chen is not within the same field of endeavor beyond mere allegation. The wiring structure shown in Chen meets the instant applications claims and also appears to be equivalent to that of the instant applications drawings in figures 1 and 2.
Examiner additionally points to MPEP2141.01(a)I which states, “When determining whether the "relevant field of endeavor" test is met, the examiner should consider "explanations of the invention’s subject matter in the patent application, including the embodiments, function, and structure of the claimed invention." Airbus S.A.S. v. Firepass Corp., 941 F.3d 1374, 1380, 2019 USPQ2d 430083 (Fed. Cir. 2019) (quoting Bigio, 381 F.3d at 1325, 72 USPQ2d at 1212)…The Federal Circuit reads KSR as "direct[ing] us to construe the scope of analogous art broadly" because "familiar items may have obvious uses beyond their primary purposes, and a person of ordinary skill often will be able to fit the teachings of multiple patents together like pieces of a puzzle." Wyers v. Master Lock Co., 616 F.3d 1231, 1238, 95 USPQ2d 1525, 1530 (Fed. Cir. 2010) (quoting KSR, 550 U.S. at 402, 127 S. Ct. at 1727)”.
Therefore it is reasonable to consider Chen to be analogous art to that of the instant application.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm.
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/STEVEN T SAWYER/ Primary Examiner, Art Unit 2847