DETAILED ACTION
This Office Action is in response to the application filed on 24 August 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takeuchi et al. (US 2015/0236161 A1; hereinafter Takeuchi).
In regards to claim 1, Takeuchi teaches, e.g. in figs. 11 and 14, a thin film transistor (TFT) unit (Title), comprising:
a first gate (124) [0118], a first gate insulating layer (140) [0118], a first semiconductor layer (154) [0118] and a first source/drain electrode layer (e.g. portions of (154) under (173/175) respectively) [0118] that are sequentially arranged on a substrate (110) [0110], wherein the first source/drain electrode layer comprises a first source (173) [0115] and a first drain (175) [0115] that are spaced apart from each other along a first direction (fig. 14: horizontally spaced apart); and
a floating electrode (TFM) [0134] disposed on a side of the first semiconductor layer away from the first gate insulating layer (fig. 14: (TFM) is on the upper side of (154) away from (140)), wherein in the first direction, an orthographic projection of the floating electrode on the substrate falls between an orthographic projection of the first source on the substrate and an orthographic projection of the first drain on the substrate (figs. 11 and 14: the plan view projection of (TFM) is in between the plan view footprints of (173) and (175)) [0134];
wherein the orthographic projection of the floating electrode on the substrate is at least partially overlapped with an orthographic projection of the first semiconductor layer on the substrate (figs. 11 and 14: the plan view footprint of (TFM) overlaps the plan view footprint of (154));
the orthographic projection of the floating electrode on the substrate, the orthographic projection of the first source on the substrate and the orthographic projection of the first drain on the substrate each are at least partially overlapped with an orthographic projection of the first gate on the substrate (figs. 11 and 14: (TFM), (173), and (175) overlap (124) in a plan view);
any two of the floating electrode, the first source and the first drain are at least partially overlapped in a second direction, and the second direction is perpendicular to the first direction (fig. 14: (TFM), (173), and (175) overlap in a horizontal direction orthogonal to a vertical direction).
In regards to claim 2, Takeuchi teaches the limitations discussed above in addressing claim 1. Takeuchi further teaches the limitations wherein the floating electrode (TFM), the first source (173); and the first drain (175) are disposed on a same layer (fig. 14) [0135].
In regards to claim 3, Takeuchi teaches the limitations discussed above in addressing claim 1. Takeuchi further teaches the limitations wherein a material of the floating electrode (TFM) comprises metal [0134].
In regards to claim 5, Takeuchi teaches the limitations discussed above in addressing claim 1. Takeuchi further teaches, e.g. in figs. 11 and 14, the limitations wherein the first source, the floating electrode and the first drain are equally spaced apart from each other in the first direction [0134].
In regards to claim 6, Takeuchi teaches, e.g. in figs. 11 and 14, a method for manufacturing a thin film transistor (TFT) unit (Title), comprising:
sequentially forming a first gate (124) [0118], a first gate insulating layer (140) [0118], a first semiconductor layer (154) [0118] and a first source/drain electrode layer (e.g. portions of (154) under (173/175) respectively) [0118] on a substrate (110) [0110], wherein the first source/drain electrode layer comprises a first source (173) [0115] and a first drain (175) [0115] that are spaced apart from each other along a first direction (fig. 14: horizontally spaced apart); and
forming a floating electrode (TFM) [0134] on a side of the first semiconductor layer away from the substrate (fig. 14: (TFM) is on the upper side of (154) away from (140)), wherein in the first direction, an orthographic projection of the floating electrode on the substrate falls between an orthographic projection of the first source on the substrate and an orthographic projection of the first drain on the substrate (figs. 11 and 14: the plan view projection of (TFM) is in between the plan view footprints of (173) and (175)) [0134];
wherein the orthographic projection of the floating electrode on the substrate is at least partially overlapped with an orthographic projection of the first semiconductor layer on the substrate (figs. 11 and 14: the plan view footprint of (TFM) overlaps the plan view footprint of (154));
the orthographic projection of the floating electrode on the substrate, the orthographic projection of the first source on the substrate and the orthographic projection of the first drain on the substrate each are at least partially overlapped with an orthographic projection of the first gate on the substrate (figs. 11 and 14: (TFM), (173), and (175) overlap (124) in a plan view);
any two of the floating electrode, the first source and the first drain are at least partially overlapped in a second direction, and the second direction is perpendicular to the first direction (fig. 14: (TFM), (173), and (175) overlap in a horizontal direction orthogonal to a vertical direction).
In regards to claim 7, Takeuchi teaches the limitations discussed above in addressing claim 6. Takeuchi further teaches, e.g. in figs. 11 and 14, the limitations wherein forming the first source/drain electrode layer (173/175) [0118] and the floating electrode (TFM) [0134] comprises:
forming a source/drain electrode film on the side of the first semiconductor layer away from the substrate [0135]; and
patterning the source/drain electrode film to obtain the first source, the first drain and the floating electrode [0135].
In regards to claim 8, Takeuchi teaches a shift register unit (fig. 1) [0066], wherein the shift register unit comprises a plurality of thin film transistors (TFTs) (TITLE), each of the thin film transistors (TFTs) comprises at least one TFT unit [0121], the plurality of TFTs comprise a plurality of target TFTs [0121], a source or drain of each of the target TFTs is connected to a pull-up node in the shift register unit [0077], at least one of the plurality of target TFTs comprises a target TFT unit, and the target TFT unit is of a target structure, wherein the target structure comprises:
a first gate (124) [0118], a first gate insulating layer (140) [0118], a first semiconductor layer (154) [0118] and a first source/drain electrode layer (e.g. portions of (154) under (173/175) respectively) [0118] that are sequentially arranged on a substrate (fig. 14), wherein the first source/drain electrode layer comprises a first source (173) and a first drain (175) that are spaced apart from each other along a first direction (fig. 14) [0134]; and
a floating electrode (TFM) disposed on a side of the first semiconductor layer away from the first gate insulating layer (fig. 14: (TFM) is on the upper side of (154) away from (140)), wherein in the first direction, an orthographic projection of the floating electrode on the substrate falls between an orthographic projection of the first source on the substrate and an orthographic projection of the first drain on the substrate (figs. 11 and 14: the plan view projection of (TFM) is in between the plan view footprints of (173) and (175)) [0134];
wherein the orthographic projection of the floating electrode on the substrate is at least partially overlapped with an orthographic projection of the first semiconductor layer on the substrate (figs. 11 and 14: the plan view footprint of (TFM) overlaps the plan view footprint of (154));
the orthographic projection of the floating electrode on the substrate, the orthographic projection of the first source on the substrate and the orthographic projection of the first drain on the substrate each are at least partially overlapped with an orthographic projection of the first gate on the substrate (figs. 11 and 14: (TFM), (173), and (175) overlap (124) in a plan view);
any two of the floating electrode, the first source and the first drain are at least partially overlapped in a second direction, and the second direction is perpendicular to the first direction (fig. 14: (TFM), (173), and (175) overlap in a horizontal direction orthogonal to a vertical direction).
In regards to claim 9, Takeuchi teaches the limitations discussed above in addressing claim 8. Takeuchi further teaches the limitations wherein each of the plurality of target TFT comprises the target TFT unit [0121].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi as applied to claim 8 above.
In regards to claim 17, Takeuchi teaches the limitations discussed above in addressing claim 8. Takeuchi further teaches, e.g. in figs. 11 and 14, the limitations wherein at least one of the plurality of TFTs comprises a source/drain electrode branch (173/175) and a floating electrode branch (TFM) (figs. 11 and 14) ([0118], [0134]); wherein the source/drain electrode branch constitutes a source and a drain of each TFT unit in the TFT, and the floating electrode branch constitutes a floating electrode of each TFT unit in the TFT (figs. 11 and 14) ([0118], [0134]).
Furthermore, the court in In re Harza held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced; therefore, one having ordinary skill in the art at the time the application at hand was filed would find it obvious to duplicate the number of branches of the source/drain electrode and the second number of floating electrode branches in the TFT taught by Takeuchi such that a difference between the number of respective branches is great than or equal than 1. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi as applied to claim 1 above, in view of Jang et al. (KR 2014-0021405 A; citations to attached English translation; hereinafter Jang).
In regards to claim 4, Takeuchi teaches the limitations discussed above in addressing claim 1. Takeuchi appears to be silent as to, but does not preclude, the limitations wherein a length of the floating electrode in the first direction, a length of the first source in the first direction and a length of the first drain in the first direction are equal. Jang teaches the limitations wherein a length of the floating electrode in the first direction, a length of the first source in the first direction and a length of the first drain in the first direction are equal (English translation page 4: source electrode (427), drain electrode (427), and floating electrode (430) all have a width of 5 μm). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Takeuchi with the aforementioned limitations taught by Jang such that the lengths of the elements of Takeuchi match the lengths of the elements taught by Jang to have desired electrical characteristics (Jang English translation page 4).
Claim(s) 14, 16, and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi as applied to claim 8 above, in view of Xu et al. (US 2020/0294461 A1; hereinafter Xu).
In regards to claim 14, Takeuchi teaches the limitations discussed above in addressing claim 8. Takeuchi appears to be silent as to, but does not preclude, the limitations wherein except the target TFT units, other TFT units in the plurality of TFTs each comprise a second gate, a second gate insulating layer, a second semiconductor layer and a second source/drain electrode layer that are sequentially arranged on the substrate, wherein the second source/drain electrode layer comprises a second source and a second drain that are spaced apart from each other, and the other TFT units do not comprise the floating electrode. Xu teaches the limitations wherein except the target TFT units, other TFT units in the plurality of TFTs each comprise a second gate, a second gate insulating layer, a second semiconductor layer and a second source/drain electrode layer that are sequentially arranged on the substrate, wherein the second source/drain electrode layer comprises a second source and a second drain that are spaced apart from each other, and the other TFT units do not comprise the floating electrode ([0064]: second gate, second gate insulating layer, second semiconductor layer, second source/drain implied by dual gate TFT). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Takeuchi with the aforementioned limitations taught by Xu to have a device with common TFT layouts (Xu [0064]).
In regards to claim 16, Takeuchi teaches the limitations discussed above in addressing claim 8. Takeuchi appears to be silent as to, but does not preclude, the limitations wherein each of the TFTs is an N-type transistor. Xu teaches the limitations wherein each of the TFTs is an N-type transistor [0014]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Takeuchi with the aforementioned limitations taught by Xu to have a device with common TFT layouts (Xu [0064]).
In regards to claim 18, Takeuchi teaches the limitations discussed above in addressing claim 8. Takeuchi appears to be silent as to, but does not preclude, the limitations of a display panel wherein the gate drive circuit comprises: at least two cascaded shift register units according to claim 8. Xu teaches the limitations of a display panel wherein the gate drive circuit comprises: at least two cascaded shift register units according to claim 8 [0107]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Takeuchi with the aforementioned limitations taught by Xu to have a device with common TFT layouts (Xu [0064]).
In regards to claim 19, the combination of Takeuchi and Xu teaches the limitations discussed above in addressing claim 18. Takeuchi further teaches the limitations of a display panel wherein the display panel comprises a substrate and the gate drive circuit according to claim 18, wherein the gate drive circuit is disposed on the substrate (fig. 3) [0027].
In regards to claim 20, the combination of Takeuchi and Xu teaches the limitations discussed above in addressing claim 19. Takeuchi further teaches the limitations of a display apparatus, comprising a power supply assembly and the display panel according to claim 19; wherein the power supply assembly is configured to supply power to the display panel [0060].
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Takeuchi and Xu as applied to claim 14 above, in view of Cho et al. (US 2015/0171114 A1; hereinafter Cho).
In regards to claim 15, the combination of Takeuchi and Xu teaches the limitations discussed above in addressing claim 14. Takeuchi further teaches the limitations wherein a length of a channel of the target TFT unit is twice a length of each of channels of the other TFT units [0118].
The combination of Takeuchi and Xu appears to be silent as to, but does not preclude, the limitations wherein the channel of the target TFT unit is a part of the first semiconductor layer which is overlapped with the first gate and is not overlapped with the floating electrode, the first source and the first drain, the channel of each of the other TFT units is a part of the second semiconductor layer which is overlapped with the second gate and is not overlapped with the second source and the second drain, and a length direction of the channel is parallel to an arrangement direction of the second source and the second drain of the transistor. Cho teaches the limitations wherein the channel of the target TFT unit is a part of the first semiconductor layer which is overlapped with the first gate and is not overlapped with the floating electrode, the first source and the first drain, the channel of each of the other TFT units is a part of the second semiconductor layer which is overlapped with the second gate and is not overlapped with the second source and the second drain, and a length direction of the channel is parallel to an arrangement direction of the second source and the second drain of the transistor (figs. 6, 9, 13, 17, etc.). It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by the combination of Takeuchi and Xu with the aforementioned limitations taught by Cho such that the parts of the device taught by Takeuchi are rearranged since the court in In re Japikse held that a rearranging of parts of a device that does not modify the operation of said device would be obvious. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950), see also MPEP §2144.04 VI C.
Allowable Subject Matter
Claims 10-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: wherein the shift register unit comprises an input circuit, a first reset circuit, an output circuit, a second reset circuit, a first pull control circuit, a first pull circuit, a second pull control circuit, a second pull circuit, and a storage capacitor; wherein the input circuit comprises a first transistor, wherein a gate and a first electrode of the first transistor are connected to a signal input terminal, and a second electrode of the first transistor is connected to the pull-up node; the first reset circuit comprises a second transistor and a third transistor, wherein a gate of the second transistor is connected to a first reset signal terminal, a first electrode of the second transistor is connected to the pull-up node, and a second electrode of the second transistor is connected to a first fixed voltage terminal; and a gate of the third transistor is connected to the first reset signal terminal, a first electrode of the third transistor is connected to a first output terminal, and a second electrode of the third transistor is connected to a second fixed voltage terminal; the output circuit comprises a first output transistor and a second output transistor, wherein a gate of the first output transistor is connected to the pull-up node, a first electrode of the first output transistor is connected to a clock signal terminal, and a second electrode of the first output transistor is connected to the first output terminal; and a gate of the second output transistor is connected to the pull-up node, a first electrode of the second output transistor is connected to the clock signal terminal, and a second electrode of the second output transistor is connected to a second output terminal; the second reset circuit comprises a fourth transistor, wherein a gate of the fourth transistor is connected to a second reset signal terminal, a first electrode of the fourth transistor is connected to the pull-up node, and a second electrode of the fourth transistor is connected to the first fixed voltage terminal; the first pull control circuit comprises a fifth transistor, a sixth transistor and a seventh transistor, wherein a gate and a first electrode of the fifth transistor are connected to a first control terminal, and a second electrode of the fifth transistor is connected to a first pull-down node; a gate of the sixth transistor is connected to the pull-up node, a first electrode of the sixth transistor is connected to the first pull-down node, and a second electrode of the sixth transistor is connected to the first fixed voltage terminal; and a gate of the seventh transistor is connected to the signal input terminal, a first electrode of the seventh transistor is connected to the first pull-down node, and a second electrode of the seventh transistor is connected to the first fixed voltage terminal; the first pull circuit comprises an eighth transistor, a ninth transistor and a tenth transistor, wherein a gate of the eighth transistor is connected to the first pull-down node, a first electrode of the eighth transistor is connected to the pull-up node, and a second electrode of the eighth transistor is connected to the first fixed voltage terminal; a gate of the ninth transistor is connected to the first pull-down node, a first electrode of the ninth transistor is connected to the second output terminal, and a second electrode of the ninth transistor is connected to the first fixed voltage terminal; and a gate of the tenth transistor is connected to the first pull-down node, a first electrode of the tenth transistor is connected to the first output terminal, and a second electrode of the tenth transistor is connected to the second fixed voltage terminal; the second pull control circuit comprises an eleventh transistor, a twelfth transistor and a thirteenth transistor, wherein a gate and a first electrode of the eleventh transistor are connected to a second control terminal, and a second electrode of the eleventh transistor is connected to a second pull-down node; a gate of the twelfth transistor is connected to the pull-up node, a first electrode of the twelfth transistor is connected to the second pull-down node, and a second electrode of the twelfth transistor is connected to the first fixed voltage terminal; and a gate of the thirteenth transistor is connected to the signal input terminal, a first electrode of the thirteenth transistor is connected to the second pull-down node, and a second electrode of the thirteenth transistor is connected to the first fixed voltage terminal; the second pull circuit comprises a fourteenth transistor, a fifteenth transistor and a sixteenth transistor, wherein a gate of the fourteenth transistor is connected to the second pull-down node, a first electrode of the fourteenth transistor is connected to the pull-up node, and a second electrode of the fourteenth transistor is connected to the first fixed voltage terminal; a gate of the fifteenth transistor is connected to the second pull-down node, a first electrode of the fifteenth transistor is connected to the second output terminal, and a second electrode of the fifteenth transistor is connected to the first fixed voltage terminal; and a gate of the sixteenth transistor is connected to the second pull-down node, a first electrode of the sixteenth transistor is connected to the first output terminal, and a second electrode of the sixteenth transistor is connected to the second fixed voltage terminal; and a first electrode of the storage capacitor is connected to the pull-up node, and a second electrode of the storage capacitor is connected to the first output terminal; wherein one of the first electrode and second electrode of each transistor is the source and the other one is the drain.
The claims of the application at hand that depend from claims objected to as allowable but dependent from rejected claims are also objected to as allowable because they respectively depend, directly or indirectly, from the objected claims of the application at hand. Therefore, the dependent claims in question incorporate the allowable limitations of the claims from which they depend.
Conclusion
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Patent Examiner, Art Unit 2812