DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 have been examined.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(a)-(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The instant application claims priority to Chinese Application CN202110311617.5, filed March 24, 2021 and International Application PCT/CN2022/081526 filed March 17, 2022.
Information Disclosure Statement
The Applicant's submission of the Information Disclosure Statements dated August 25, 2023 and September 2, 2024 is acknowledged by the Examiner and the cited references have been considered in the examination of the claims now pending, except as otherwise indicated. The citation of the Japanese reference the 20223 IDS fails to comply with 37 CFR 1.98(a)(3). Copies of the PTOL-1449s initialed and dated by the Examiner are attached to the instant office action.
Drawings
The drawings are objected to because of the following informalities.
The identification of the drawings does not include an application or docket number. The figures therefore fail to comply with 37 CFR 1.84(c), which states, “Identifying indicia should be provided, and if provided, should include the title of the invention, inventor’s name, and application number, or docket number (if any) if an application number has not been assigned to the application. If this information is provided, it must be placed on the front of each sheet within the top margin.”
The format of the view numbers is “Fig.” rather than “FIG.” The figures therefore fail to comply with 37 CFR 1.84(u)(1), which states, “View numbers must be preceded by the abbreviation "FIG."
The format of the view numbers is at the bottom of the page rather than the top. The view numbers are also too small. The figures therefore fail to comply with 37 CFR 1.84(t), which states, “The sheets of drawings should be numbered in consecutive Arabic numerals, starting with 1, within the sight as defined in paragraph (g) of this section. These numbers, if present, must be placed in the middle of the top of the sheet, but not in the margin. The numbers can be placed on the right-hand side if the drawing extends too close to the middle of the top edge of the usable surface. The drawing sheet numbering must be clear and larger than the numbers used as reference characters to avoid confusion. The number of each sheet should be shown by two Arabic numerals placed on either side of an oblique line, with the first being the sheet number and the second being the total number of sheets of drawings, with no other marking.” (emphasis supplied)
The lines in several places, e.g., around the computational arrays in Figures 1 and 2, are faint, blurry, fuzzy, and pixelated. The figures therefore fail to comply with 37 CFR 1.84(l), which states, “All drawings must be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views.”
The text in Figures 2-4 is too small. The text also, in Figure 2, is placed on hatched surfaces. The figures therefore fail to comply with 37 CFR 1.84(p)(3), which states, “Numbers, letters, and reference characters must measure at least .32 cm. (1/8 inch) in height. They should not be placed in the drawing so as to interfere with its comprehension. Therefore, they should not cross or mingle with the lines. They should not be placed upon hatched or shaded surfaces. When necessary, such as indicating a surface or cross section, a reference character may be underlined and a blank space may be left in the hatching or shading where the character occurs so that it appears distinct.” (emphasis supplied)
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the Applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The abstract includes language that can be implied, e.g., “The present disclosure discloses.” The abstract therefore fails to comply with 37 CFR 1.72. As explained at MPEP § 608.01(b), “The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc. In addition, the form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided.”
Appropriate correction is required. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which Applicant may become aware in the specification.
Claim Objections
Claims 1-20 are objected to because of the following informalities.
Claim 1 recites, “at least two the computation modules.” This appears to be a typographical error. Applicant may have intended “at least two of the computation modules.” Claim 10 has similar language and is similarly objected to.
Claim 3 recites, “no the data path.” This appears to be a typographical error. Applicant may have intended “no [[the]] data path.” Claim 18 has similar language and is similarly objected to.
Claim 3 recites, “the first-stage the computational array.” This appears to be a typographical error. Applicant may have intended “the first-stage of the computational array.” Claims 4, 18, and 19 have similar language and are similarly objected to.
Claim 5 recites, “control output data.” This appears to be a typographical error. Applicant may have intended “controlling output data.” Claim 20 has similar language and is similarly objected to.
Claims 9, 14, 15, and 16 are improperly ordered. As indicated at MPEP § 608.01(n), “A claim which depends from a dependent claim should not be separated therefrom by any claim which does not also depend from said "dependent claim."”
Claims 2-9 and 11-20 are objected to as depending from objected to base claims and failing to remedy the deficiencies of those claims. Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are as follows.
a reconfiguration configuration unit in claims 1, 4, 10, and 19. No sufficient structure is disclosed in the specification.
at least one computation module in claims 1, 3-7, 10, 12, 13, and 18-20. No sufficient structure is disclosed in the specification.
a computation control unit in claims 4-9, 12, 14-16, 19, and 20. No sufficient structure is disclosed in the specification.
a compensation unit in claims 4-9, 12, 14-16, 19, and 20. No sufficient structure is disclosed in the specification.
a first interconnection unit in claims 4-9, 12, 14-16, 19, and 20. No sufficient structure is disclosed in the specification.
a second interconnection unit in claims 4-9, 12, 14-16, 19, and 20. No sufficient structure is disclosed in the specification.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “a reconfiguration configuration unit is configured to provide….” The disclosure does not provide adequate structure to perform the claimed function of providing the reconfiguration information. The specification does not demonstrate that applicant has made an invention that achieves the claimed function because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. Claims 4, 10, and 19 have similar language and are similarly rejected.
Claim 1 recites “at least one computation module…synchronously output….” The disclosure does not provide adequate structure to perform the claimed function of synchronous output. The specification does not demonstrate that applicant has made an invention that achieves the claimed function because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. Claims 3-7, 10, 12, 13, and 18-20 have similar language and are similarly rejected.
Claim 4 recites “a computation control unit…configured to be selectively connected….” The disclosure does not provide adequate structure to perform the claimed function of being selectively connected. The specification does not demonstrate that applicant has made an invention that achieves the claimed function because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. Claims 4-9, 12, 14-16, 19, and 20 have similar language and are similarly rejected.
Claim 4 recites “a compensation unit…configured to select….” The disclosure does not provide adequate structure to perform the claimed function of selecting. The specification does not demonstrate that applicant has made an invention that achieves the claimed function because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. Claims 4-9, 12, 14-16, 19, and 20 have similar language and are similarly rejected.
Claim 4 recites “a first connection unit …configured to connect….” The disclosure does not provide adequate structure to perform the claimed function of connecting. The specification does not demonstrate that applicant has made an invention that achieves the claimed function because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. Claims 4-9, 12, 14-16, 19, and 20 have similar language and are similarly rejected.
Claim 4 recites “a second connection unit …configured to connect….” The disclosure does not provide adequate structure to perform the claimed function of connecting. The specification does not demonstrate that applicant has made an invention that achieves the claimed function because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention. Claims 4-9, 12, 14-16, 19, and 20 have similar language and are similarly rejected.
Claims 2-9 and 11-20 are rejected as depending from rejected base claims and failing to cure the deficiencies of those base claims.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the Applicant regards as the invention.
Claim 1 recites “a reconfiguration configuration unit is configured to provide….” This limitation invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed function. There is no disclosure of any particular structure, either explicitly or inherently, to perform the providing. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which structure or structures perform(s) the claimed function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. Claims 4, 10, and 19 have similar language and are similarly rejected.
Claim 1 recites “at least one computation module…synchronously output….” This limitation invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed function. There is no disclosure of any particular structure, either explicitly or inherently, to perform the synchronous output. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which structure or structures perform(s) the claimed function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. Claims 3-7, 10, 12, 13, and 18-20 have similar language and are similarly rejected.
Claim 1 recites, at lines 10-11, “at least one computation module is set in each stage of the computational array.” This limitation is indefinite because the limitation suggests multiple stages per computational array. This contradicts the rest of the claim and the written description, which discloses single stage comprises a single computational array. Also, “the computational array” lacks antecedent basis. For purposes of examination, the limitation is interpreted as, “at least one computation module is set in each stage of the reconfigurable array.” Claims 2-7, 10, 12, and 14-20 include similar limitations and are similarly rejected.
Claim 1 recites, at lines 11-12, “one stage of the computational array.” This limitation is indefinite because the limitation suggests multiple stages per computational array, which contradicts the rest of the claim and the written description. Also, “the computational array” lacks antecedent basis. For purposes of examination, the limitation is interpreted as, “one stage of the reconfigurable array.” Claims 2-7, 10, 12, and 14-20 include similar limitations and are similarly rejected.
Claim 1 recites, at lines 15-16, “only one the computational array is set on each column of one the reconfigurable array, and the computational array on each the column is one stage of the computational array.” The language of this limitation is confusing and grammatically incorrect, rendering the scope of the claim indefinite. Also, “the computational array” lacks antecedent basis. For purposes of examination, the limitation is interpreted as, “only one [[the]] computational array is set on each column of [[one]] the reconfigurable array, and the one computational array on the each [[the]] column is one stage of the reconfigurable array.”
Claim 1 recites, at line 16, “the number of the computational arrays in the reconfigurable array is preset and these computational arrays exist in the reconfigurable array in the form of a cascaded structure.” The antecedent basis for several of the terms in this limitation is unclear, rendering the scope of the claim indefinite. For purposes of examination, the limitation is interpreted as, “the reconfigurable array comprises a preset number of computational arrays, and the preset number of computational arrays are configured in a cascaded structure.”
Claim 1 recites, at line 16, “each stage of pipeline of the data path pipeline structure.” The limitation includes language that is redundant and confuses the scope of the claim. For purposes of examination, the limitation is interpreted as, “each stage of the data path pipeline structure.”
Claim 1 recites, at lines 19 and 20, “the computational array.” This limitation lacks antecedent basis. For purposes of examination, the limitation is interpreted as, “the reconfigurable array.”
Claim 1 recites, at line 20, “the computational module.” This limitation lacks antecedent basis. For purposes of examination, the limitation is interpreted as, “[[the]] a computational module.”
Claim 1 recites, at lines 20-21, “in each stage of the computational array, the computation module connected to the data path pipeline structure is equivalent to a corresponding stage of the pipeline.” It cannot be determined what it means for the computation module to be equivalent to a corresponding stage. For purposes of examination, the limitation is interpreted as referring to the coupling corresponding computation modules in adjacent stages.
Claim 1 recites, at line 23, “the pipeline depth is time consumed.” The meaning of this limitation cannot be determined. For purposes of examination, the limitation is interpreted as indicating that time is required for data to be processed.
Claim 3 recites “the same stage.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, the limitation is interpreted as, “[[a]] the same stage.” Claims 10, 13, and 18 have similar language and are similarly rejected.
Claim 3 recites “the computation modules in a current stage.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, the limitation is interpreted as, “[[the]] computation modules in a current stage.” Claim 18 has similar language and is similarly rejected.
Claim 3 recites “lower” and “higher.” The meaning of these terms cannot be determined based on the specification and claims. For purposes of examination, the limitations are interpreted as preceding and succeeding, respectively.
Claim 4 recites, “the current stage.” There are multiple possible antecedent bases for this term, rendering the scope of the claim indefinite. Claims 5, 6, 7, 9, 12, and 18-20 have similar language and are similarly rejected.
Claim 4 recites “the same computation module.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, the limitation is interpreted as, “[[the]] a same computation module.” Claims 6, 12, and 19 have similar language and are similarly rejected.
Claim 4 recites “a computation control unit…configured to be selectively connected….” This limitation invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed function. There is no disclosure of any particular structure, either explicitly or inherently, to perform the selective connection. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which structure or structures perform(s) the claimed function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. Claims 4-9, 12, 14-16, 19, and 20 have similar language and are similarly rejected.
Claim 4 recites “a compensation unit…configured to select….” The disclosure does not provide adequate structure to perform the claimed function of selecting. This limitation invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed function. There is no disclosure of any particular structure, either explicitly or inherently, to perform the selecting. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which structure or structures perform(s) the claimed function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. Claims 4-9, 12, 14-16, 19, and 20 have similar language and are similarly rejected.
Claim 4 recites “a first connection unit …configured to connect….” This limitation invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed function. There is no disclosure of any particular structure, either explicitly or inherently, to perform the connecting. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which structure or structures perform(s) the claimed function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. Claims 4-9, 12, 14-16, 19, and 20 have similar language and are similarly rejected.
Claim 4 recites “a second connection unit …configured to connect….” This limitation invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. The specification is devoid of adequate structure to perform the claimed function. There is no disclosure of any particular structure, either explicitly or inherently, to perform the connecting. The specification does not provide sufficient details such that one of ordinary skill in the art would understand which structure or structures perform(s) the claimed function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. Claims 4-9, 12, 14-16, 19, and 20 have similar language and are similarly rejected.
Claim 5 recites “the register path.” There is insufficient antecedent basis for this limitation in the claim. For purposes of examination, the limitation is interpreted as, “the matched register path.” Claims 6 and 20 have similar language and are similarly rejected.
Claim 6 recites “the stored generated the delay difference.” This language is grammatically incorrect and renders the scope of the claim indefinite. For purposes of examination, the limitation is interpreted as “the delay difference.”
Claim 11 recites, at lines 26-37, limitations that are all essentially already present in the claim. This renders the scope of the claims indefinite because it cannot be determined how many times these operations are to be performed. Also, the duplicate language introduces a number of antecedent basis limitations. For purposes of examination, the claim is interpreted as only requiring a single instance of the duplicative limitations.
Claims 2-9 and 11-20 are rejected as depending from rejected base claims and failing to cure the indefiniteness of those base claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 10-12, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Publication No. 2019/0377580 by Vorbach et al. (as cited by Applicant and hereinafter referred to as “Vorbach”).
Regarding claim 1, Vorbach discloses:
a reconfigurable processor, the reconfigurable processor comprising a reconfiguration configuration unit and a reconfigurable array (Vorbach discloses, at Figure 4 and related description, a processor that includes an instruction issue unit, i.e., configuration unit, and an array of ALUs and associated circuitry, i.e., a reconfigurable array. See also, e.g., ¶ [0098] et seq. Issuing instructions to the various ALUs is interpreted as reconfiguration. See, e.g., ¶ [0164] et seq.),
wherein the reconfiguration configuration unit is configured to provide, according to an algorithm matched with a current application scenario, reconfiguration information used for reconfiguring a computation structure in the reconfigurable array (Vorbach discloses, at Figure 4 and related description, the instruction issuing unit issues instructions to the ALU stages. The instructions indicate the operations to be performed for a particular program, which reconfigures which ALUs are active, i.e., the structure.);
the reconfigurable array comprises at least two stages of computational arrays, the reconfigurable array is configured to connect, according to the reconfiguration information provided by the reconfiguration configuration unit, adjacent two stages of the computational arrays to form a data path pipeline structure satisfying computation requirements of the algorithm matched with the current application scenario; at least one computation module is set in each stage of the computational array; in a case that at least two the computation modules are set in one stage of the computational array, pipeline depths of different computation modules connected to the data path pipeline structure are equal, such that the different computation modules connected to the data path pipeline structure synchronously output data (Vorbach discloses, at Figure 4 and related description, multiple rows (stages) of ALUs. Based on the instructions, which are based on the desired algorithm, adjacent rows are connected. At least one ALU (computation module) in each stage is set. Vorbach also discloses, at ¶ [0270] et seq., buffering data to ensure that all data from a stage is available at the same time.);
only one the computational array is set on each column of one the reconfigurable array, and the computational array on each the column is one stage of the computational array; the number of the computational arrays in the reconfigurable array is preset, and these computational arrays exist in the reconfigurable array in the form of a cascaded structure (Vorbach discloses, at Figure 4, a single row (computational array) per stage, with the stages cascaded, e.g., 411 and 412. As disclosed, e.g., at ¶ [0111], the processor includes multiple blocks of ALUs, which discloses multiple rows. The number of rows is understood to be preset at fabrication.);
each stage of pipeline of the data path pipeline structure corresponds to one stage of the computational array; in each stage of the computational array, the computation module connected to the data path pipeline structure is equivalent to a corresponding stage of the pipeline connected to the data path pipeline structure (Vorbach discloses, at Figure 4, each row (computational array) is coupled to a data path.); and
the pipeline depth is time consumed for data to flow through the corresponding data path of the data path pipeline structure (Vorbach discloses, at Figure 4, data being input to the ALUs, which perform operations. This is understood to consume time.).
Regarding claim 2, Vorbach discloses the elements of claim 1, as discussed above. Vorbach also discloses:
the reconfigurable processor further comprises an input FIFO group and an output FIFO group (Vorbach discloses, at ¶ [0195], input and output FIFOs.);
output ends of the input FIFO group are respectively in corresponding connection with input ends of the reconfigurable array, and the reconfigurable array is configured to receive, according to the reconfiguration information, data-to-be-computed transmitted from the input FIFO group, and transmit the data-to-be-computed to the data path pipeline structure (Vorbach discloses, at ¶ [0195], receiving operand data from input FIFOs and operating on the data, which discloses receiving from the output ends of the input FIFOs and transmitting on the data path pipeline according to reconfiguration information.); and
input ends of the output FIFO group are respectively in corresponding connection with output ends of the reconfigurable array, and the reconfigurable array is further configured to provide, according to the reconfiguration information, output data of one stage of the computational array corresponding to a last-stage pipeline of the data path pipeline structure to the output FIFO group (Vorbach discloses, at ¶ [0195], outputting results, which discloses transmitting to the input ends of the output FIFOs from the last stage of the pipeline.).
Regarding claim 10, Vorbach discloses:
a configuration method based on a reconfigurable processor, the reconfigurable processor comprising a reconfiguration configuration unit and a reconfigurable array (Vorbach discloses, at Figure 4 and related description, a processor that includes an instruction issue unit, i.e., configuration unit, and an array of ALUs and associated circuitry, i.e., a reconfigurable array. See also, e.g., ¶ [0098] et seq. Issuing instructions to the various ALUs is interpreted as reconfiguration. See, e.g., ¶ [0164] et seq.),
wherein the reconfiguration configuration unit is configured to provide, according to an algorithm matched with a current application scenario, reconfiguration information used for reconfiguring a computation structure in the reconfigurable array (Vorbach discloses, at Figure 4 and related description, the instruction issuing unit issues instructions to the ALU stages. The instructions indicate the operations to be performed for a particular program, which reconfigures which ALUs are active, i.e., the structure.);
the reconfigurable array comprises at least two stages of computational arrays, the reconfigurable array is configured to connect, according to the reconfiguration information provided by the reconfiguration configuration unit, adjacent two stages of the computational arrays to form a data path pipeline structure satisfying computation requirements of the algorithm matched with the current application scenario; at least one computation module is set in each stage of the computational array; in a case that at least two the computation modules are set in one stage of the computational array, pipeline depths of different computation modules connected to the data path pipeline structure are equal, such that the different computation modules connected to the data path pipeline structure synchronously output data (Vorbach discloses, at Figure 4 and related description, multiple rows (stages) of ALUs. Based on the instructions, which are based on the desired algorithm, adjacent rows are connected. At least one ALU (computation module) in each stage is set. Vorbach also discloses, at ¶ [0270] et seq., buffering data to ensure that all data from a stage is available at the same time.);
only one the computational array is set on each column of one the reconfigurable array and the computational array on each the column is one stage of the computational array; the number of the computational arrays in the reconfigurable array is preset, and these computational arrays exist in the reconfigurable array in the form of a cascaded structure (Vorbach discloses, at Figure 4, a single row (computational array) per stage, with the stages cascaded, e.g., 411 and 412. As disclosed, e.g., at ¶ [0111], the processor includes multiple blocks of ALUs, which discloses multiple rows. The number of rows is understood to be preset at fabrication.);
each stage of pipeline of the data path pipeline structure corresponds to one stage of the computational array; in each stage of the computational array, the computation module connected to the data path pipeline structure is equivalent to a corresponding stage of the pipeline connected to the data path pipeline structure (Vorbach discloses, at Figure 4, each row (computational array) is coupled to a data path.); and
the pipeline depth is time consumed for data to flow through the corresponding data path of the data path pipeline structure (Vorbach discloses, at Figure 4, data being input to the ALUs, which perform operations. This is understood to consume time.),
the configuration method comprising: connecting, according to computation requirements of an algorithm matched with a current application scenario, adjacent stages of computational arrays of reconfigurable array to form a data path pipeline structure which supports data to pass, with the equal pipeline depth, through different computation modules within the same stage of the computational array and satisfies the computation requirements of the algorithm matched with the current application scenario (Vorbach discloses, at Figure 4 and related description, multiple rows (stages) of ALUs. Based on the instructions, which are based on the desired algorithm, adjacent rows are connected. At least one ALU (computation module) in each stage is set. Vorbach also discloses, at ¶ [0270] et seq., buffering data to ensure that all data from a stage is available at the same time.),
each stage of pipeline of the data path pipeline structure corresponding to one stage of the computational array, the computation module connected to a data path within a current stage of the computational array being a current stage of the pipeline connected to the data path pipeline structure (Vorbach discloses, at Figure 4, each row (computational array) is coupled to a data path.), and
the pipeline depth being time consumed for data to flow through the corresponding data path of the data path pipeline structure (Vorbach discloses, at Figure 4, data being input to the ALUs, which perform operations. This is understood to consume time.).
Regarding claim 11, Vorbach discloses the elements of claim 10, as discussed above. Vorbach also discloses:
configuring the reconfigurable array to receive data-to-be-computed transmitted from an input FIFO group, and transmitting the data-to-be-computed to the data path pipeline structure, and meanwhile configuring the reconfigurable array to output a computation result of a computational array corresponding to a last stage of the data path pipeline structure to an output FIFO group, the reconfigurable processor comprises the input FIFO group and the output FIFO group (Vorbach discloses, at ¶ [0195], receiving operand data from input FIFOs and operating on the data and outputting results, which discloses transmitting to the input ends of the output FIFOs from the last stage of the pipeline.).
Regarding claim 12, Vorbach discloses the elements of claim 11, as discussed above. Vorbach also discloses:
a specific configuration method for connecting to form the data path pipeline structure comprises: judging, within one computation module of the current stage of the computational array, whether the current stage of the computational array is detected as a first-stage pipeline corresponding to the data path pipeline structure or not, in a case that the current stage of the computational array is detected as the first-stage pipeline corresponding to the data path pipeline structure, connecting a first interconnection unit and a computation control unit to form the first-stage pipeline of the data path pipeline structure, and configuring the first interconnection unit to input data-to-be-computed output by a matched output end within the input FIFO group to the computation control unit; in a case that the current stage of the computational array is not detected as the first-stage pipeline corresponding to the data path pipeline structure, connecting the first interconnection unit and the computation control unit to form the current stage of the pipeline of the data path pipeline structure, and configuring the first interconnection unit to input the computation result output by a matched computation module within adjacent previous stage of the computational array to the computation control unit (Vorbach discloses, at Figure 4 and related description, receiving data from input FIFOs, in the case of the first stage, or preceding stages, in the case of stages other than the first stage. Doing so encompasses configuring corresponding interconnection units.);
judging whether the current stage of the computational array is detected as a corresponding last-stage pipeline or not, in a case that the current stage of the computational array is detected as the corresponding last-stage pipeline, connecting a second interconnection unit and a compensation unit to form the last-stage pipeline of the data path pipeline structure, and configuring the second interconnection unit to transmit data subject to delay compensation processing by the compensation unit to a matched output FIFO within the output FIFO group; and in a case that the current stage of the computational array is not detected as the corresponding last-stage pipeline, connecting the second interconnection unit and the compensation unit to form the current stage of the pipeline of the data path pipeline structure, and configuring the second interconnection unit to transmit the data subject to delay compensation processing by the compensation unit to a matched computation module within adjacent next stage of the computational array (Vorbach discloses, at Figure 4 and related description, transmitting data to output FIFOs, in the case of the last stage, or to subsequent stages, in the case of stages other than the last stage. Doing so encompasses configuring corresponding interconnection units and sending according to configured delay, as disclosed, e.g., at ¶ [0869].);
judging whether the computation control unit detects a computation gating signal or not, in a case that the computation control unit detects the computation gating signal, configuring data, input into the computation control unit, to be output to the compensation unit after computation is executed, and in a case that the computation control unit not detects the computation gating signal, configuring the data, input into the computation control unit, to directly pass and be transmitted to the compensation unit without executing the computation, the computation gating signal is used for controlling data transmitted by the first interconnection unit to be selectively output between the data through path and the data computation path, so as to satisfy the computation requirements of the algorithm in each stage of the pipeline of the data path pipeline structure (Vorbach discloses, at Figure 4 and related description, selectively enabling ALUs via instructions issued to the stages that include the ALUs. This discloses a signal to either perform a computation or to bypass the ALUs. See also ¶ [0446] et seq.);
and then, configuring the compensation unit to select a corresponding delay difference to perform delay processing on the output data of the computation control unit within the same computation module, so as to perform delay compensation on the pipeline depth of the same computation module to the maximum pipeline depth allowed by the current stage of the computational array, the maximum pipeline depth allowed by the current stage of the computational array being the pipeline depth of the computation control unit where it takes the longest time for data to flow through the data path within the current stage of computational array, the computation module comprises the computation control unit, the compensation unit, the first interconnection unit and the second interconnection unit, in the same computation module of each stage of the computational array, an input end of the first interconnection unit being an input end of the computation module, an output end of the first interconnection unit being connected with an input end of the computation control unit, an output end of the computation control unit being connected with an input end of the compensation unit, an output end of the compensation unit being connected with an input end of the second interconnection unit, and an output end of the second interconnection unit being an output end of the computation module (Vorbach discloses, e.g., at ¶ [0869], delaying outputs to match the slowest operation in a stage. See also, ¶ [1179]. This discloses the claimed arrangement, i.e., receive data, operate (or not) on the data, delay the data (if needed), and output the data.).
Regarding claim 17, Vorbach discloses the elements of claim 10, as discussed above. Vorbach also discloses:
the reconfigurable processor further comprises an input FIFO group and an output FIFO group (Vorbach discloses, at ¶ [0195], input and output FIFOs.);
output ends of the input FIFO group are respectively in corresponding connection with input ends of the reconfigurable array, and the reconfigurable array is configured to receive, according to the reconfiguration information, data-to-be-computed transmitted from the input FIFO group, and transmit the data-to-be-computed to the data path pipeline structure (Vorbach discloses, at ¶ [0195], receiving operand data from input FIFOs and operating on the data, which discloses receiving from the output ends of the input FIFOs and transmitting on the data path pipeline according to reconfiguration information.); and
input ends of the output FIFO group are respectively in corresponding connection with output ends of the reconfigurable array, and the reconfigurable array is further configured to provide, according to the reconfiguration information, output data of one stage of the computational array corresponding to a last-stage pipeline of the data path pipeline structure to the output FIFO group (Vorbach discloses, at ¶ [0195], outputting results, which discloses transmitting to the input ends of the output FIFOs from the last stage of the pipeline.).
Claim Rejections - 35 US