DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, claims 1-9 and 16-20 in the reply filed on 07/08/2026 is acknowledged. The traversal is on the ground(s) that the amended claims 1 and 10, filed on 07/08/2026 along with the response the restriction requirement, have corresponding technical features. In the spirit of compact prosecution, the examiner agrees to examine claims 1-20.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/21/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the first lead terminal is electrically connected to a first layer of sub-coil of the first coil structure in a direction away from the dielectric substrate, and the second lead terminal is electrically connected to a first layer of sub-coil of the N-th coil structure in the direction away from the dielectric substrate” as recited in claim 4, the “an i-th layer of sub-coil and an (i+1)-th layer of sub-coil of the second coil structure are electrically connected through a transfer electrode that is composed of at least one layer of sub-coil in (i+2)-th to (i+k−1)-th layers of sub-coils in the first coil structure” as claimed in claim 9 and similar limitations in claim 15 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4-7, 9, 12, 13, 15 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4, applicant should clarify what’s intended by “the first lead terminal is electrically connected to a first layer of sub-coil of the first coil structure in a direction away from the dielectric substrate, and the second lead terminal is electrically connected to a first layer of sub-coil of the N-th coil structure in the direction away from the dielectric substrate” as recited. Specifically, it’s not clear the “direction away from” relationship between the first layer of sub-coil of the first coil structure and the dielectric substrate. As seen in FIGs. 15-24, the present invention appears to show the N coils structure on substrate 10, and the sub-coils of the N coil and substrate are parallel. So, if the sub-coils are parallel with the substrate, the examiner is not clear how “a first layer of sub-coil of the first coil structure” is “in a direction away from the dielectric substrate” as claimed. While the specification appears to disclose the claimed limitations in question, there’s no further explanation as to how the sub-coil is in a direction away from the dielectric substrate.
Similar rejection is applied to claims 5-7, 12 and 13.
Regarding claim 9, it’s not clear what’s intended by “an i-th layer of sub-coil and an (i+1)-th layer of sub-coil of the second coil structure are electrically connected through a transfer electrode that is composed of at least one layer of sub-coil in (i+2)-th to (i+k−1)-th layers of sub-coils in the first coil structure” as recited in the last paragraph of the claim. Specifically, it’s not clear if “a transfer electrode that is composed of at least one layer of sub-coil in (i+2)-th to (i+k−1)-th layers of sub-coils in the first coil structure” means the transfer electrode is the same material as of one layer of sub-coil in (i+2)-th to (i+k−1)-th layers of sub-coils in the first coil structure” or else.
Similar rejection is applied to claim 15.
Claim 20 is rejected under 35 USC 112(b) as being dependent from claim 3, and therefore inheriting the indefiniteness thereof.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 10-14 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Merrill et al. (U.S. Patent No. 5,610,433, hereinafter “Merrill”).
With respect to claim 1, Merrill teaches an inductor 10 (FIGs. 1-10) comprising a dielectric substrate 60 (FIG. 2, substrate 60 is made of silicon (col. 3, lines 23-25)), which has dielectric properties) and N coil structures M1-M3 (FIG. 3)disposed on the dielectric substrate, wherein the N coil structures are nested and electrically connected in sequence, wherein N is an integer greater than or equal to 2; wherein,
any one of the coil structures comprises a plurality of layers of sub-coils (inner M1s or outer M1s) formed on the dielectric substrate in sequence, and at least one interlayer insulating layer 70 and or 72 is disposed between sub-coils disposed adjacently, and adjacent layers of sub-coils are electrically connected through a first connection via 40 and or 34, or 16 and or 22 penetrating the interlayer insulating layer between the adjacent layers of sub-coils (col. 2, lines 45-62, and col. 3, lines 23-25 and 53—67).
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With respect to claim 2, Merrill teaches the inductor of claim 1, further comprising a first lead terminal 11 and a second lead terminal 48, wherein the first lead terminal is electrically connected to a head end 18 (FIG. 1) of a first coil structure (coil structure of inner sub-coils M1), and the second lead terminal is electrically connected to a tail end 46 of an N-th coil structure (col. 2, lines 36-38, 45-50 and 59-61).
With respect to claim 3, Merrill teaches the inductor of claim 2, wherein the first lead terminal and the second lead terminal are disposed in a same layer (top or bottom layer) and of a same material (col. 2, lines 64-67).
With respect to claim 4, best understood in view of 35 USC 112(b) rejection, Merrill teaches the inductor of claim 3, wherein the first lead terminal is electrically connected to a first layer (bottom or top layer) of sub-coil of the first coil structure in a direction away from the dielectric substrate, and the second lead terminal is electrically connected to a first layer (bottom or top layer) of sub-coil of the N-th coil structure in the direction away from the dielectric substrate (col. 2, lines 64-67).
With respect to claim 5, best understood in view of 35 USC 112(b) rejection, Merrill teaches the inductor of claim 4, wherein the first lead terminal is disposed in a same layer (top or bottom layer) as the first layer of sub-coil of the first coil structure in the direction away from the dielectric substrate, and the first lead terminal and the first layer of sub-coil of the first coil structure are integrally formed; and/or,
the second lead terminal is disposed in a same layer as the first layer of sub-coil of the N-th coil structure in the direction away from the dielectric substrate, and the second lead terminal and the first layer of sub-coil of the N-th coil structure are integrally formed (col. 2, lines 45-53 and lines 64-67).
With respect to claim 6, best understood in view of 35 USC 112(b) rejection, Merrill teaches the inductor of claim 3, wherein the first lead terminal is electrically connected to a last layer (top or bottom layer) of sub-coil of the first coil structure in a direction away from the dielectric substrate, and the second lead terminal is electrically connected to a last layer (top or bottom layer) of sub-coil of the N-th coil structure in the direction away from the dielectric substrate (col. 2, lines 45-53 and lines 64-67).
With respect to claim 7, best understood in view of 35 USC 112(b) rejection, Merrill teaches the inductor of claim 6, wherein the first lead terminal is disposed in a same layer (top or bottom layer) as the last layer of sub-coil of the first coil structure in the direction away from the dielectric substrate, and the first lead terminal and the last layer of sub-coil of the first coil structure are integrally formed; and/or,
the second lead terminal is disposed in a same layer as the last layer of sub-coil of the N-th coil structure in the direction away from the dielectric substrate, and the second lead terminal and the last layer of sub-coil of the N-th coil structure are integrally formed (col. 2, lines 45-53 and lines 64-67).
With respect to claim 8, Merrill teaches the inductor of claim 1, wherein each of the N coil structures comprises M layers of the sub-coils, wherein M is an integer greater than or equal to 2; sub-coils of k-th layers in all coil structures are disposed in a same layer, wherein k is an integer greater than or equal to 1 and less than or equal to N (col. 2, lines 45-50).
With respect to claim 10, Merrill teaches a method for manufacturing an inductor 10 (FIGs. 1-10), comprising: providing a dielectric substrate 60 (FIG. 2, substrate 60 is made of silicon (col. 3, lines 23-25)), forming N coil structures on the dielectric substrate, wherein the N coil structures are nested and electrically connected in sequence; wherein N is an integer greater than or equal to 2; wherein an act of forming any coil structure comprises:
forming, in sequence, a plurality of layers of sub-coils (inner M1s or outer M1s), and forming at least one interlayer insulating layer 70 and or 72 between adjacent layers of sub-coils on the dielectric substrate; wherein adjacent layers of sub-coils are electrically connected through a first connection via 40 and or 34, or 16 and or 22 penetrating the interlayer insulating layer between the adjacent layers of sub-coils (col. 2, lines 45-62, and col. 3, lines 23-25 and 53—67).
With respect to claim 11, Merrill teaches the method for manufacturing an inductor of claim 10, further comprising forming a first lead terminal 11 and a second lead terminal 48 on the dielectric substrate, wherein the first lead terminal is electrically connected to a head end 12 (FIG. 1) of a first coil structure (inner coils M1), and the second lead terminal is electrically connected to a tail end 46 of an N-th coil structure (col. 2, lines 36-38, 45-50 and 59-61).
With respect to claim 12, best understood in view of 35 USC 112(b) rejection, Merrill teaches the method for manufacturing an inductor of claim 11, wherein the first lead terminal and a first layer of sub-coil of the first coil structure in a direction away from the dielectric substrate are formed by a single patterning process; and/or,
the second lead terminal and a first layer of sub-coil of the N-th coil structure in the direction away from the dielectric substrate are formed by a single patterning process (col. 2, lines 45-53 and lines 64-67, col. 3, lines 55-64).
With respect to claim 13, best understood in view of 35 USC 112(b) rejection, Merrill teaches the method for manufacturing an inductor of claim 11, wherein the first lead terminal and a last layer of sub-coil of the first coil structure in a direction away from the dielectric substrate are formed by a single patterning process; and/or,
the second lead terminal and a last layer of sub-coil of the N-th coil structure in the direction away from the dielectric substrate are formed by a single patterning process(col. 2, lines 45-53 and lines 64-67, col. 3, lines 55-64).
With respect to claim 14, Merrill teaches the method for manufacturing an inductor of claim 10, wherein each of the N coil structures comprises M layers of sub-coils, wherein M is an integer greater than or equal to 2; sub-coils of k-th layers in all coil structures are formed by a single patterning process, wherein k is an integer greater than or equal to 1 and less than or equal to N (col. 2, lines 45-53 and lines 64-67, col. 3, lines 55-64).
With respect to claim 16, Merrill teaches a filter comprising the inductor of claim 1 (col. 1, lines 13-16).
With respect to claim 17, Merrill teaches the an electronic device comprising the filter of claim 16 (col. 1, lines 13-16).
With respect to claim 18, Merrill teaches the inductor of claim 2, wherein each of the N coil structures comprises M layers of the sub-coils, wherein M is an integer greater than or equal to 2; sub-coils of k-th layers in all coil structures are disposed in a same layer, wherein k is an integer greater than or equal to 1 and less than or equal to N (col. 2, lines 36-38 and 45-50).
With respect to claim 19, Merrill teaches the inductor of claim 3, wherein each of the N coil structures comprises M layers of the sub-coils, wherein M is an integer greater than or equal to 2; sub-coils of k-th layers in all coil structures are disposed in a same layer, wherein k is an integer greater than or equal to 1 and less than or equal to N (col. 2, lines 36-38 and 45-50).
With respect to claim 20, Merrill teaches the inductor of claim 4, wherein each of the N coil structures comprises M layers of the sub-coils, wherein M is an integer greater than or equal to 2; sub-coils of k-th layers in all coil structures are disposed in a same layer, wherein k is an integer greater than or equal to 1 and less than or equal to N (col. 2, lines 36-38 and 45-50).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 9 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Merrill, as applied to claims 1 and 10 above, in view of Liu et al. (U.S. PG. Pub. No. 2002/0101322 A1, hereinafter “Liu”).
With respect to claim 9, Merrill teaches the inductor of claim 1. Merrill does not expressly teach quantities of layers in at least two coil structures in the N coil structures are not equal;
for any two of the coil structures with unequal quantities of layers of sub-coils, one of the any two coil structures comprises P layers of sub-coils, and the other one of the any two coil structures comprises Q layers of sub-coils; a coil structure comprising the P layers of sub-coils is referred to as a first coil structure, and a coil structure comprising the Q layers of sub-coils is referred to as a second coil structure, wherein P is an integer greater than or equal to 2, Q is an integer greater than or equal to 2, and P is greater than Q;
an i-th layer of sub-coil in the first coil structure and the i-th layer of sub-coil in the second coil structure are disposed in a same layer, and an (i+k)-th layer of sub-coil in the first coil structure and an (i+1)-th layer of sub-coil in the second coil structure are disposed in a same layer, wherein i is an integer greater than or equal to 1 and less than or equal to N, and k is an integer greater than or equal to 2 and less than or equal to N−i;
an i-th layer of sub-coil and an (i+1)-th layer of sub-coil of the second coil structure are electrically connected through a transfer electrode that is composed of at least one layer of sub-coil in (i+2)-th to (i+k−1)-th layers of sub-coils in the first coil structure.
Best understood in view of 35 USC 112(b) rejection, Liu teaches an inductor (FIG. 4), wherein quantities of layers in at least two coil structures in the N coil structures are not equal;
for any two of the coil structures (inner coils structure and outer coils structure) with unequal quantities of layers of sub-coils (inner coil layers and outer coil layers), one of the any two coil structures comprises P layers (four layers of inner coils) of sub-coils, and the other one of the any two coil structures comprises Q layers (three layers of outer coils) of sub-coils; a coil structure comprising the P layers of sub-coils is referred to as a first coil structure, and a coil structure comprising the Q layers of sub-coils is referred to as a second coil structure, wherein P is an integer greater than or equal to 2, Q is an integer greater than or equal to 2, and P is greater than Q;
an i-th layer (layer of coil 441) of sub-coil in the first coil structure and the i-th layer (layer of coil 442) of sub-coil in the second coil structure are disposed in a same layer, and an (i+k)-th layer (layer of coil 431) of sub-coil in the first coil structure and an (i+1)-th layer (layer of coil 432) of sub-coil in the second coil structure are disposed in a same layer, wherein i is an integer greater than or equal to 1 and less than or equal to N, and k is an integer greater than or equal to 2 and less than or equal to N−i;
an i-th layer of sub-coil and an (i+1)-th layer of sub-coil of the second coil structure are electrically connected through a transfer electrode (via connection between coil 442 and 432) that is composed of at least one layer of sub-coil in (i+2)-th to (i+k−1)-th layers of sub-coils in the first coil structure (paras. [0029] and [0030]).
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It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have the at least two coil structures in the N coil structures as taught by Liu to the inductor of Merrill to provide an inductor that exhibits a marked increase in the inductance to unit area ratio (para. [0009]).
With respect to claim 15, Merrill teaches the method for manufacturing an inductor of claim 10. Merrill does not expressly teach quantities of layers in at least two coil structures in the N coil structures are not equal;
for any two of the coil structures with unequal quantities of layers of sub-coils, one of the any two coil structures comprises P layers of sub-coils, and the other one of the any two coil structures comprises Q layers of sub-coils; a coil structure comprising the P layers of sub-coils is referred to as a first coil structure, and a coil structure comprising the Q layers of sub-coils is referred to as a second coil structure, wherein P is an integer greater than or equal to 2, Q is an integer greater than or equal to 2, and P is greater than Q;
an i-th layer of sub-coil in the first coil structure and the i-th layer of sub-coil in the second coil structure are formed by a single patterning process, and an (i+k)-th layer of sub-coil in the first coil structure and an (i+1)-th layer of sub-coil in the second coil structure are formed by a single patterning process, wherein i is an integer greater than or equal to 1 and less than or equal to N, and k is an integer greater than or equal to 2 and less than or equal to N−i;
an i-th layer of sub-coil and an (i+1)-th layer of sub-coil of the second coil structure are electrically connected through a transfer electrode that is composed of at least one layer of sub-coil in (i+2)-th to (i+k−1)-th layers of sub-coils in the first coil structure.
Best understood in view of 35 USC 112(b) rejection, Liu teaches a method for manufacturing an inductor (FIG. 4),
quantities of layers in at least two coil structures (inner coils structure and outer coils structure) in the N coil structures are not equal;
for any two of the coil structures with unequal quantities of layers of sub-coils, one of the any two coil structures comprises P layers (four layers of inner coils) of sub-coils, and the other one of the any two coil structures comprises Q layers (three layers of outer coils) of sub-coils; a coil structure comprising the P layers of sub-coils is referred to as a first coil structure, and a coil structure comprising the Q layers of sub-coils is referred to as a second coil structure, wherein P is an integer greater than or equal to 2, Q is an integer greater than or equal to 2, and P is greater than Q;
an i-th layer (layer of coil 441)of sub-coil in the first coil structure and the i-th layer (layer of coil 442) of sub-coil in the second coil structure are formed by a single patterning process, and an (i+k)-th layer (layer of coil 431) of sub-coil in the first coil structure and an (i+1)-th layer (layer of coil 432) of sub-coil in the second coil structure are formed by a single patterning process, wherein i is an integer greater than or equal to 1 and less than or equal to N, and k is an integer greater than or equal to 2 and less than or equal to N−i;
an i-th layer of sub-coil and an (i+1)-th layer of sub-coil of the second coil structure are electrically connected through a transfer electrode (via connection between coil 442 and 432) that is composed of at least one layer of sub-coil in (i+2)-th to (i+k−1)-th layers of sub-coils in the first coil structure (paras. [0029] and [0030]).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the method as taught by Liu to the method for manufacturing the inductor of Merrill to provide an inductor that exhibits a marked increase in the inductance to unit area ratio (para. [0009]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. A list of pertinent prior art is attached in form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MANGTIN LIAN whose telephone number is (571)270-5729. The examiner can normally be reached Monday-Friday 0800-1700.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shawki S. Ismail can be reached at 571-272-3985. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MANG TIN BIK LIAN/ Primary Examiner, Art Unit 2837
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