DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, and 5 are rejected under 35 U.S.C. 103 as being unpatentable over JP 2020013829 A (to Makino), as applied to claim 1 above, (cited on IDS) – translation attached previously and relied upon below, in view of WO 2011111676 A1 (to Takase et al.) – translation attached and relied upon below.
With respect to claim 1, Makino teaches a wiring module (Figures 1 & 3) that is attached to a plurality of power storage devices/(battery cells) (2), electrode terminals (3A & 3B) of the plurality of power storage devices (2) being arranged in two rows continuously in an aligning direction of the plurality of power storage devices (2) (as illustrated in Figure 1),
and the two rows of electrode terminals (3A & 3B) being separated from each other in a separation direction that is orthogonal to the aligning direction (as illustrated), the wiring module comprising:
a first substrate (32) that is flexible and has a plurality of first voltage detection lines (L2, L4, L6) on only one surface thereof (page 4, last 16 lines);
a second substrate (31) that is flexible and has a plurality of second voltage detection
lines (L1, L3, L5, L7) on only one surface thereof (page 4, last 16 lines); and
a connector (40),
wherein the plurality of first voltage detection lines (L2, L4, L6) are folded an odd number of times (one time – see the dashed lines connected to solid lines (36 – on the right side of the module (10) (Figures 1 & 3),
ends on one side of the first voltage detection lines (L2, L4, L6) are electrically connected to electrode terminals (3A & 3B) that form one row of the two rows of electrode terminals (3A & 3B),
ends on the other side of the first voltage detection lines (L2, L4, L6) are aligned in the
separation direction in an order of potentials of the electrode terminals (3A & 3B) electrically connected thereto via the first voltage detection lines (L2, L4, L6), and are electrically connected to the connector (40) (as illustrated), ends on one side of the second voltage detection lines (L1, L3, L5, L7) are electrically connected to electrode terminals (3A & 3B) that form the other row of the two rows of electrode terminals (3A & 3B), ends on the other side of the second voltage detection lines (L1, L3, L5, L7) are aligned in the separation direction in an order of potentials of the electrode terminals (3A & 3B) electrically connected thereto (page 4, 4th paragraph) via the second voltage detection lines (L1, L3, L5, L7), and are electrically connected to the connector (40), and the first voltage detection lines (L2, L4, L6) and the second voltage detection lines (L1, L3, L5, L7) are connected to the connector (40) from the same side in the aligning direction (as illustrated).
Makino fails to teach wherein the plurality of second voltage detection lines (L1, L3, L5, L7)
It would have been obvious to one having ordinary skill in the art at the time of filing for the invention to fold the second voltage detection lines an even number of times in Makino, as taught by Takase, in order to accommodate design and space limitations.
With respect to claim 2, Makino teaches wherein the surface of the first substrate (32) on which the ends on the other side of the first voltage detection lines (L2, L4, L6) are disposed and the surface of the second substrate (31) on which the ends on the other side of the second voltage detection lines (L1, L3, L5, L7) are disposed face each other (as illustrated in Figure 1).
With respect to claim 5, Makino teaches wherein the connector (40) includes first terminals (not shown- page 4, last 16 lines) that are connected to the ends on the other side of the first voltage detection lines (L2, L4, L6), and second terminals (not shown - page 4, last 16 lines) that are connected to the ends on the other side of the second voltage detection lines (L1, L3, L5, L7), the first terminals and the second terminals are aligned in a row in the separation direction (Figures 1 & 3), and the first terminals and the second terminals (the terminals within connector (40) though not shown, it is obvious in the figures that the ends of the first and second voltage lines (L1…L7) are alternately disposed in the separation direction (as illustrated in Figures 1 & 3), and are aligned in an order of potential (page 4, 4th paragraph).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over JP 2020013829 A (to Makino) in view of WO 2011111676 A1 (to Takase et al.), as applied to claim 1 above, and further in view of CN 102484385 A (to Kunimitsu et al.) – translation attached and relied upon below.
With respect to claim 3, Makino as modified discloses all claim limitations as set forth above but fails to teach wherein the first substrate includes a plurality of thermistor circuits on the surface of the first substrate on which the first voltage detection lines are disposed, ends on one side of the plurality of thermistor circuits are connected to a common ground potential, and ends on the other side of the plurality of thermistor circuits are connected to the connector, and are disposed between the ground potential and an end on the other side of a first voltage detection line connected to an electrode terminal that has the lowest potential.
Kunimitsu teaches a battery module (Figure 3, 100) comprising a plurality of battery cells (10), a plurality of positive and negative electrodes (10a & 10b) (Figure 4), a connector (Figure 19, 23/23c/23a) comprising a plurality of electrodes/(input and output terminals) (para. [0149]-[0150]), and substrates (Figure 19, 40) that include a plurality of thermistor (11) circuits on the surface of the first substrate (40) on which first voltage detection lines (52) are disposed (as illustrated), ends (27) on one side of the plurality of thermistor circuits (11) are connected to a common ground potential (GND1) (para. [0089], [0214]) (as illustrated in Figures 19 & 20), and ends (27) on the other side of the plurality of thermistor circuits (11) are connected to the connector (23/23a) (para. [0214]) (as illustrated in Figure 20), and are disposed between the ground potential (GND2) and an end on the other side of a first voltage detection line (52) (within connector (23a)) (see Figure 18) connected to an electrode terminal that has the lowest potential/(negative electrode) (para. [0181]-[0183], [0316]) (see also Figure 25) in order to mount the detector circuit and communication circuit on a common printed circuit board for improved and stable circuit communication (para. [0025]).
It would have been obvious to one having ordinary skill in the art at the time of filing for the invention to have the first substrate include a plurality of thermistor circuits on the surface of the first substrate on which the first voltage detection lines are disposed, ends on one side of the plurality of thermistor circuits are connected to a common ground potential, and ends on the other side of the plurality of thermistor circuits are connected to the connector, and are disposed between the ground potential and an end on the other side of a first voltage detection line connected to an electrode terminal that has the lowest potential in the apparatus of modified Makino, as taught by Kunimitsu, in order to mount the detector circuit and communication circuit on a common printed circuit board for improved and stable circuit communication.
Claims 6 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over JP 2020013829 A (to Makino) in view of WO 2011111676 A1 (to Takase et al.), as applied to claim 1 above, and further in view of Groshert et al. (US 2017/0271642 A1).
With respect to claim 6, Makino as modified discloses all claim limitations as set forth above but fails to teach providing a protector that protects the first substrate and the second substrate. Groshert teaches a battery module comprising a plurality of battery cells (para. [0070]), and a substrate/(support element (102)) which supports voltage detection lines/(current conductor system (104)) (para. [0070]), and a protector/(cover (108)) that is placeable on the substrate/(support element (102)) (para. [0070], [0078]-[0080]) in order to protect the components of the battery module and wiring system from any damage.
It would have been obvious to one having ordinary skill in the art at the time of filing for the invention to have the apparatus of modified Makino comprise a protector/cover that protects the first substrate and the second substrate, as taught by Groshert, in order to protect the components of the battery module and wiring system from any damage.
With respect to claim 10, Takase further teaches wherein the ECU (Figure 2, 17) is positioned on-top of the battery modules (as illustrated); therefore, placing the ECU (5) and the connector (40) of Makino (as illustrated in Figure 6 of Makino) on top of the battery module would provide that the protector/cover (108 – taught by Groshert above) covering the substrate would further support and protect the connector (158).
It would have been obvious to one having ordinary skill in the art at the time of filing for the invention to place the connector of Makino on top of the battery module, as taught by Takase, in order for the protector/cover taught by Groshert to support and protect the connector.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over JP 2020013829 A (to Makino) in view of WO 2011111676 A1 (to Takase et al.), as applied to claim 1 above, and further in view of WO 2011093105 A1 (to Kishimoto et al.) – translation attached and relied upon below.
With respect to claim 7, Makino as modified discloses all claim limitations as set forth above but fails to teach wherein each of the ends on the one side of the first voltage detection lines is connected to one of the electrode terminals via a metal piece and a bus bar, and
each of the ends on the one side of the second voltage detection lines is connected to one of the electrode terminals via a metal piece and a bus bar.
Kishimoto teaches a battery module comprising a substrate (Figure 14, 50) supporting a first voltage detection lines (51) and a second voltage detection lines (52) wherein each of the ends on the one side of the first voltage detection lines (51) is connected to one of the electrode terminals (Figure 15, 22) (page 16, last 2 paragraphs) via a metal piece (46) and a bus bar (40) (as illustrated in Figure 14), and
each of the ends on the one side of the second voltage detection lines (52) is connected to one of the electrode terminals (Figure 15, 22) via a metal piece (46) and a bus bar (40) in order to provide a reliable electrical connection.
It would have been obvious to one having ordinary skill in the art at the time of filing for the invention to connect each of the ends on the one side of the first voltage detection lines to one of the electrode terminals via a metal piece and a bus bar, and to connect each of the ends on the one side of the second voltage detection lines to one of the electrode terminals via a metal piece and the bus bar of modified Makino, as taught by Kishimoto, in order to provide a reliable electrical connection.
With respect to claim 8, Kishimoto further teaches wherein each of the ends on the one side of the second voltage detection lines (52) is connected to the metal piece (46) through soldering, and the bus bar (40) is connected to the metal piece (46) through welding (page 16, lines 12-22).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over JP 2020013829 A (to Makino) in view of WO 2011111676 A1 (to Takase et al.) in view of CN 102484385 A (to Kunimitsu et al.), as applied to claim 3 above, and further in view of CN 101685898 A (to Yano et al.) – translation attached and relied upon below.
With respect to claim 9, Makino as modified discloses all claim limitations as set forth above but fails to teach wherein each of the plurality of thermistor circuits (taught by Kunimitsu) is disposed on a temperature measuring piece provided on the first substrate.
Yano teaches a battery module comprising voltage detection lines (Figure 7, 8), and thermistor circuits (not numbered) that are connected to a cell state detecting circuit (30) (as illustrated), wherein each of the plurality of thermistor circuits (not numbered) is disposed on a temperature measuring piece (38) (as illustrated) provided on the first substrate (Figure 5, 7) in order to provide a means for measuring the temperature of the respective battery cell units (1).
It would have been obvious to one having ordinary skill in the art at the time of filing for the invention to dispose each of the plurality of thermistor circuits in the battery module of modified Makino on a temperature measuring piece provided on the first substrate, as taught by Yano, in order to provide a means for measuring the temperature of the respective battery cell units.
Product-by-process limitations are not given weight in apparatus claims. Therefore, the recited limitations of “the temperature measuring piece is provided by making a cut in the first substrate, and folding a cut portion toward a central portion of a corresponding power storage device of the plurality of power storage devices in the separation direction” are not given weight as they are directed to the process of making the instantly claimed “temperature measuring piece”.
Response to Arguments
Applicant’s arguments with respect to claims 1-3 and 5-10 have been considered but are moot because the new ground of rejection does not rely on the same combination of references applied in the prior rejection of record as necessitated by applicant’s amendments to the claims.
Allowable Subject Matter
Claim 4 is allowed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KAITY V CHANDLER/ 9/29/2026Primary Examiner, Art Unit 1725
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