DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 8 and 10-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by CHEN et al. (CN106549459 A, hereinafter CHEN).
Regarding claims 1 and 11, CHEN discloses an electronic device (See Fig.5, discloses a phone), wherein the electronic device comprises an interface (See Fig.1, discloses a USB-C interface), a voltage detection circuit (See Par.18, discloses detecting a voltage of CC pin in the USB -C interface), and a processor (See Par.21, discloses the monitoring circuit comprising an analog to digital converter (ADC) provides the output measurement to a processor), wherein
the interface is configured to connect a power supply device (See Fig.5, discloses “charger” connected to the other end of cable); the interface comprises a first pin (See Fig.1, Pin A5 “CC Pin” ) and a second pin (See Fig.1, Pin A4 “VBUS pin”), the first pin being configured to transmit a data signal (See Fig.1, CC pin discloses a configuration pin, normal function of the pin in a USB-C interface. Applicant’s specification identifies CC pins among a plurality of other pins to be data pins [Par.49]), and the second pin being configured to transmit a charging voltage signal (See Fig.1, VBUS pin discloses a power delivery pin, normal function for pin in USB-C interface); and
the voltage detection circuit is respectively connected to the first pin and the processor (See Par.18 and 21, disclose an ADC for detecting the voltage on the CC pin and providing the measurement to a processor);
the voltage detection circuit is configured to:
detect a voltage of the first pin (See Pars.18 and 21 and Fig.9, disclose CC1 and CC2 as inputs to the ADC); and the processor is configured to:
determine a second voltage value according to the voltage of the first pin when the power supply device transmits a charging voltage signal with a first voltage value to the second pin and the power supply devices supports fast charging (See Pars.20-29, disclose detecting a voltage on the CC pin and based on the value of the voltage transmit a signal set the charging voltage),
wherein determining the second voltage value comprises:
determining the second voltage value to be a first value when the voltage of the first pin is no less than a preset first threshold (See Pars.26-29 and 50, disclose when the detected voltage on the CC pin is greater than a certain value, then asking for safe charging voltage. Par.75, discloses the safe voltage to be 5V); and
determining the second voltage value to be a second value when the voltage of the first pin is less than the preset first threshold (See Pars.26-29, disclose when the detected CC pin voltage is less than a threshold, then requesting a high-voltage charging from the charger); the first value being less than the second value (See Pars.70 and 74, disclose the safe voltage charging is 5V while the high-voltage charging is 9V), the first threshold being less than or equal to the first voltage value and greater than a maximum voltage value of the data signal transmitted by the first pin (See Par.11, discloses the threshold voltage May be 0.7V); and
send the second voltage value to the power supply device for the power supply device to adjust a voltage value of the charging voltage signal to the second voltage value (See Par.29, discloses the electronic device requests a safe voltage or a high-voltage from the charger).
Regarding claim 3, CHEN discloses the electronic device according to claim 1 as discussed above, wherein the electronic device further comprises a protocol processing circuit (See Par.22, discloses the processor determines the charging voltage (protocol as safe or high-voltage) based on the measured CC Pin voltage. This implicitly indicates the presence of a protocol processing circuit), the protocol processing circuit being respectively connected to a third pin of the interface and the processor, the third pin being configured to transmit a data signal (See Pars.22 and 26-29, disclose the processor compares the measured voltage to a threshold and selects a protocol based on the comparison. This is interpreted to mean that the processor sends the output of the comparison to the protocol processing circuit which selects the appropriate charging protocol safe or high-voltage); and the processor is further configured to:
when sending the second voltage value to the power supply device, send the second voltage value to the protocol processing circuit (See Pars.22 and 26-29, disclose the processor compares the measured voltage to a threshold and selects a protocol based on the comparison. This is interpreted to mean that the processor sends the output of the comparison to the protocol processing circuit which selects the appropriate charging protocol safe or high-voltage); and
the protocol processing circuit is configured to: send the second voltage value to the power supply device through the third pin of the interface (See Fig.1, discloses pins D+/D-, it is well known that these pins are used for data exchange between the electronic device and the charger).
Regarding claim 8, CHEN discloses the electronic device according to claim 1 as discussed above, wherein when detecting the voltage of the first pin, the voltage detection circuit is further configured to:
compare the voltage of the first pin with the preset first threshold, and send a comparison result to the processor (See Pars.26-29).
Regarding claim 10, CHEN discloses the electronic device according to claim 1 as discussed above, wherein the interface is a Type-C interface (See Fig.1 and Par.18, disclose a USB-C interface), the second pin is a VBUS pin (See Fig.1, claim 1 rejection VBUS/A9 is the second pin), and the first pin is any data pin in the Type-C interface (See Fig.1, claim 1 rejection A5, CC pin is the first pin).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHEN.
Regarding claim 4, CHEN discloses the electronic device according to claim 1 as discussed above, wherein the voltage detection circuit comprises:
a first analog-to-digital converter (ADC) (See Fig.9, discloses an ADC connected to CC1 and CC2), wherein an input terminal of the voltage detection circuit is configured to connect the first pin (See Fig.9, discloses input terminals of ADC are connected to CC1 and CC2 and Par.69, discloses CC1 and CC2 are inputs to the ADC), and an output terminal is configured to connect the processor (See Par.21, discloses the output of the monitoring circuit is connected to the processor);
the input terminal of the voltage detection circuit is connected to an input terminal of the first ADC (See Fig.9, discloses the CC1/CC2 inputs are connected to the input of the ADC via resistors);
an output terminal of the first ADC is taken as the output terminal of the voltage detection circuit (See Par.21, discloses the ADC output is provided to the processor); and the first ADC is configured to:
convert a received analog voltage signal into a digital voltage signal, and send the digital voltage signal to the processor (See Par.21, ADC inherently converts analog measurements to digital).
However, CHEN does not disclose the input terminal of the ADC is connected via a first resistor.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention disclosed by CHEN by adding a resistor to the input of the ADC for the benefit of reducing noise in the ADC converter.
Regarding claim 5, CHEN discloses the electronic device according to claim 4 as discussed above, wherein that the input terminal of the voltage detection circuit is connected to an input terminal of the first ADC through the first resistor comprises:
the input terminal of the voltage detection circuit being grounded through a second resistor and a third resistor connected in series (See Fig.9, discloses terminals CC1 and CC2 are connected to ground “GND” via resistor connected in series), and a connection terminal of the second resistor and the third resistor being connected to the input terminal of the first ADC through the first resistor [ See claim 4 rejection above discloses the first resistor is connected to the input of the ADC for filtering and noise suppression]).
Regarding claim 6, CHEN discloses the electronic device according to claim 4, wherein that the input terminal of the voltage detection circuit is connected to an input terminal of the first ADC through the first resistor comprises:
the input terminal of the voltage detection circuit being connected to the input terminal of the first ADC through a switch and the first resistor connected in series (See Fig.9, discloses 3 switches connecting CC1, CC2 and VBUS to the input of the ADC, as modified in claim 4 a first resistor is connected at the input of the ADC in series with the switches); and
a control terminal of the switch being connected to the processor; and the processor is configured to:
control the switch to be on when determining that the power supply device supports fast charging; and control the switch to be off after determining the second voltage value (See Par.69 and Fig.9, disclose the switch is activated to determine the CC pin voltage after which the switches are deactivated and VBUS is connected).
Regarding claim 7, CHEN discloses the electronic device according to claim 4 as discussed above, wherein the first ADC is located in a power management unit (PMU) of the electronic device, or located in the processor (See Par.22, discloses ADC is built into an interface conversion chip. The examiner explains that adding an ADC in a processor is routine and well known in the part to reduce the size of the circuitry).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHEN in view of HUYNH (US 2022/0393692 A1, hereinafter HUYNH).
Regarding claim 9, CHEN discloses the electronic device according to claim 8 as discussed above, wherein the voltage detection circuit comprises: an input terminal of the voltage detection circuit configured to connect the first pin (See Fig.9, discloses inputs of ADC are connected to CC1 and CC2), and an output terminal configured to connect the processor (See Par.21, discloses the output of the voltage monitoring is connected to processor). However, CHEN does not disclose wherein the input terminal of the voltage detection circuit is connected to a first input terminal of a comparator through a fourth resistor, a second input terminal of the comparator is connected to a reference voltage terminal, a voltage at the reference voltage terminal is the first threshold, and an output terminal of the comparator is taken as the output terminal of the voltage detection circuit; and the comparator is configured to: compare voltages received by the first input terminal and the second input terminal, and output a comparison result.
HUYNH discloses a voltage detection circuit wherein the input terminal of the voltage detection circuit is connected to a first input terminal of a comparator (See Fig.4, discloses a comparator with an input connected to sensed voltage Vin [corresponds to pin voltage of CC pin]), a second input terminal of the comparator is connected to a reference voltage terminal, a voltage at the reference voltage terminal is the first threshold (See Fig.4, discloses comparator is connected to Vref. Vref is the threshold to which the Vin is compared), and an output terminal of the comparator is taken as the output terminal of the voltage detection circuit (See Fig.4, discloses the output of the comparator is input to digital circuit 410, combination of CHEN and HUYNH would provide the power of the comparator to the ADC); ; and the comparator is configured to: compare voltages received by the first input terminal and the second input terminal, and output a comparison result (See Fig.4, discloses the output of the comparator is the result of the comparison).
CHEN and HUYNH are analogous art since they both deal with voltage detection circuits.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention disclosed by CHEN with the teachings of HUYNH by using the disclosed voltage detection circuit for the benefit of increasing the accuracy of the voltage measurement.
However, CHEN and HUYNH do not disclose the input terminal of the comparator is connected via a fourth resistor.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention disclosed by CHEN and HUYNH by adding a resistor to the input of the ADC for the benefit of reducing noise in the measurement.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AHMED H OMAR whose telephone number is (571)270-7165. The examiner can normally be reached 10:00 am -7:00 PM EST.
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/AHMED H OMAR/ Primary Examiner, Art Unit 2859
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