DETAILED ACTION
This office action is in response to the application filed on 08/29/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/29/2023 has been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 3, 5, 11, 13 and 15-16 are objected to because of the following informalities: Claim 3 lines 6 and 12 “a voltage across a direct current bus” and “that the voltage is” this should be “a voltage across the direct current bus” and “that the sampled voltage is”. Claims 5 and 15-16 line 6 “as so to” should be “so as to”. Claim 11 recites as apparatus claim which is considered different from the method claim, claim 1 and should be separated. Claim 13 line 1 “claim 12” should be “claim 11”. Appropriate correction is required. Examiner’s Note: Claim 13 recites “wherein in a case that the inverter is a two stage inverter” and claim 12 recites “wherein in a casa that the inverter is a single state inverter”; the claims present two different scenarios so claim 13 should not depend from claim 12.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2 and 8-11 and 14 is/are rejected under 35 U.S.C. 102(a)(2) as being unpatentable by Pauletti et al. US 2020/0303949.
Regarding Claim 1, Pauletti teaches (Figures 1-5) a method for controlling a rapid shutdown system (fig. 1), comprising: applying an electrical signal disturbance (414) to a direct current bus (dc pwr) connected to a shutdown device (100) in the rapid shutdown system at least once within each pre-shutdown period of the shutdown device (Fig. 4, 400 before t1), by an inverter in the rapid shutdown system operating (par. 36) in a mode of limited power output (mode 1); sampling an input parameter and/or an output parameter of the shutdown device by the shutdown device (par. 63) and determining, by the shutdown device (100) based on the sampled input parameter and/or the sampled output parameter, whether the electrical signal disturbance applied to the direct current bus meets a preset condition (par. 63, shutdown condition occurring at t1); and switching the shutdown device on (at t1 in fig. 4) or maintaining the shutdown device in an ON state, in response to a determination result that the electrical-signal disturbance already meets the preset condition (shutdown conditions at t1). (For Example: Par. 37-44 and 61-70)
Regarding Claim 2, Pauletti teaches (Figures 1-5) wherein the inverter is a single-stage inverter (at 106) comprising only an inverter circuit, and the applying the electrical signal disturbance to the direct current bus connected to the shutdown device in the rapid shutdown system at least once within the pre-shutdown period of the shutdown device (See 400 and 412 in fig. 4 before t1) comprises: applying the electrical signal disturbance to the direct current bus (dc pwr, see fig. 2 the keep alive signal 108 is taken from 126, see par. 28 and 38) connected to the shutdown device in the rapid shutdown system at least once within the pre-shutdown period (before t1) by the inverter circuit under control of the inverter (par. 36). (For Example: Par. 37-44 and 61-70)
Regarding Claim 8, Pauletti teaches (Figures 1-5) wherein a preset duration (determined by S-FSK, par. 35), and at least one of the number of times (Fig. 4), a frequency and an amplitude of the electrical signal disturbance applied by the inverter within the pre- shutdown period depend on a power limit set for the inverter in the mode of limited power output (see par. 35 and Figure 4 before time t1 and between times t1-t2). (For Example: Par. 37-44 and 61-70)
Regarding Claim 9, Pauletti teaches (Figures 1-5) wherein the electrical signal disturbance is a current signal disturbance and/or a voltage signal disturbance (108, par. 28), or the electrical signal disturbance is a power signal disturbance. (For Example: Par. 37-44 and 61-70)
Regarding Claim 10, Pauletti teaches (Figures 1-5) further comprising: maintaining the shutdown device (100) in an OFF state in response to a determination result that the electrical signal disturbance does not meet the preset condition after the sampling the input parameter and/or the output parameter of the shutdown device by the shutdown device (staying in mode 1) and determining, by the shutdown device (100) based on the sampled input parameter and/or the sampled output parameter, whether the electrical-signal disturbance applied to the direct current bus connected to the shutdown device meets the preset condition (at t1 in Fig. 4 moving to mode 2). (For Example: Par. 37-44 and 61-70)
Regarding Claim 11, Pauletti teaches (Figures 1-5) a rapid shutdown system (Figure 1), comprising: an inverter (114); and at least one photovoltaic string (PV Cells), wherein for each of the at least one photovoltaic string, input terminals of shutdown devices (100, 202 and 222) in the photovoltaic string are connected to respective photovoltaic modules, output terminals of the shutdown devices are connected in series to form two terminals of the photovoltaic string (two terminals are dc pwr +/-), and the two terminals of the photovoltaic string (PV cells) are connected to a direct current end of the inverter through a direct current bus (110, see fig. 1); an alternating current end of the inverter is connected to a grid (output of the inverter 114); and the inverter is configured to perform, cooperating with each of the shutdown devices, the method according to claim 1 (see rejection to claim 1). (For Example: Par. 37-44 and 61-70)
Regarding Claim 14, Pauletti teaches (Figures 1-5) wherein the inverter is single-phase (116) or three-phase. (For Example: Par. 37-44 and 61-70)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pauletti in view of Yao US 20190326757.
Regarding Claim 12, Pauletti teaches (Figures 1-5) wherein in a case that the inverter is a single-stage inverter (114), the inverter comprises: a controller (controller for the inverter); an inverter circuit (114); a bus capacitor (348); and at least one driving circuit (driver of 114), wherein two terminals of the bus capacitor are connected to respective input terminals of the inverter circuit (at 110 and 112) through a direct current bus of the inverter (DC PWR); an output end of the inverter circuit serves as the alternating current end of the inverter (output inverter). (For Example: Par. 37-44 and 61-70)
Pauletti does not teach an output terminal of the driving circuit is connected to control terminals of respective switch transistors in the inverter circuit; and the controller is communicatively connected to the driving circuit, and is configured to send a control instruction to the driving circuit for the driving circuit to output a drive signal to the switch transistors.
Yao teaches (Figure 1-4 and 7) an output terminal of the driving circuit (74-75) is connected to control terminals of respective switch transistors (S3-S6) in the inverter circuit; and the controller (controller of the system) is communicatively connected to the driving circuit, and is configured to send a control instruction to the driving circuit for the driving circuit (with 73) to output a drive signal to the switch transistors (S3-S6). (For Example: Par. 52-53)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Pauletti teaches to include an output terminal of the driving circuit is connected to control terminals of respective switch transistors in the inverter circuit; and the controller is communicatively connected to the driving circuit, and is configured to send a control instruction to the driving circuit for the driving circuit to output a drive signal to the switch transistors, as taught by Yao in order to improve the safety of the photovoltaic power system.
Regarding Claim 13, Pauletti teaches (Figures 1-5)the rapid shutdown system.
Pauletti does not teach wherein in a case that the inverter is a two-stage inverter, the inverter further comprises: at least one Boost circuit, wherein input terminals of the Boost circuit serve as a pair of direct current terminals of the inverter, and a positive output terminal and a negative output terminal of the Boost circuit are connected to two terminals of the bus capacitor respectively; and the controller is connected to control terminals of switch transistors in the Boost circuit through the driving circuit.
Yao teaches (Figures 1-4 and 7) wherein in a case that the inverter is a two-stage inverter (see fig. 4), the inverter further comprises: at least one Boost circuit (boost circuit), wherein input terminals of the Boost circuit serve as a pair of direct current terminals of the inverter (see fig. 4), and a positive output terminal and a negative output terminal of the Boost circuit are connected to two terminals of the bus capacitor (Capacitor next to D1) respectively; and the controller (controller of the system) is connected to control terminals of switch transistors in the Boost circuit through the driving circuit (with 41 and driver 44). (For Example: Par. 26-30)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Pauletti teaches to include wherein in a case that the inverter is a two-stage inverter, the inverter further comprises: at least one Boost circuit, wherein input terminals of the Boost circuit serve as a pair of direct current terminals of the inverter, and a positive output terminal and a negative output terminal of the Boost circuit are connected to two terminals of the bus capacitor respectively; and the controller is connected to control terminals of switch transistors in the Boost circuit through the driving circuit, as taught by Yao in order to improve the safety of the photovoltaic power system.
Allowable Subject Matter
Claim 3-7 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Indicating Allowable Subject Matter
The following is an examiner’s statement of reasons for indicating Allowable Subject Matter:
Claim 3; prior art of record fails to disclose either by itself or in combination: “…wherein the inverter is a two-stage inverter comprising a Boost circuit and an inverter circuit, and the applying the electrical signal disturbance to the direct current bus connected to the shutdown device in the rapid shutdown system at least once within the pre-shutdown period of the shutdown device comprises: sampling a voltage across a direct current bus of the inverter and determining whether the sampled voltage is greater than a preset voltage by the inverter; operating the Boost circuit in a shoot through mode under control of the inverter and applying the electrical signal disturbance to the direct current bus connected to the shutdown device in the rapid shutdown system at least once within the pre-shutdown period by the inverter circuit under control of the inverter, in response to a determination result that the voltage is greater than the preset voltage; and applying the electrical signal disturbance to the direct current bus connected to the shutdown device in the rapid shutdown system at least once within the pre-shutdown period by the Boost circuit under control of the inverter, in response to a determination result that the voltage is not greater than the preset voltage”.
Claim 5; prior art of record fails to disclose either by itself or in combination: “…wherein the applying the electrical signal disturbance to the direct current bus connected to the shutdown device in the rapid shutdown system at least once within the pre-shutdown period by the inverter circuit under control of the inverter comprises: feeding a current to a grid at least once within the pre-shutdown period by the inverter circuit, to charge or discharge a bus capacitor in the inverter, as so to apply the electrical signal disturbance to the direct current bus connected to the shutdown device in the rapid shutdown system.
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record.
Conclusion
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838