DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/09/2026 has been entered.
Response to Amendments
Applicant's response of 07/09/2026 has been acknowledged. Claims 1-2, 4-5, 7-8, 10-13, 15-16, 20, and 23 have been amended. No new matter has been added. Claims 3, 6, and 19 were previously cancelled
This office action considers claims 1-2, 4-5, 7-18 and 20-23 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant’s arguments filed 07/09/2026 have been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1, 2, 4-5, 7, 22, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Song et al. (US 20210202633 A1 – hereinafter Song) in view of Choi et al. (US 20220208924 A1 – hereinafter Choi) and Yuan et al. (US 20210225955 A1 – hereinafter Yuan).
Regarding independent claim 1, Song teaches:
(Currently amended) A display substrate (100 – [0091] – “the display
panel 10 according to the embodiment may include a substrate 100”), comprising a display region (DA – Fig. 1A – [0075] – “display area DA”), wherein the
display region (DA) comprises a drive structure layer (Fig. 6H – {[0144] – “the conductive layers shown in FIG. 6D or before forming the conductive layers shown in FIG. 6G”}, {[0148] – “As shown in FIG. 6H, data lines 161 and a power voltage line 163 may be on the first insulating layer 116”} – this is interpreted as Fig. 6H shows the drive layer structure, hereinafter ‘DSL’) disposed on a base substrate (100), the drive structure layer (DSL) at least comprises a plurality of circuit units ([0093] – “pixel circuit of the first pixel PXL in the first pixel area SPA1 and a pixel circuit of the second pixel PXR”) constituting a plurality of unit rows ([0185] – “In each of rows 1R, 2R, 3R . . . , the first emission area EA1 of the first color pixel PX1” – Fig. 10 shows this) and a plurality of unit columns ([0186] – “odd-numbered column 1M, 3M . . . , the first emission area EA1 of the first color pixel PX1 and the third emission area EA3 of the third color pixel PX3 may be alternately arranged in the second direction D2” – Fig. 10 shows this), a plurality of data signal lines (161 – [0148] – “data lines 161 and the power voltage line 163 extend in the second direction D2” – Fig. 6H shows this) extending along a second direction (D2 – [0148] – “the second direction D2”), a plurality of first connection lines (151 – Fig. 6G – [0136] – “first scan connecting line 151 may extend in the first direction D1”) extending along a first direction (D1 – Fig. 6G – [0136] – “the first direction D1”), and a plurality of second connection lines extending along the second direction, the first direction intersects with the second direction; a circuit unit comprises a pixel drive circuit, at least one data signal line is connected with a plurality of pixel drive circuits of a unit column, first ends of the plurality of first connection lines are correspondingly connected with the plurality of data signal lines, and second ends of the plurality of first connection lines are correspondingly connected with the plurality of second connection lines; pixel drive circuits in adjacent unit columns are mirror symmetrical with respect to a center line, the center line is a straight line located between adjacent unit columns and extending along the second direction, and a second connection line is disposed at a gap between the pixel drive circuits of the adjacent unit columns,
wherein a part of the plurality of data signal lines are connected with lead-out lines in a bonding region located on a side of the display region through data connection lines, while another part of the plurality of data signal lines are directly connected with lead-out lines in the bonding region, wherein the data connection lines comprise the plurality of first connection lines and the plurality of second connection lines; and
the drive structure layer (DSL) further comprises a plurality of first power supply line (163 – Fig. 6H – [0148] – “a power voltage line 163), the second connection line (161E – Fig. 6H – [0149] – “first data line 161E”) is disposed between two adjacent first power supply lines (163), and a data signal line (161O – Fig. 6H – [0149] – “second data line 161O”) and the second connection line (161E) are respectively disposed at two sides of a first power supply line (163).
Song does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Choi teaches
a plurality of second connection lines (VCL – fig. 7 – [0092] – “plurality of vertical connection lines VCL”) extending along the second direction (Y – Fig. 7 – [0076] – “direction (e.g., the +y direction)”), the first direction (X) intersects with the second direction (Y); a circuit unit comprises a pixel drive circuit (PC – Fig. 7 – [0075] – “pixel circuit PC driving the organic light-emitting diode OLED”), at least one data signal line (DL) is connected with a plurality of pixel drive circuits (PC – Fig. 6 shows this) of a unit column (Fig. 5 annotated, see below – [0056} – “plurality of pixels PX that are two-dimensionally arranged in rows and columns” – hereinafter ‘N’), first ends (Fig. 5 annotated, see below – hereinafter ‘FE’) of the plurality of first connection lines (HCL – Fig. 7 – [0092] – “a plurality of horizontal connection lines HCL”) are correspondingly connected ([0096] – “the plurality of connection lines CL may be electrically connected to a second data line DL2 at a second node N2”) with the plurality of data signal lines (DL2), and second ends (Fig. 5 annotated, see below – hereinafter ‘SE’) of the plurality of first connection lines (HCL) are correspondingly connected ([0093] – “vertical connection line VCL and the horizontal connection line HCL may be electrically connected to each other through a contact hole”) with the plurality of second connection lines (VCL – Fig. 5 shows this); pixel drive circuits (PC) in adjacent unit columns (N) are mirror symmetrical ([0131] – “the first pixel circuit PC1 and the second pixel circuit PC2 may have a structure symmetrical”) with respect to a center line (CTL – Fig. 3 – [0082] – “symmetrical with respect to a virtual center line CTL passing through the center of the display panel”), the center line (CTL) is a straight line located between adjacent unit columns (N) and extending along the second direction (Y – Fig. 3 shows this),
wherein a part of the plurality of data signal lines (DL) are connected with lead-out lines (IL – Fig. 3 – [0078] – “a plurality of input lines IL transmitting data signals to be applied to the display area DA may be located in the peripheral area PA. The plurality of input lines IL may be electrically connected to the pad portion PAD, and may transmit a data signal received from the pad portion PAD to the data line DL”) in a bonding region (Fig. 3 annotated, see below – this corresponds to a bonding region, hereinafter ‘BR’) located on a side of the display region (DA – Fig. 3 – [0056] – “display area DA”) through data connection lines (HCL and VCL), while another part of the plurality of data signal lines (DL) are directly connected with lead-out lines (IL – Fig. 3 – [0078] – “plurality of input lines IL may be electrically connected to the pad portion PAD, and may transmit a data signal received from the pad portion PAD to the data line DL”) in the bonding region (BR), wherein the data connection lines (HCL and VCL) comprise the plurality of first connection lines (HCL) and the plurality of second connection lines (VCL).
PNG
media_image1.png
807
813
media_image1.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate pixel circuit structure as taught by Choi into Song.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result of [0005] – “a display device having a reduced dead space and having excellent characteristics such as low power consumption and excellent display quality.”
Song and Choi do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Yuan teaches
and a second connection line (112 – Fig. 4A – [0050] – “second detection line 112 extending along the second direction D2”) is disposed at a gap (Fig. 3B annotated, see below – this is a gap) between the pixel drive circuits (yuan (130 – Fig. 3B – [0064] – “plurality of pixel units 130”) of the adjacent unit columns (Fig. 3B annotated, see below – [0040] – “an array structure of a plurality of rows and a plurality of columns along a first direction D1 and a second direction D2” – hereinafter ‘M’).
PNG
media_image2.png
437
848
media_image2.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second connection line structure as taught by Yuan into Song and Choi.
An ordinary artisan would have been motivated to use the known technique of Yuan in the manner set forth above to produce the predictable result of [0003] – “organic light-emitting diode (OLED) display panels have the characteristics of self-luminous, high contrast, low power consumption, wide viewing angle, fast response speed, being suitable for flexible panels, wide temperature application range, simple manufacturing, etc., and have a broad development prospect.”
Regarding claim 2, Song as modified by Choi and Yuan, teaches claim 1 from which claim 2 depends. Song and Choi do not expressly disclose the limitations of claim 2.
However, in an analogous art, Yuan teaches
(Currently amended) The display substrate according to claim 1, wherein
two data signal lines (140 – Fig. 4A – [0050] – “A plurality of data lines 140 extend along a second direction (e.g., a column direction of the array) D2”) in at least one of the adjacent unit column (M) are mirror symmetrical with respect to the second connection line (112), and a minimum distance (Fig. 4A annotated, see below – hereinafter ‘L1’) between the second connection line (112) and an adjacent data signal line (140) in the first direction (D1 – Fig. 4A – [0050] – “plurality of first power supply lines 113 extend along the first direction D1” is greater than a minimum distance (Fig. 4A annotated, see below – hereinafter ‘L3’) between the two data signal lines (140) in the at least one of the adjacent unit columns (M) in the first direction (D1 – Fig. 4A annotated, see below, shows this);
or,
two data signal lines (140) in at least one of the adjacent unit column (M) are mirror symmetrical with respect to the second connection line (112), and a minimum distance (L1) between the second connection line (112) and an adjacent data signal line (140) in the first direction is 1/2 of a minimum distance between the two data signal lines (140) in the at least one of the adjacent unit columns (M) in the first direction (D1).
PNG
media_image3.png
719
640
media_image3.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the symmetrical spacing structure as taught by Yuan into Song and Choi.
An ordinary artisan would have been motivated to use the known technique of Yuan in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 4, Song as modified by Choi, and Yuan, teaches claim 1 from which claim 4 depends. Song and Choi do not expressly disclose the limitations of claim 4.
However, in an analogous art, Yuan teaches
(Currently amended) The display substrate according to claim 1, wherein
the drive structure layer ([0073] – “FIG. 4A is a schematic diagram illustrating an array substrate provided by an embodiment of the present disclosure. For clarity, only a part of the subpixel array (3 rows and 6 columns of subpixels 100) in the array substrate is illustrated in the FIG. 4” – this is interpreted as drive structure layer) further comprises a plurality of power supply traces (114 – Fig. 4B – [0071] – “power supply line 114”) extending along the second direction (D2 – Fig. 4B – [0071] – “power supply line 114 extends along the second direction D2”), and a power supply trace (114) is disposed at a gap between the pixel drive circuits of the adjacent unit columns (114 – Fig. 4B – [0071] – “power supply line 114 is provided between the adjacent pixel unit column groups 210, the second power supply line 114 extends along the second direction D2”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the symmetrical spacing structure as taught by Yuan into Song and Choi.
An ordinary artisan would have been motivated to use the known technique of Yuan in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 5, Song as modified by Choi, and Yuan, teaches claim 4 from which claim 5 depends. Song does not expressly disclose the limitations of claim 5.
However, in an analogous art, Choi teaches
(Currently amended) The display substrate according to claim 4, wherein
two data signal lines (DL) in at least one of the adjacent unit column (N) are mirror symmetrical with respect to the power supply trace (PL – Fig. 14 – [0076] – “data lines DL and the driving voltage lines PL may extend in a first direction (e.g., +y direction)”), and a minimum distance between the power supply trace and an adjacent data signal line in the first direction is greater than a minimum distance between the two data signal lines in the at least one of the adjacent unit columns in the first direction;
or,
two data signal lines in at least one of the adjacent unit column are mirror symmetrical with respect to the power supply trace, and a minimum distance between the power supply trace and an adjacent data signal line in the first direction is 1/2 of a minimum distance between the two data signal lines in the at least one of the adjacent unit columns in the first direction.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate data signal line structure as taught by Choi into Song.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result as stated above in claim 1.
Song and Choi do not expressly disclose the other limitations of claim 5.
However, in an analogous art, Yuan teaches
a minimum distance (Fig. 2 annotated, see below – hereinafter ‘L1’) between the power supply trace (114 – Fig. 2 – [0050] – “plurality of second power supply lines 114”) and an adjacent data signal line (140 – Fig. 2 – [0050] – “plurality of data lines 140”) in the first direction (D1 – Fig. 2 – [0050] – “first direction (e.g., a row direction of the array) D1”) is greater than a minimum distance (Fig. 2 annotated, see below – hereinafter ‘L2’) between the two data signal lines (140) in the at least one of the adjacent unit columns (M) in the first direction (D1);
or,
two data signal lines (140) in at least one of the adjacent unit column (M) are mirror symmetrical with respect to the power supply trace (114), and a minimum distance (L1) between the power supply trace (114) and an adjacent data signal line (140) in the first direction (D1) is 1/2 of a minimum distance between the two data signal lines (140) in the at least one of the adjacent unit columns (M) in the first direction (D1 – Fig. 2 annotated, see below show this as the figure has been extended in the D1 direction by the examiner to better illustrate this).
PNG
media_image4.png
490
604
media_image4.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate data signal line structure as taught by Yuan into Song and Choi.
An ordinary artisan would have been motivated to use the known technique of Yuan in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 7, Song as modified by Choi and Yuan, teaches claim 1 from which claim 7 depends. Song and Yuan do not expressly disclose the limitations of claim 7.
However, in an analogous art, Choi teaches
(Currently amended) The display substrate according to claim 1, wherein
in a plane perpendicular to the display substrate (100 – Fig. 15 – [0074] – “substrate 100”), the drive structure layer (Fig. 15 annotated, see below – hereinafter ‘DSL’) comprises a plurality of conductive layers sequentially disposed on the base substrate (100), the plurality of first connection lines (HCL) and the plurality of second connection lines (VCL) are disposed in different conductive layers (Fig. 15 shows this), and the plurality of data signal lines (DL) and the plurality of second connection lines (VCL) are disposed in a same conductive layer (Fig. 15 shows this).
PNG
media_image5.png
625
978
media_image5.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate drive layer structure as taught by Choi into Song and Yuan.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result of as stated above in claim 1.
Regarding claim 22, Song as modified by Choi and Yuan, teaches claim 1 from which claim 22 depends. Song further teaches
(Previously presented) A display apparatus (10 – [0091] – “the display
panel 10”), comprising a display substrate (100 – [0091] – “the display panel 10 according to the embodiment may include a substrate 100”) according to claim 1.
Regarding independent claim 23, Song teaches:
(Currently amended) A preparation method of a display substrate
(100 – [0091] – “the display panel 10 according to the embodiment may include a substrate 100”), wherein the display substrate (100) comprises a display region (DA – Fig. 1A – [0075] – “display area DA”) and the preparation method comprises:
forming a drive structure layer (Fig. 6H – {[0144] – “the conductive layers shown in FIG. 6D or before forming the conductive layers shown in FIG. 6G”}, {[0148] – “As shown in FIG. 6H, data lines 161 and a power voltage line 163 may be on the first insulating layer 116”} – this is interpreted as Fig. 6H shows the drive layer structure, hereinafter ‘DSL’) on a base substrate (100) of the display region (DA), wherein the drive structure layer (DSL) at least comprises a plurality of circuit units ([0093] – “pixel circuit of the first pixel PXL in the first pixel area SPA1 and a pixel circuit of the second pixel PXR”) constituting a plurality of unit rows ([0185] – “In each of rows 1R, 2R, 3R . . . , the first emission area EA1 of the first color pixel PX1” – Fig. 10 shows this) and a plurality of unit columns ([0186] – “odd-numbered column 1M, 3M . . . , the first emission area EA1 of the first color pixel PX1 and the third emission area EA3 of the third color pixel PX3 may be alternately arranged in the second direction D2” – Fig. 10 shows this), a plurality of data signal lines (161 – [0148] – “data lines 161 and the power voltage line 163 extend in the second direction D2” – Fig. 6H shows this) extending along a second direction (D2 – [0148] – “the second direction D2”), a plurality of first connection lines (151 – Fig. 6G – [0136] – “first scan connecting line 151 may extend in the first direction D1”) extending along a first direction (D1 – Fig. 6G – [0136] – “the first direction D1”), and a plurality of second connection lines extending along the second direction, the first direction intersects with the second direction; a circuit unit comprises a pixel drive circuit, at least one data signal line is connected with a plurality of pixel drive circuits of a unit column, first ends of the plurality of first connection lines are correspondingly connected with the plurality of data signal lines, and second ends of the plurality of first connection lines are correspondingly connected with the plurality of second connection lines; pixel drive circuits in adjacent unit columns are mirror symmetrical with respect to a center line, the center line is a straight line located between adjacent unit columns and extending along the second direction, and a second connection line is disposed at a gap between the pixel drive circuits of the adjacent unit columns,
wherein a part of the plurality of data signal lines are connected with lead-out lines in a bonding region located on a side of the display region through data connection lines, while another part of the plurality of data signal lines are directly connected with lead-out lines in the bonding region, wherein the data connection lines comprise the plurality of first connection lines and the plurality of second connection lines,
the drive structure layer (116 – Fig. 6H – [0148] – “As shown in FIG. 6H, data lines 161 and a power voltage line 163 may be on the first insulating layer 116”) further comprises a plurality of first power supply line (163 – Fig. 6H – [0148] – “a power voltage line 163), the second connection line (161E – Fig. 6H – [0149] – “first data line 161E”) is disposed between two adjacent first power supply lines, and a data signal line (161O – Fig. 6H – [0149] – “second data line 161O”) and the second connection line (161E) are respectively disposed at two sides of a first power supply line (163).
Song does not expressly disclose the other limitations of claim 23.
However, in an analogous art, Choi teaches
a plurality of second connection lines (VCL – fig. 7 – [0092] – “plurality of vertical connection lines VCL”) extending along the second direction (Y – Fig. 7 – [0076] – “direction (e.g., the +y direction)”), the first direction (X) intersects with the second direction (Y); a circuit unit comprises a pixel drive circuit (PC – Fig. 7 – [0075] – “pixel circuit PC driving the organic light-emitting diode OLED”), at least one data signal line (DL) is connected with a plurality of pixel drive circuits (PC – Fig. 6 shows this) of a unit column (Fig. 5 annotated, see below – [0056} – “plurality of pixels PX that are two-dimensionally arranged in rows and columns” – hereinafter ‘N’), first ends (Fig. 5 annotated, see below – hereinafter ‘FE’) of the plurality of first connection lines (HCL – Fig. 7 – [0092] – “a plurality of horizontal connection lines HCL”) are correspondingly connected ([0096] – “the plurality of connection lines CL may be electrically connected to a second data line DL2 at a second node N2”) with the plurality of data signal lines (DL2), and second ends (Fig. 5 annotated, see below – hereinafter ‘SE’) of the plurality of first connection lines (HCL) are correspondingly connected ([0093] – “vertical connection line VCL and the horizontal connection line HCL may be electrically connected to each other through a contact hole”) with the plurality of second connection lines (VCL – Fig. 5 shows this); pixel drive circuits (PC) in adjacent unit columns (N) are mirror symmetrical ([0131] – “the first pixel circuit PC1 and the second pixel circuit PC2 may have a structure symmetrical”) with respect to a center line (CTL – Fig. 3 – [0082] – “symmetrical with respect to a virtual center line CTL passing through the center of the display panel”), the center line (CTL) is a straight line located between adjacent unit columns (N) and extending along the second direction (Y – Fig. 3 shows this),
wherein a part of the plurality of data signal lines (DL) are connected with lead-out lines (IL – Fig. 3 – [0078] – “a plurality of input lines IL transmitting data signals to be applied to the display area DA may be located in the peripheral area PA. The plurality of input lines IL may be electrically connected to the pad portion PAD, and may transmit a data signal received from the pad portion PAD to the data line DL”) in a bonding region (Fig. 3 annotated, see below – this corresponds to a bonding region, hereinafter ‘BR’) located on a side of the display region (DA – Fig. 3 – [0056] – “display area DA”) through data connection lines (HCL and VCL), while another part of the plurality of data signal lines (DL) are directly connected with lead-out lines (IL – Fig. 3 – [0078] – “plurality of input lines IL may be electrically connected to the pad portion PAD, and may transmit a data signal received from the pad portion PAD to the data line DL”) in the bonding region (BR), wherein the data connection lines (HCL and VCL) comprise the plurality of first connection lines (HCL) and the plurality of second connection lines (VCL).
PNG
media_image1.png
807
813
media_image1.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate pixel circuit structure as taught by Choi into Song.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result as stated above in claim 1.
Song and Choi do not expressly disclose the other limitations of claim 23.
However, in an analogous art, Yuan teaches
a second connection line (112 – Fig. 4A – [0050] – “second detection line 112 extending along the second direction D2”) is disposed at a gap (Fig. 3B annotated, see below – this is a gap) between the pixel drive circuits (130 – Fig. 3B – [0064] – “plurality of pixel units 130”) of the adjacent unit columns (Fig. 3B annotated, see below – [0040] – “an array structure of a plurality of rows and a plurality of columns along a first direction D1 and a second direction D2” – hereinafter ‘M’).
PNG
media_image2.png
437
848
media_image2.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second connection line structure as taught by Yuan into Song and Choi.
An ordinary artisan would have been motivated to use the known technique of Yuan in the manner set forth above to produce the predictable result as stated above in claim 1.
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Choi, Yuan, and Cho et al. (US 20230397462 A1 – hereinafter Cho).
Regarding claim 13, Song as modified by Choi and Yuan, teaches claim 1 from which claim 13 depends.
Song, Yuan, and Choi do not expressly disclose the limitations of claim 13.
However, in an analogous art, Cho teaches
(Currently amended) The display substrate according to claim 1, wherein the pixel drive circuit (PDU – Fig. 6 – [0150] – “pixel driver PDU”) at least comprises a fourth transistor (ST2 – Fig. 6 – [0150] – “first to seventh transistors ST1, ST2, ST3, ST4, ST5, ST6, and ST7”), a first electrode of the fourth transistor (ST2) is connected with the data signal line (DL – Fig. 6 – [0149] – “data line DL”) through a data connection electrode (DCH1 – Fig. 7 – [0173] – “first data connection hole DCH1”), and in at least one circuit unit (PDU), the a first connection line (DCL1 – Fig. 7 – [0171] – “first data connection line DCL1”) is connected with the data connection electrode (DCH1 – Fiig. 7 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the pixel drive circuit structure as taught by Cho into Song, Yuan, and Choi.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result of [0006] – “a display device capable of removing a spot on a display surface caused by fan-out lines due to a reduction in the size of a non-display area.”
Regarding claim 14, Song as modified by Choi, Yuan, and Cho, teaches claim 13 from which claim 14 depends. Song, Yuan, and Choi do not expressly disclose the limitations of claim 14.
However, in an analogous art, Cho teaches
(Original) The display substrate according to claim 13, wherein the at least
one circuit unit (PDU) further comprises a data connection block (Fig. 12 annotated, see below – hereinafter ‘DCB’), a first end of the data connection block (DCB) is connected with the first connection line (DCL1), and a second end of the data connection block (DCB) is connected with the data connection electrode (DCH1 – Fig. 12 annotated shows this).
PNG
media_image6.png
804
854
media_image6.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the data connection structure as taught by Cho into Song, Yuan, and Choi.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 13.
Regarding claim 15, Song as modified by Choi, Yuan, and Cho, teaches claim 14 from which claim 15 depends. Song, Yuan, and Choi do not expressly disclose the limitations of claim 15.
However, in an analogous art, Cho teaches
(Original) The display substrate according to claim 14, wherein in at least
one circuit unit (PDU), the first connection line (DCL1), the data connection electrode (DCH1), and the data connection block (DCB) are disposed in a same layer and are of an interconnected integral structure (DCH1 – Fig. 12 annotated, see above, shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the data connection structure as taught by Cho into Song, Yuan, and Choi.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 13.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Choi, Yuan, and Yoon et al. (US 20230240103 A1 – hereinafter Yoon).
Regarding claim 8, Song as modified by Choi and Yuan, teaches claim 7 from which claim 8 depends. Song and Yuan do not expressly disclose the other limitations of claim 8.
However, in an analogous art, Choi teaches
(Currently amended) The display substrate according to claim 7, wherein
the plurality of conductive layers at least comprise a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer that are sequentially disposed along a direction away from the base substrate, the plurality of first connection lines (HCL) are disposed in the second source-drain metal layer (Fig. 15 annotated, see below – hereinafter ‘SD2’), the plurality of data signal lines (DL) and plurality of the second connection lines (VCL) are disposed in the third source-drain metal layer (Fig. 15 annotated, see below – hereinafter ‘SD3’), the data signal line (DL) is connected with a first end of a first connection line (HCL) through a via (N2 – Fig. 5 – [0096] – “the plurality of connection lines CL may be electrically connected to a second data line DL2 at a second node N2” – Fig. 5 shows this) and the second connection line (VCL) is connected with a second end of the first connection line (HCL) through a via ([0093] – “the vertical connection line VCL and the horizontal connection line HCL may be arranged on different layers. The vertical connection line VCL and the horizontal connection line HCL may be electrically connected to each other through a contact hole”).
PNG
media_image5.png
625
978
media_image5.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the connection line structure as taught by Choi into Song and Yuan.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result as stated above in claim 1.
Song, Yuan, and Choi do not expressly disclose the other limitations of claim 8.
However, in an analogous art, Yoon teaches
(Currently amended) The display substrate according to claim 7, wherein
the plurality of conductive layers at least comprise a first source-drain metal layer ([0042] – “a first source/drain layer disposed on an interlayer insulating layer covering the second gate layer”), a second source-drain metal layer ([0042] – “a second source/drain layer disposed on a first planarization layer covering the first source/drain layer”), and a third source-drain metal layer ([0042] – “a third source/drain layer disposed on a second planarization layer covering the second source/drain layer”) that are sequentially disposed along a direction away from the base substrate (SUB – Fig. 15 – [0086] – “substrate SUB”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second and third conductive layer structure as taught by Yoon into Song, Yuan, and Choi.
An ordinary artisan would have been motivated to use the known technique of Yoon in the manner set forth above to produce the predictable result of [0007] – “a display panel with a minimum width of a non-display area and satisfactory resolution.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Choi, Yuan, Yoon, Cho, and Kim (US RE50581 E – hereinafter Kim).
Regarding claim 9, Song as modified by Choi, Yuan, and Yoon, teaches claim 8 from which claim 9 depends. Song, Yuan, Yoon, and Choi do not expressly disclose the limitations of claim 9.
However, in an analogous art, Cho teaches
(Original) The display substrate according to claim 8, wherein the pixel
drive circuit (200 – Fig. 6 – [0102] – “display driving circuit 200”) at least comprises a first transistor (ST4 – Fig. 6 – [0156] – “transistor ST4”), a second transistor (ST3 – Fig. 6 – [0156] – “transistor ST3”), and a storage capacitor (C1 – Fig. 6 – [0156] – “capacitor C1”), the first transistor (ST4) at least comprises a first active layer ([0157] – “an active layer of each of the third transistor ST3 and the fourth transistor ST4 configured as the N-type or kind MOSFETs may be formed of an oxide semiconductor” – hereinafter ‘AT4’), the second transistor (ST3) at least comprises a second active layer ([0157] – “an active layer of each of the third transistor ST3 and the fourth transistor ST4 configured as the N-type or kind MOSFETs may be formed of an oxide semiconductor” – hereinafter ‘AT3’),
the second source-drain metal layer ([0240] – “The second source/drain layer may include the plurality of first data connection lines DCL1, the plurality of data lines DL, the first vertical line VDD_V”) further comprises a shielding electrode ({[0311] – “the parasitic capacitance may be reduced through a shielding structure between the first data connection line DCL1 and the first connection electrode BE1 by changing the structure of the first connection electrode BE1”}, {[0198] – “first electrode S1 of the first transistor ST1 may be electrically coupled (e.g., connected) to the first electrode DTS of the driving transistor DT through a first connection electrode BE1 of the first source/drain layer, and the second electrode D1 of the first transistor ST1 may be electrically coupled (e.g., connected) to the bias voltage line VOB through a second connection electrode BE2 of the first source/drain layer”} – hereinafter ‘SE’), an orthographic projection of the shielding electrode (SE) on the base substrate (SUB – [0189] – “substrate SUB may be a base substrate or a base member”) is at least partially overlapped with an orthographic projection of the second region of the first active layer (AT4) and the first region of the second active layer (A5) on the base substrate (SUB), and the orthographic projection of the shielding electrode (SE) on the base substrate (SUB) is at least partially overlapped with an orthographic projection of the first connection electrode (BE1) on the base substrate (SUB).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the drive circuit and shielding structure as taught by Cho into Song, Yuan, and Choi.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 13.
Song, Yuan, Yoon, Choi, and Cho do not expressly disclose the other limitations of claim 9.
However, in an analogous art, Kim teaches
a second region ([18:8-18] – “a first transistor comprising a first gate electrode and a first active layer curved below the first gate electrode; a second transistor electrically connected to the first scanning line and comprising a second active layer, wherein the second active layer is integrally coupled to a first portion of the first active layer as a single body; and a capacitor electrically connected to the first transistor”) of the first active layer (A4 – Fig. 5 – [9:40-44] – “Active layers A1, A2, A3, A4, A5, and A6, which are respectively of a driving TFT T1, a switching TFT T2, a compensation TFT T3, an initialization TFT T4, a first emission control TFT T5, and a second emission control TFT T6” – this corresponds to the first active layer) and a first region of the second active layer (A5 – Fig. 5 – this corresponds to the second active layer) are of an interconnected integral structure, and are connected with a first electrode plate (CE1 – [7:22-23] – “the first electrode CE1 of the storage capacitor Cst1”) of the storage capacitor (Cst1 – [7:22-23] – “the first electrode CE1 of the storage capacitor Cst1”) through a first connection electrode ([7:22-24] – “drain electrode D4 of the initialization TFT T4 is coupled to the first electrode CE1 of the storage capacitor Cst1” – these are connected through wires acting as connection electrodes, {[10:48-49] – “second gate wiring GL2 may include two second capacitor electrodes 116-1 and 116-2” – Fig. 8 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate active layer structure as taught by Kim into Song, Yuan, Yoon, Choi, and Cho.
An ordinary artisan would have been motivated to use the known technique of Kim in the manner set forth above to produce the predictable result of [2:8-11] – “capacitor devices with increased capacitance, an organic light emitting display apparatus including the capacitor devices, and a method for manufacturing the organic light emitting display apparatus.”
Regarding claim 10, Song as modified by Choi, Yuan, Yoon, Cho, and Kim, teaches claim 9 from which claim 10 depends. Song, Yuan, Yoon, Kim, and Choi do not expressly disclose the limitations of claim 10.
However, in an analogous art, Cho teaches
(Currently amended) The display substrate according to claim 9, wherein
the third source-drain metal layer (Fig. 11 annotated, see below, shows this, this is interpreted as conductive layer equating to applicant’s [0262] – “the sixth conductive layer may be referred to as a third source-drain metal (SD3) layer” – hereinafter ‘SD3’) further comprises the plurality of first power supply lines (VOB – [0198] – “first electrode S1 of the first transistor ST1 may be electrically coupled (e.g., connected) to the first electrode DTS of the driving transistor DT through a first connection electrode BE1 of the first source/drain layer, and the second electrode D1 of the first transistor ST1 may be electrically coupled (e.g., connected) to the bias voltage line VOB through a second connection electrode BE2 of the first source/drain layer”), and the first power supply line (VOB) is connected with the shielding electrode (SE) through a via (CNT1 – [0233] – “the second connection electrode BE2 may be coupled (e.g., connected) to the bias voltage line VOB through the first contact hole CNT1 penetrating the second interlayer insulating layer IL2”).
PNG
media_image7.png
761
1088
media_image7.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the power supply and shielding structure as taught by Cho into Song, Yuan, Yoon, Kim, and Choi.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 13.
Regarding claim 11, Song as modified by Choi, Yuan, Yoon, Cho, and Kim, teaches claim 10 from which claim 11 depends. Song, Choi, Yuan, Yoon, and Kim do not expressly disclose the limitations of claim 11.
However, in an analogous art, Cho teaches
(Currently amended) The display substrate according to claim 10, wherein
in the plane perpendicular to the display substrate (SUB), the display substrate (SUB) further comprises a light emitting structure layer (Fig. 11 annotated, see below – hereinafter ‘ESL’) disposed on a side of the drive structure layer away (Fig. 11 annotated, see below – hereinafter ‘DSL’) from the base substrate (SUB), the light emitting structure layer (ESL) comprises a plurality of light emitting units (ED – Fig. 11 – [0251] – “light emitting elements ED disposed in the plurality of sub-pixels SPX”), a light emitting unit (ED) at least comprises an anode (171 – Fig. 11 – [0252] – “pixel electrode 171 of the light emitting element ED”); in at least one light emitting unit (ED), an orthographic projection of the anode (171) on the base substrate (SUB) is at least partially overlapped with an orthographic projection of the first power supply line (VOB) on the base substrate (SUB), and the orthographic projection of the anode on the base substrate (SUB) is at least partially overlapped with the orthographic projection of the shielding electrode (SE) on the base substrate (SUB – Fig. 11 shows ED overlapping BE1 which is part of SE that is coupled to VOB).
PNG
media_image7.png
761
1088
media_image7.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the layer structure as taught by Cho into Song, Choi, Yuan, Yoon, and Kim.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 13.
Regarding claim 12, Song as modified by Choi, Yuan, Yoon, Cho, and Kim, teaches claim 11 from which claim 12 depends. Song, Choi, Yuan, Yoon, and Kim do not expressly disclose the limitations of claim 12.
However, in an analogous art, Cho teaches
(Currently amended) The display substrate according to claim 11, wherein
in the at least one light emitting unit (ED), the orthographic projection of the anode (171) on the base substrate (SUB) and the orthographic projection of the first power supply line (VOB) on the base substrate (SUB) have a first overlapping region (Fig. 10 annotated, see below, shows this, hereinafter ‘FOR’), and the orthographic projection of the anode (171) on the base substrate (SUB) and the orthographic projection of the shielding electrode (SE) on the base substrate (SUB) have a second overlapping region (Fig. 10 annotated, see below, shows this, hereinafter ‘SOR’), an area of the first overlapping region (FOR) is less than an area of the second overlapping region (FOR – this is obvious as the anode is smaller than the power line as the anode applies to a pixel and the powerline connect multiple pixels).
PNG
media_image8.png
812
855
media_image8.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the overlapping structure as taught by Cho into Song, Choi, Yuan, Yoon, and Kim.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 13.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Choi, Yuan, Cho, and Yoon.
Regarding claim 16, Song as modified by Choi, and Yuan, teaches claim 1 from which claim 16 depends. Song, Choi, and Yuan do not expressly disclose the limitations of claim 16.
However, in an analogous art, Cho teaches
(Currently amended) The display substrate according to claim 1, herein at least one circuit unit (PDU) further comprises a second initial signal line (VAIL – Fig. 13 – [0226] – “second initialization voltage line VAIL may extend in the first direction DR1”) extending along the first direction (DR1 – Fig. 13 – [0226] – “first direction DR1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second signal line structure as taught by Cho into Song, Choi, and Yuan.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 13.
Song, Choi, Yuan, and Cho do not expressly disclose the other limitations of claim 16.
However, in an analogous art, Yoon teaches
a second initial connection line (VVAIL – [0338] – “initialization vertical line VVAIL extending in the second direction DR2”) extending along the second direction (DR2 – [0338] – “initialization vertical line VVAIL extending in the second direction DR2”), the second initial connection line (VVAIL) is disposed between two second initial signal lines (VVGIL – [0335] – “gate initialization vertical line VVGIL extending in the second direction DR2”) adjacent in the second direction and is respectively connected with the two second initial signal lines to form a second initial signal lines with of a network communication structure in the display region (Fig. 7 shows a mesh communication structure that carries signals to each pixel).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the network structure as taught by Yoon into Song, Choi, Yuan, and Cho.
An ordinary artisan would have been motivated to use the known technique of Yoon in the manner set forth above to produce the predictable result as stated above in claim 8.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Choi, Yuan, Cho, Yoon, Ma et al. (US 20240395829 A1 – hereinafter Ma), and Wang et al. (US 20210225984 A1 – hereinafter Wang).
Regarding claim 17, Song as modified by Choi, Yuan, Cho, and Yoon, teaches claim 16 from which claim 17 depends. Song, Choi, Yuan, Cho, and Yoon do not expressly disclose the limitations of claim 17.
However, in an analogous art, Ma teaches
(Previously presented) The display substrate according to claim 16,
wherein the second initial connection line (70 – Fig. 20 – [0096] – “connection line 70”) is disposed in an odd-numbered unit column (Fig. 20 annotated, see below – column and row directions are relative), or the second initial connection line (70) is disposed in an even-numbered unit column.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second connection line structure as taught by Ma into Song, Choi, Yuan, Cho, and Yoon.
An ordinary artisan would have been motivated to use the known technique of Ma in the manner set forth above to produce the predictable result of [0003] - a display substrate and a display device.” The connection line structure electrically connects all the pixels with a minimum amount of connection lines thus easing manufacturing and lower costs.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Song, Choi, Yuan, Cho, Yoon, and Ma do not expressly disclose the other limitations of claim 17.
However, in an analogous art, Wang teaches
the second initial signal line (SL – Fig. 11 annotated, see below – [0057] – “plurality of signal lines SL”) and the second initial connection line ([0056] – “plurality of connecting lines CL”) are disposed in a same layer ([0056] – “plurality of connecting lines CL and other signal lines of the stretchable display panel are disposed in a same layer” – Fig. 11 annotated shows this) and are of an interconnected integral structure ([0034] – “FIG. 11 is a schematic diagram illustrating an inter-connected network formed by a plurality of connecting lines”).
PNG
media_image9.png
648
598
media_image9.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second connection line structure as taught by Wang into Song, Choi, Yuan, Cho, Yoon, and Ma.
An ordinary artisan would have been motivated to use the known technique of Wang in the manner set forth above to produce the predictable result of [0001] – “display technology, more particularly, to a stretchable display panel, a stretchable display apparatus, and a method of fabricating a stretchable display panel.” The connection line structure electrically connects all the pixels with a minimum amount of connection lines thus easing manufacturing and lower costs.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Choi, Yuan, Cho, Yoon, Na et al. (US 20220045158 A1 – hereinafter Na)
Regarding claim 18, Song as modified by Choi, Yuan, Cho, and Yoon, teaches claim 16 from which claim 18 depends. Song, Choi, Yuan, Cho, and Yoon do not expressly disclose the limitations of claim 18.
However, in an analogous art, Na teaches
(Original) The display substrate according to claim 16, wherein in two
adjacent unit rows (Fig. 1 annotated, see below), a unit column (Fig. 1 annotated, see below) in which the second initial connection line (128b – Fig. 1 – [0050] – “the second initialization voltage line 128 has a mesh structure including a horizontal portion 128a disposed along a first direction DR1 and a vertical portion 128b disposed along a second direction DR2 crossing the first direction DR1”) is located in one unit row is different from a unit column in which the second initial connection line is located in the other unit row (Fig. 1 annotated, shows this).
PNG
media_image10.png
731
970
media_image10.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second connection line structure as taught by Na into Song, Choi, Yuan, Cho, and Yoon.
An ordinary artisan would have been motivated to use the known technique of Na in the manner set forth above to produce the predictable result of [0008] – “a display device that may evenly transmit a second initialization voltage.”
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Song in view of Choi, Yuan, Cho, Yoon, Tai et al. (US 20230335562 A1 – hereinafter (Tai), and Zhang et al. (US 20210174746 A1 – hereinafter Zhang).
Regarding claim 20, Song as modified by Choi, and Yuan, teaches claim 7 from which claim 20 depends. Song and Yuan do not expressly disclose the other limitations of claim 20.
However, in an analogous art, Choi teaches
the third gate metal layer (1500 – fig. 12 – [0173] – “fifth pattern layer 1500”) at least comprises a second scan signal line (SL2b – Fig. 12 – [0173] – “upper scan line SL2b of the second scan line SL2”) and a third scan signal line (SL2b – Fig. 12 – [0173] – “upper scan line SLpb of the previous scan line SLp”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the third gate metal layer structure as taught by Choi into Song and Yuan.
An ordinary artisan would have been motivated to use the known technique of Choi in the manner set forth above to produce the predictable result as stated above in claim 1.
Song, Yuan, and Choi do not expressly disclose the other limitations of claim 20.
However, in an analogous art, Cho teaches
(Currently amended) The display substrate according to claim 7, wherein the pixel drive circuit the pixel drive circuit (PDU) at least comprises a storage capacitor (C1) and a plurality of transistors ([0150] – “first to seventh transistors ST1, ST2, ST3, ST4, ST5, ST6, and ST7” – this is a plurality), and the plurality of conductive layers ([0186] – “plurality of conductive layers”),
a second semiconductor layer ([0157] – “transistors formed of the polysilicon and the transistors formed of the oxide semiconductor may be disposed on different layers”),
a first source-drain metal layer ([0229] – “first source/drain layer may be disposed on the second interlayer insulating layer IL2”), a second source-drain metal layer ([0240] – “second source/drain layer may be disposed on the first via layer VIA1”), and a third source-drain metal layer (Fig. 11 annotated, see below, shows this, hereinafter ‘SD3’),
comprises a second initial signal lines (VAIL),
the second source-drain metal layer [0240] – “second source/drain layer may be disposed on the first via layer VIA1”) at least comprises a shielding electrode (SE) and the plurality of first connection lines (EML – Fig. 18 – [0210 ] – “emission line EML in the second direction DR2”).
PNG
media_image7.png
761
1088
media_image7.png
Greyscale
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the pixel drive circuit layer structure as taught by Cho into Song, Yuan, and Choi.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 1.
Song, Yuan, Choi, and Cho do not expressly disclose the other limitations of claim 20.
However, in an analogous art, Yoon teaches
the first source-drain metal layer ([0042] – “a first source/drain layer disposed on an interlayer insulating layer covering the second gate layer”) at least comprises a second initial signal line of a network communication structure (Fig. 7 shows a mesh communication structure that carries signals to each pixel).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first metal layer and network structure as taught by Yoon into Song, Yuan, Choi, and Cho.
An ordinary artisan would have been motivated to use the known technique of Yoon in the manner set forth above to produce the predictable result as stated above in claim 8.
Song, Yuan, Choi, Cho, and Yoon do not expressly disclose the other limitations of claim 20.
However, in an analogous art, Tai teaches
comprise a shielding layer (M0 – Fig. 2 – [0036] – “patterned light shielding layer M0”), a first semiconductor layer (SC – Fig. 2 – [0036] – “patterned semiconductor layer SC”), a first gate metal layer (M1 – Fig. 2 – [0036] – “patterned first conductive layer M1”), a second gate metal layer (M2 – Fig. 2 – [0036] – “patterned first conductive layer M2”), a second semiconductor layer, a third gate metal layer (I1 – Fig. 2 – [0036] – “patterned third conductive layer I1”), a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed sequentially along a direction away from the base substrate (SB1 – Fig. 2 – [0036] – “substrate SB1”); the shielding layer (M0) at least comprises a shielding electrode (LS – Fig. 2 – [0044] – “light shielding element LS”), the first semiconductor layer (SC) at least comprises active layers of a plurality of low temperature poly silicon transistors ([0035] – “the semiconductor layer SC is made of a material with high carrier mobility (e.g., low temperature polysilicon (LTPS) material)”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the layer structure as taught by Tai into Zhang, Yuan, Choi, Cho, and Yoon.
An ordinary artisan would have been motivated to use the known technique of Tai in the manner set forth above to produce the predictable result [0005] – “to provide better design of device configuration to ameliorate the defects such as insufficient aperture ratio and short circuit caused by reduction of element size and manufacturing factors in the prior art.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Song, Yuan, Choi, Cho, Yoon, and Tai do not expressly disclose the other limitations of claim 20.
However, in an analogous art, Zhang teaches
the first gate metal layer (320 – Fig. 12B – [0184] – “first conductive layer 320”) at least comprises a first scan signal line (Ga – Fig. 12B – [0184] – “first scanning signal line Ga”), a light emitting signal line (E – Fig. 12B – [0184] – “light emitting control signal line E”), and a first electrode plate (C1 – Fig. 12B – [0184] – “first end C1 of the storage capacitor”) of the storage capacitor (C), the second gate metal layer (330 – Fig. 12C – [0203] – “second conductive layer 330”) at least comprises a second electrode plate (C2 – Fig. 12C – [0203] – “second end C2 of the storage capacitor C”) of the storage capacitor (C), the second semiconductor layer (310 – Fig. 12A – [0177] – “active semiconductor layer 310”) at least comprises active layers of a plurality of oxide transistors ([0179] – “the active semiconductor layer 310 may be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first gate metal layer structure as taught by Zhang into Song, Yuan, Choi, Cho, Yoon, and Tai.
An ordinary artisan would have been motivated to use the known technique of Zhang in the manner set forth above to produce the predictable result of [0003] – “organic light-emitting diode (OLED) display panels have the characteristics of self-luminescence, high contrast, low power consumption, wide viewing angle, rapid response speed, capability of being applied in flexible panels, wide service temperature range, simple production, etc., and have a wide development prospect.”
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 21, Song as modified by Choi, Yuan, Cho, Yoon, Tai, and Zhang, teaches claim 20 from which claim 21 depends. Song, Yuan, Choi, Yoon, Tai, and Zhang do not expressly disclose the limitations of claim 21.
However, in an analogous art, Cho teaches
(Original) The display substrate according to claim 20, wherein the plurality
of transistors comprise a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor ([0150] – “first to seventh transistors ST1, ST2, ST3, ST4, ST5, ST6, and ST7”), the first transistor and the second transistor are oxide transistors ([0157] – “an active layer of each of the third transistor ST3 and the fourth transistor ST4 configured as the N-type or kind MOSFETs may be formed of an oxide semiconductor”), and the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are low temperature poly silicon transistors ([0157] – “active layer of each of the driving transistor DT, the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6 and the seventh transistor ST7 configured as the P-type or kind MOSFETs may be formed of polysilicon”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the transistor structure as taught by Cho into Song, Yuan, Choi, Yoon, Tai, and Zhang.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 1.
Pertinent Art
For the benefits of the Applicant, US RE50581 E are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including specific layer structure elements.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and ttps://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights