Prosecution Insights
Last updated: April 19, 2026
Application No. 18/280,413

CODE BLOCK INTERLEAVING FOR DFT-S-OFDM WAVEFORMS

Non-Final OA §102§103§112
Filed
Sep 05, 2023
Examiner
KRUEGER, KENT K
Art Unit
2474
Tech Center
2400 — Computer Networks
Assignee
Intel Corporation
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
94%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
389 granted / 445 resolved
+29.4% vs TC avg
Moderate +7% lift
Without
With
+6.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
18 currently pending
Career history
463
Total Applications
across all art units

Statute-Specific Performance

§101
3.0%
-37.0% vs TC avg
§103
45.7%
+5.7% vs TC avg
§102
26.0%
-14.0% vs TC avg
§112
13.9%
-26.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 445 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . A preliminary amendment received on 9/05/2023 canceling claims 1-20 and adding claims 21-40 has been entered by the examiner. Information Disclosure Statement The information disclosure statements (IDSs) submitted on 9/05/2023 has been entered and considered by the examiner. 35 USC 112 CLAIM REJECTIONS The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 37-40 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Regarding claim 37, they recite “performing parallel-to-serial conversion of the plurality of code blocks to generate a concatenated code blocks bitstream”. Therefore, it is not clear to the Examiner what exactly this means. The word parallel is only used three times in the specification. In para. 0086 of the published application, it states “the transmit/receive components may be arranged in multiple parallel transmit/receive chains, may be disposed of in the same or different chips/modules, etc.”, which doesn’t seem applicable to the claim language. At para. 0119, it states “The communication device 1100 may include an output controller 1128, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices”; which has nothing to do with the claim language. At para. 0141, it states “performing parallel-to-serial conversion of the plurality of code blocks to generate a concatenated code block bitstream”, which is just the exact language of the claim and provides no guidance on exactly what this means. Since the code blocks would be coming from the processor of the UE, it would be in parallel format such as 8, 16, etc. bits wide, whereas the modulators, interleavers, etc. would be operating at the bit level so it appears that the data would be converted to a bitstream of bits rather than parallel words. For purposes of examination, Examiner interprets the claims to read “performing a conversion of the plurality of code blocks to bits and to generate a concatenated code blocks bitstream”. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 21-24, 26-27, 29-33, 35, 37-38, and 40 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Luo et al (US2012/0082075 A1) IDS submitted by Applicant. Regarding claims 21 and 30, Luo teaches an apparatus/ non-transitory computer-readable storage medium/ for a user equipment (UE) configured for operation in a Fifth Generation New Radio (5G NR) and beyond wireless network (Abstract), the apparatus comprising: processing circuitry, wherein to configure the UE for code block-based operation in the wireless network, the processing circuitry is to; and a memory coupled to the processing circuitry and configured to store the data bitstream (Paras. 0025 and 0028): encode a data bitstream to generate a plurality of code blocks (Figs. 3-6; Paras. 0006, 0023-0025, and 0037-0044; transmit (TX) multiple-input multiple-output (MIMO) processor 1230 may perform spatial processing (e.g., precoding) on the data symbols, the control symbols, and/or the reference symbols from transmit processor 1220, if applicable, and may provide T output symbol streams to T modulators (MODs) 1232 a through 1232 t. Each modulator 1232 may process a respective output symbol stream (e.g., for SC-FDMA, OFDM, etc.) to obtain an output sample stream; a plurality of information bits may be divided into a first set of information bits and a second set of information bits. The first and second set of information bits may be encoded, such as with one or more block encoders, to form a first and second set of coded bits; i.e. the sets of coded bits reads on the plurality of code blocks and there are a plurality of streams to create a plurality of sets of coded bits); perform code block interleaving of a subset of code blocks of the plurality of code blocks to generate an interleaved bitstream (Figs. 3-6; Paras. 0006, 0023-0025, and 0037-0044; After the first and second sets of coded bits are rate matched, the first and second sets of coded bits may be interleaved to generate a third set of coded bits for transmission. Interleaving may be either bit-level interleaving or symbol-level interleaving, and the bits may be interleaved into time slots in a pseudo-random or even/odd manner; i.e. each of two or more of the T sets of coded bits from the T streams where the two or more of the coded bits are a subset of the plurality of sets of coded bits); modulate the interleaved bitstream using a digital modulation scheme to obtain modulated data symbols (Figs. 3-6; Paras. 0006, 0023-0025, and 0037-0044; Each modulator 1232 may process a respective output symbol stream (e.g., for SC-FDMA, OFDM, etc.) to obtain an output sample stream); generate a set of time-domain samples according to discrete Fourier transform-spread-orthogonal frequency division multiplexing (DFT-s-OFDM) waveform using the modulated data symbols (Figs. 3-6; Paras. 0006, 0023-0025, and 0037-0044; PUCCH format 3 transmits a discrete Fourier transform single-carrier orthogonal frequency division multiplexing (DFT-S-OFDM) waveform in each SC-FDM symbol; In general, modulation symbols are sent in the frequency domain with OFDM and in the time domain with SC-FDM); and cause transmission of the set of time-domain samples (Figs. 3-6; Paras. 0006, 0023-0025, 0139-0142, 0188-0204, and 0306; PUCCH format 3 transmits a discrete Fourier transform single-carrier orthogonal frequency division multiplexing (DFT-S-OFDM) waveform in each SC-FDM symbol; In general, modulation symbols are sent in the frequency domain with OFDM and in the time domain with SC-FDM). Regarding claims 22 and 31, Luo teaches the limitations of the previous claims. Luo further teaches wherein the processing circuitry is configured to: perform the code block interleaving in bit domain (Figs. 3-6; Paras. 0006, 0023-0025, and 0037-0044; After the first and second sets of coded bits are rate matched, the first and second sets of coded bits may be interleaved to generate a third set of coded bits for transmission. Interleaving may be either bit-level interleaving or symbol-level interleaving, and the bits may be interleaved into time slots in a pseudo-random or even/odd manner). Regarding claims 23, 32, and 40, Luo teaches the limitations of the previous claims. Luo further teaches wherein the subset of code blocks comprises at least one code block bundle (CBB) with a pre-configured number of symbols (Figs. 3-6; Paras. 0006, 0023-0025, 0030, and 0037-0044; In one design, PUCCH Format 3 uses length-5 orthogonal cover codes (OCC) across data SC-FDM symbols in each time slot). Regarding claims 24 and 33, Luo teaches the limitations of the previous claims. Luo further teaches wherein the subset of code blocks comprises a plurality of DFT-s-OFDM symbols (Figs. 3-6; Paras. 0006, 0023-0025, 0030, and 0037-0044; PUCCH format 3 transmits a discrete Fourier transform single-carrier orthogonal frequency division multiplexing (DFT-S-OFDM) waveform in each SC-FDM symbol; In general, modulation symbols are sent in the frequency domain with OFDM and in the time domain with SC-FDM; In one design, PUCCH Format 3 uses length-5 orthogonal cover codes (OCC) across data SC-FDM symbols in each time slot). Regarding claim 26, Luo teaches the limitations of the previous claims. Luo further teaches wherein the processing circuitry is configured to: perform multiplexing of the interleaved bitstream to generate multiple bitstreams (Figs. 3-6; Paras. 0006, 0023-0025, and 0037-0044; transmit (TX) multiple-input multiple-output (MIMO) processor 1230 may perform spatial processing (e.g., precoding) on the data symbols, the control symbols, and/or the reference symbols from transmit processor 1220, if applicable, and may provide T output symbol streams to T modulators (MODs) 1232 a through 1232 t. Each modulator 1232 may process a respective output symbol stream (e.g., for SC-FDMA, OFDM, etc.) to obtain an output sample stream. Each modulator 1232 may further process (e.g., convert to analog, amplify, filter, and upconvert) the output sample stream to obtain an uplink signal. T uplink signals from modulators 1232 a through 1232 t may be transmitted via T antennas). Regarding claims 27 and 35, Luo teaches the limitations of the previous claims. Luo further teaches wherein the processing circuitry is configured to: perform DFT-s-OFDM modulation of the multiple multiplexed bitstreams to generate multiple streams of time-domain samples (Figs. 3-6; Paras. 0006, 0023-0025, and 0037-0044; transmit (TX) multiple-input multiple-output (MIMO) processor 1230 may perform spatial processing (e.g., precoding) on the data symbols, the control symbols, and/or the reference symbols from transmit processor 1220, if applicable, and may provide T output symbol streams to T modulators (MODs) 1232 a through 1232 t. Each modulator 1232 may process a respective output symbol stream (e.g., for SC-FDMA, OFDM, etc.) to obtain an output sample stream. Each modulator 1232 may further process (e.g., convert to analog, amplify, filter, and upconvert) the output sample stream to obtain an uplink signal. T uplink signals from modulators 1232 a through 1232 t may be transmitted via T antennas). Regarding claim 29, Luo teaches the limitations of the previous claims. Luo further teaches further comprising: transceiver circuitry coupled to the processing circuitry; and two or more antennas coupled to the transceiver circuitry; wherein the processing circuitry causes transmission of the multiple sets of time-domain samples using the two or more antennas (Figs. 3-6; Paras. 0006, 0023-0025, and 0037-0044; transmit (TX) multiple-input multiple-output (MIMO) processor 1230 may perform spatial processing (e.g., precoding) on the data symbols, the control symbols, and/or the reference symbols from transmit processor 1220, if applicable, and may provide T output symbol streams to T modulators (MODs) 1232 a through 1232 t. Each modulator 1232 may process a respective output symbol stream (e.g., for SC-FDMA, OFDM, etc.) to obtain an output sample stream. Each modulator 1232 may further process (e.g., convert to analog, amplify, filter, and upconvert) the output sample stream to obtain an uplink signal. T uplink signals from modulators 1232 a through 1232 t may be transmitted via T antennas). Regarding claim 37, Luo teaches a non-transitory computer-readable storage medium that stores instructions for execution by one or more processors of a user equipment (UE), the instructions to configure the UE for operation in a Fifth Generation New Radio (5G NR) and beyond wireless network (Abstract; Para. 25), and to cause the UE to perform operations comprising: encode a data bitstream to generate a plurality of code blocks (Figs. 3-6; Paras. 0006, 0023-0025, and 0037-0044; transmit (TX) multiple-input multiple-output (MIMO) processor 1230 may perform spatial processing (e.g., precoding) on the data symbols, the control symbols, and/or the reference symbols from transmit processor 1220, if applicable, and may provide T output symbol streams to T modulators (MODs) 1232 a through 1232 t. Each modulator 1232 may process a respective output symbol stream (e.g., for SC-FDMA, OFDM, etc.) to obtain an output sample stream; a plurality of information bits may be divided into a first set of information bits and a second set of information bits. The first and second set of information bits may be encoded, such as with one or more block encoders, to form a first and second set of coded bits; i.e. the sets of coded bits reads on the plurality of code blocks and there are a plurality of streams to create a plurality of sets of coded bits); performing parallel-to-serial conversion of the plurality of code blocks to generate a concatenated code blocks bitstream (Figs. 3-6; Paras. 0006, 0023-0025, and 0037-0044; Interleaving may be either bit-level interleaving or symbol-level interleaving, and the bits may be interleaved into time slots in a pseudo-random or even/odd manner; i.e. the plurality of information bits would need to be converted to a bit stream for processing); modulating the concatenated code blocks bitstream using a digital modulation scheme to obtain modulated data symbols (Figs. 3-6; Paras. 0006, 0023-0025, and 0037-0044; Each modulator 1232 may process a respective output symbol stream (e.g., for SC-FDMA, OFDM, etc.) to obtain an output sample stream); performing interleaving of a subset of the modulated data symbols to obtain interleaved modulated data symbols (Figs. 3-6; Paras. 0006, 0023-0025, and 0037-0044; After the first and second sets of coded bits are rate matched, the first and second sets of coded bits may be interleaved to generate a third set of coded bits for transmission. Interleaving may be either bit-level interleaving or symbol-level interleaving, and the bits may be interleaved into time slots in a pseudo-random or even/odd manner); generate a set of time-domain samples according to discrete Fourier transform-spread-orthogonal frequency division multiplexing (DFT-s-OFDM) waveform using the interleaved modulated data symbols (Figs. 3-6; Paras. 0006, 0023-0025, and 0037-0044; PUCCH format 3 transmits a discrete Fourier transform single-carrier orthogonal frequency division multiplexing (DFT-S-OFDM) waveform in each SC-FDM symbol; In general, modulation symbols are sent in the frequency domain with OFDM and in the time domain with SC-FDM); and cause transmission of the set of time-domain samples (Figs. 3-6; Paras. 0006, 0023-0025, 0139-0142, 0188-0204, and 0306; PUCCH format 3 transmits a discrete Fourier transform single-carrier orthogonal frequency division multiplexing (DFT-S-OFDM) waveform in each SC-FDM symbol; In general, modulation symbols are sent in the frequency domain with OFDM and in the time domain with SC-FDM). Regarding claim 38, Luo teaches the limitations of the previous claims. Luo further teaches the operations further comprising: performing multiplexing of the interleaved modulated data symbols to generate multiple modulated data symbols streams (Figs. 3-6; Paras. 0006, 0023-0025, and 0037-0044; transmit (TX) multiple-input multiple-output (MIMO) processor 1230 may perform spatial processing (e.g., precoding) on the data symbols, the control symbols, and/or the reference symbols from transmit processor 1220, if applicable, and may provide T output symbol streams to T modulators (MODs) 1232 a through 1232 t. Each modulator 1232 may process a respective output symbol stream (e.g., for SC-FDMA, OFDM, etc.) to obtain an output sample stream. Each modulator 1232 may further process (e.g., convert to analog, amplify, filter, and upconvert) the output sample stream to obtain an uplink signal. T uplink signals from modulators 1232 a through 1232 t may be transmitted via T antennas). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 25, 28, 34, 36, and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Luo et al (US2023/0073095 A1) IDS submitted by Applicant in view of Horn et al (US 2023/0318778 A1). Regarding claim 25, Luo teaches the limitations of the previous claims. However, while Luo teaches a reference signal allocated with the data (Fig. 3; Para. 0031), he does not specifically disclose wherein the processing circuitry is configured to: insert phase tracking reference signals (PT-RS) among the modulated data symbols. Horn teaches a user equipment (UE) may transmit an indication of a capability to receive or transmit a time domain communication having a first portion of a symbol configured with a first modulation and coding scheme (MCS) and a second portion of the symbol configured with a second MCS that is different from the first MCS (Abstract). He further teaches wherein the processing circuitry is configured to: insert phase tracking reference signals (PT-RS) among the modulated data symbols (Para. 0072; the time domain reference signals may include a time domain phase tracking reference signals (PTRSs) to compensate for an integrated phase noise (IPN) that increases with higher frequencies). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings as in Horn with the teachings as in Luo. The motivation for doing so would have been to better support mobile broadband internet access by improving spectral efficiency, lowering costs, improving services, making use of new spectrum, and better integrating with other open standards using orthogonal frequency division multiplexing (OFDM) with a cyclic prefix (CP) (CP-OFDM) on the downlink, using CP-OFDM and/or single-carrier frequency division multiplexing (SC-FDM) (also known as discrete Fourier transform spread OFDM (DFT-s-OFDM)) on the uplink (Horn at para. 0004). Regarding claims 28, 36, and 39, Luo teaches the limitations of the previous claims. Luo further teaches wherein the processing circuitry is configured to: perform DFT spreading and subcarrier mapping using the multiple streams of modulated data symbols to generate multiple streams of data subcarriers (Paras. 0023 and 0032; OFDM and SC-FDM partition a frequency range into multiple (Ks) orthogonal subcarriers, which are also commonly referred to as tones, bins, etc. Each subcarrier may be modulated with data). However, while Luo teaches a reference signal allocated with the data (Fig. 3; Para. 0031), he does not specifically disclose perform DFT spreading; and perform inverse fast Fourier transform (IFFT) and cyclic prefix (CP) addition using the multiple streams of data subcarriers to generate the multiple sets of time-domain samples. Horn teaches a user equipment (UE) may transmit an indication of a capability to receive or transmit a time domain communication having a first portion of a symbol configured with a first modulation and coding scheme (MCS) and a second portion of the symbol configured with a second MCS that is different from the first MCS (Abstract). He further teaches perform DFT spreading; and perform inverse fast Fourier transform (IFFT) and cyclic prefix (CP) addition using the multiple streams of data subcarriers to generate the multiple sets of time-domain samples (Paras. 0004, 0065, 0076, 0139-0142, 0188-0197, and 0306; NR is designed to better support mobile broadband internet access by improving spectral efficiency, lowering costs, improving services, making use of new spectrum, and better integrating with other open standards using orthogonal frequency division multiplexing (OFDM) with a cyclic prefix (CP) (CP-OFDM) on the downlink, using CP-OFDM and/or single-carrier frequency division multiplexing (SC-FDM) (also known as discrete Fourier transform spread OFDM (DFT-s-OFDM)) on the uplink, as well as supporting beamforming, multiple-input multiple-output (MIMO) antenna technology, and carrier aggregation; an RU 340, controlled by a DU 330, may correspond to a logical node that hosts RF processing functions, or low-PHY layer functions (such as performing fast Fourier transform (FFT), inverse FFT (iFFT), digital beamforming, physical random access channel (PRACH) extraction and filtering, or the like), or both, based at least in part on the functional split, such as a lower layer functional split). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings as in Horn with the teachings as in Luo. The motivation for doing so would have been to better support mobile broadband internet access by improving spectral efficiency, lowering costs, improving services, making use of new spectrum, and better integrating with other open standards using orthogonal frequency division multiplexing (OFDM) with a cyclic prefix (CP) (CP-OFDM) on the downlink, using CP-OFDM and/or single-carrier frequency division multiplexing (SC-FDM) (also known as discrete Fourier transform spread OFDM (DFT-s-OFDM)) on the uplink (Horn at para. 0004). Regarding claim 34, Luo teaches the limitations of the previous claims. Luo further teaches wherein the operations further comprising: performing multiplexing of the interleaved bitstream to generate multiple bitstreams (Figs. 3-6; Paras. 0006, 0023-0025, and 0037-0044; transmit (TX) multiple-input multiple-output (MIMO) processor 1230 may perform spatial processing (e.g., precoding) on the data symbols, the control symbols, and/or the reference symbols from transmit processor 1220, if applicable, and may provide T output symbol streams to T modulators (MODs) 1232 a through 1232 t. Each modulator 1232 may process a respective output symbol stream (e.g., for SC-FDMA, OFDM, etc.) to obtain an output sample stream. Each modulator 1232 may further process (e.g., convert to analog, amplify, filter, and upconvert) the output sample stream to obtain an uplink signal. T uplink signals from modulators 1232 a through 1232 t may be transmitted via T antennas). However, while Luo teaches a reference signal allocated with the data (Fig. 3; Para. 0031), he does not specifically disclose inserting phase tracking reference signals (PT-RS) among the modulated data symbols. Horn teaches a user equipment (UE) may transmit an indication of a capability to receive or transmit a time domain communication having a first portion of a symbol configured with a first modulation and coding scheme (MCS) and a second portion of the symbol configured with a second MCS that is different from the first MCS (Abstract). He further teaches inserting phase tracking reference signals (PT-RS) among the modulated data symbols (Para. 0072; the time domain reference signals may include a time domain phase tracking reference signals (PTRSs) to compensate for an integrated phase noise (IPN) that increases with higher frequencies). Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings as in Horn with the teachings as in Luo. The motivation for doing so would have been to better support mobile broadband internet access by improving spectral efficiency, lowering costs, improving services, making use of new spectrum, and better integrating with other open standards using orthogonal frequency division multiplexing (OFDM) with a cyclic prefix (CP) (CP-OFDM) on the downlink, using CP-OFDM and/or single-carrier frequency division multiplexing (SC-FDM) (also known as discrete Fourier transform spread OFDM (DFT-s-OFDM)) on the uplink (Horn at para. 0004). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENT KRUEGER whose telephone number is (303)297-4238. The examiner can normally be reached on M-F 8:00-5:00 MT. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Thier can be reached on (571) 272-2832. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KENT KRUEGER/Primary Examiner, Art Unit 2474
Read full office action

Prosecution Timeline

Sep 05, 2023
Application Filed
Dec 30, 2025
Non-Final Rejection — §102, §103, §112 (current)

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Expected OA Rounds
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94%
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2y 6m
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