Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 2, 12, 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Kim, Y et al., "A Reconfigurable Digital Neuromorphic Processor with Memristive Synaptic Crossbar for Cognitive Computing," ACM J. Emerg . Technol. Comput . Syst. April 27, 2015, Volume 11, Issue 4, Article 38; pp. 1-25. https://doi.org/10.1145/2700234 , filed as an IDS reference filed on 09/06/2023), hereinafter, “Kim” in view of Chiarello et al. ( Chiarello , F. et al., "Artificial neural network base don SQUIDS: demonstration of network training and operation," Semantic Scholar, Computer Science, Superconductor Science and Technology, May 7, 2012; pp.1-11. https://arxiv.org/ftp/arxiv/papers/1205/1205.1422 , filed as an IDS reference filed on 09/06/2023), hereinafter, “ Chiarello ”. Regarding Claims 1 and 16 , Kim discloses a neuromorphic computing circuit comprising: a plurality of memristors that function as synapses (See, Page 38.4, Fig. 1, “Memristor Crossbar Array” and “Synapse Unit” and Page 38.3, Paragraph 5- Page 38/2, Paragraph 1) ; and a superconducting quantum interference device (SQUID) coupled to the plurality of memristors and that functions as a neuron such that the plurality of memristors and the interference device form a neural unit of the neuromorphic computing circuit (See, Page 38.4, Fig. 1, Synapse Unit, Neuron unit along with “LIF Arithmetic Unit”, Page 38.3, Paragraph 5-Page 38.5, Paragraph 1) . Kim does not explicitly disclose superconducting quantum interference device (SQUID) that function as a neuron. Chiarello discloses superconducting quantum interference device (SQUID) that function as a neuron (See, Page 1, Paragraph 3- Page 2, Paragraph 1). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use, in the system of Kim, superconducting quantum interference device (SQUID) that function as a neuron as taught by Chiarello in order to provide high computational speeds and also allows amplification, readout and memorization of the input signals. Regarding Claim 2 , the rejection of claim 1 is incorporated and Kim in view of Chiarello further discloses wherein the plurality of memristors are in the form of a memristor crossbar array (See, Page 38.4, Fig. 1, “Memristor Crossbar Array”). Regarding Claim s 12 and 20 , the rejection of claims 1 and 16 is incorporated and Kim in view of Chiarello further discloses wherein the SQUID includes a superconducting loop and two Josephson junctions (See, Chiarello , Page 1, Paragraph 3-Page 2, Paragraph 1, Since the feature of using SQUID has been combined in the rejection of claim s 1 and 16 and this claim further limit the combined feature, a separate motivation to combine statement is not needed. See rejection of claim s 1 and 16). Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chiarello and further in view of Wan g et al. (US 2014/0103282 A1). Regarding Claim 3 , the rejection of claim 1 is incorporated and the combination of Kim and Chiarello does not explicitly disclose wherein each memristor in the plurality of memristors includes a pin-hole free, uniform, and atomically thin tunneling barrier. Wang discloses memory registers that includes a pin-hole free, uniform, and atomically thin tunneling barrier (See, Paragraphs 0008 and 0029). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use, in the system of Kim and Chiarello , memristors that includes a pin-hole free, uniform, and atomically thin tunneling barrier as taught by Wang in order to ensure a consistency of diffusion barrier properties (See, Wang, Paragraph 0008). Claim s 5, 6 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chiarello and further in view of Hansen ( Hansen, Mirko. On the development of memristive devices for electroforming-free and analog memristive crossbar arrays. Diss. Christian- Albrechts Universität Kiel, 2018 ), hereinafter, “Hansen” . Regarding Claims 5 and 17 , the rejection of claims 1 and 16 is incorporated and the combination of Kim and Chiarello does not explicitly disclose wherein the plurality of memristors include superconducting electrodes and wires. Hansen discloses memristors includ ing superconducting electrodes and wires (See, Pages 37-38, Section 4.2.2, “Low Temperature Measurements” and Page 81, Section 7.1.2, “Tunnel Barrier Characterization” ). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use, in the system of Kim and Chiarello , memristors that includes superconducting electrodes and wires as taught by Hansen because superconducting electrodes made with niobium provides highest critical temperature with zero energy dissipation. Regarding Claim 6 , the rejection of claim 5 is incorporated and the combination of Kim, Chiarello and Hansen further discloses wherein the superconducting electrodes comprises niobium electrodes and wires that are lossless at cryogenic temperatures below 9.3 Kelvin (See, Hansen, Pages 37-38, Section 4.2.2, “Low Temperature Measurements” and Page 81, Section 7.1.2, “Tunnel Barrier Characterization”). Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chiarello and further in view of Stasiak et al. (US 2005/0123674 A1), hereinafter, “ Stasiak ”. Regarding Claim 11 , the rejection of claim 5 is incorporated and the combination of Kim and Chiarello does not explicitly disclose wherein the SQUID includes electrodes that have a superconducting transition temperature of 9.3 Kelvin. Stasiak discloses a SQUID includes electrodes that have a superconducting transition temperature of 9.3 Kelvin (See, Paragraphs 0034, 0043, 0048, Note : Stasiak uses Niobium based superconductor electrodes which are known to have a superconducting transition temperature of 9.3 Kelvin). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use, in the system of Kim and Chiarello , Squid that includes electrodes that have a superconducting transition temperature of 9.3 Kelvin as taught by Stasiak because superconducting electrodes made with niobium provides highest critical temperature with zero energy dissipation. Allowable Subject Matter Claims 4, 7-10, 13-15 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT YOGESH PALIWAL whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-1807 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F 9:00AM-5:00PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Amir Mehrmanesh can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571)270-3351 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YOGESH PALIWAL/ Primary Examiner, Art Unit 2435