DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
No Information Disclosure Statement has been submitted.
The Examiner would like to remind Applicants about Duty of Disclosure, Candor, and Good Faith (See 37 C.F.R. F56 and MPEP2001).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 6-10, 12, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2019/0296048 (corresponding to US 10,811,4370).
In re Claim 1, Lee discloses a pixel unit structure comprising a gate line 121 (Figs. 1), a data line 171 and a thin film transistor Q (Fig. 4), wherein the gate line 121 and the data line 171 intersect and define a pixel region PX; wherein the thin film transistor Q (Fig. 4) comprises a source electrode 173, an interlayer dielectric layer 180, a gate electrode 124, a gate insulating layer 140, a drain electrode 175 and a metal oxide semiconductor layer 153 formed on a substrate 110, wherein the source electrode 173, the interlayer dielectric layer 180, the gate electrode 124 and the gate insulating layer 140 are sequentially disposed in a direction away from the substrate 110; the source electrode 173 is connected to the data line 171; the gate electrode 124 is connected to the gate line 121; the drain electrode 175 is disposed on a side of the gate insulating layer 140 away from the substrate 110; the metal oxide semiconductor layer 153 is disposed on a side of the gate insulating layer 140 away from the substrate 110, and comprises a semiconductor portion (marked as SP in Fig. A) and a first conductive portion (a portion of 153 underneath 165, marked as 1CP in Fig. A) and a second conductive portion (a portion of 153 underneath 163, marked as 2CP in Fig. A) respectively located on both sides of the semiconductor portion SP, wherein the semiconductor portion SP covers a protrusion P of the gate insulating layer 140, and the protrusion P is a portion where the gate insulating layer 140 covers the gate electrode 124; a terminal 165 of the first conductive portion 1CP adjacent to the drain electrode 175 is connected to the drain electrode or serves as at least a portion of the drain electrode 175; and the second conductive portion (the portion of 153 underneath 163) is connected to the source electrode 173 (Figs. 1-4 and A, [0006 -0141]).
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Fig. A. Lee’s Fig. 4 annotated to show the details cited
Lee does not explicitly indicate that the second conductive portion 2CP is connected to the source electrode 173 through a first via formed correspondingly on the gate insulating layer 140 and the interlayer dielectric layer 180a.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to connect the second conduction portion 2CP to the source electrode 173 through a first via 235 formed correspondingly on the gate insulating layer 140 and the interlayer dielectric layer 180a, since it was well-known in the art as and shown by T in Fig. A. (See MPEP2144.I.)
In re Claim 6, Lee discloses the pixel unit structure according to claim 1, wherein the first conductive portion 1CP is disposed in a same layer as the drain electrode 175, and a terminal 165 of the first conductive portion 1CP adjacent to the drain electrode 175 is superposed on a side of the drain electrode 175 away from the substrate 110 (Fig. A).
In re Claim 7, Lee discloses the pixel unit structure according to claim 6, wherein the thin film transistor Q further comprises a passivation layer (a lower portion of 230), a planarization layer (an upper portion of 230) and a pixel electrode 191, wherein the passivation layer (the lower portion of 230) is disposed on a side of the interlayer dielectric layer 180a away from the substrate 110 and covers the metal oxide semiconductor layer 153; the planarization layer (the upper portion of 230) is disposed on a side of the passivation layer (the lower portion of 230) away from the substrate 110; the pixel electrode 191 is disposed on a side of the planarization layer (the upper portion of 230) away from the substrate 110, and is connected to the drain electrode 175 through a second via 235 correspondingly formed on the planarization layer (the upper portion of 230) and the passivation layer (the lower portion of 230) (Fig. A).
In re Claim 8, Lee discloses the pixel unit structure according to claim 1, wherein the thin film transistor further comprises a passivation layer (a lower portion of 230) disposed on a side of the interlayer dielectric layer 180a away from the substrate 110 and covering the metal oxide semiconductor layer 153; the drain electrode 197 (197 is essentially drain electrode being electrically connected to 175) is disposed on a side of the passivation layer (the lower portion of 230) away from the substrate 110, and is connected to the first conductive portion 1CP through a third via 235 formed on the passivation layer (a lower portion of 230) (Fig. A).
In re Claim 9, Lee discloses the pixel unit structure according to claim 8, wherein the thin film transistor Q further comprises a planarization layer (an upper portion of 230) and a pixel electrode 191, wherein the planarization layer (the upper portion of 230) is disposed on a side of the passivation layer (the lower portion of 230) away from the substrate 110; the pixel electrode 191 is disposed on a side of the planarization layer (the upper portion of 230) away from the substrate 110, and is connected to the drain electrode 175 through a second via formed on the planarization layer (the upper portion of 230) (Fig. A).
In re Claim 10, Lee discloses the pixel unit structure according to claim 1, wherein a terminal T of the first conductive portion 1CP adjacent to the drain electrode 175 (being electrically connected to 175) serves as at least a portion of the drain electrode 175; the thin film transistor Q further comprises a passivation layer (a lower portion of 230), a planarization layer (an upper portion of 230) and a pixel electrode 191, wherein the passivation layer (the lower portion of 230) is disposed on a side of the interlayer dielectric layer 180a away from the substrate 110 and covers the metal oxide semiconductor layer 153; the planarization layer (the upper portion of 230) is disposed on a side of the passivation layer (the lower portion of 230) away from the substrate 110; the pixel electrode 191 is disposed on a side of the planarization layer (the upper portion of 230) away from the substrate 110, and is connected to the first conductive portion 1CP through a second via 235 correspondingly formed on the planarization layer (the upper portion of 230) and the passivation layer (the lower portion of 230) (Fig. A).
In re Claim 12, Lee discloses all limitations of Claim 12 including that the interlayer dielectric layer 180a comprises silicon dioxide ([0089]), except for that a thickness of the interlayer dielectric layer 1890a is greater than or equal to 5000A. It is known in the art that the layer thickness is a result effective variable – because its mas depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the thickness of the interlayer dielectric layer 180a is greater than or equal to 5000Å, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (MPEP2144.05.I).
In re Claim 14, the phrase “A display panel comprising the pixel unit structure according to Claim 1” merely represents an intended use or a manner in which a claimed apparatus is intended to be employed and does not differentiate the claimed apparatus from a prior art apparatus of Lee. See MPEP 2114. II. MANNER OF OPERATING THE DEVICE DOES NOT DIFFERENTIATE APPARATUS CLAIM FROM THE PRIOR ART. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987).
Allowable Subject Matter
Claims 2-5, 11, and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reason for indicating allowable subject matter
In re Claim 2: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 2 as: “the gate electrode comprises a first outer surface adjacent to the interlayer dielectric layer and a second outer surface adjacent to the gate insulating layer; and a cross section length of the second outer surface in a direction perpendicular to an extension direction of the gate electrode satisfies that an equivalent channel length is greater than or equal to a preset length”, in combination with limitations of Claim 1 on which it depends.
In re Claim 11: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 11 as: “an orthographic projection of the second via on a plane parallel to the substrate overlaps an orthographic projection of the gate on a plane parallel to the substrate”, in combination with limitations of Claims 1 and 10 on which it depends.
In re Claim 13: The prior art of record cited by the current office action, alone or in combination, fail to anticipate or render obvious such limitation of claim 13 as: “the passivation layer comprises a first passivation layer and a second passivation layer disposed in sequence in a direction away from the substrate, and the first passivation portion comprises silicon dioxide; and the second passivation portion comprises silicon nitride or silicon oxynitride”, in combination with limitations of Claims 1 and 10 on which it depends.
Claims 15-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
In re Claim 15, prior-art fails to disclose a method for preparing a pixel unit structure, comprising a step of “correspondingly forming a first via on the gate insulating layer and the interlayer dielectric layer … the second conductive portion is connected to the source electrode through the first via.” Therefore, the claimed method differs from prior art methods on this point and there is no evidence it would have been obvious to make this change.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nakagawa, US 2020/0271997;
Nakagawa, US 11,333,935.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIKOLAY K YUSHIN whose telephone number is (571)270-7885. The examiner can normally be reached Monday-Friday (7-7 PST).
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/NIKOLAY K YUSHIN/Primary Examiner, Art Unit 2893