DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites at least one transistor on line three for the asymmetric amplifier and again in the same claim on line 5 recites plural transistors for the same amplifier. This renders the limitation of at least one transistor void. If the applicant wants to broaden claim 1 by at least one transistor then in a dependent claim of claim 7 applicant could use the plural transistors as further limiting claim limitation.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 8-10 are rejected under 35 U.S.C. 102 as being anticipated by Gui-Jia Su, “Multilevel DC-Link Inverter”, IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 41, NO. 3, MAY/JUNE 2005, cited by the applicant).
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Fig. 3(a) of Su reproduced for ease of reference.
Regarding claim 7, Su discloses (Fig. 3): a linear amplifier for providing a sinusoidal waveform to a load (Fig. 3a and 3b; and section 11-B. The circuit of figure 3a acts as a DC to AC converter, where the diode clamped leg is the linear amplifier part as claimed and the inductive load RL-XL is shown in Figs. 6 and 7 exemplarily), characterized in that the linear amplifier (diode clamped leg) is composed of an asymmetric amplifier (Fig. 3a; and section II-B. The "diode clamped leg" part of figure 3a is based on a similar stacked NMOS, per claim 8, transistor architecture of the "asymmetric amplifier" of figure 1 of the present application) and a H-bridge module (Fig. 3a (SPFB inverter); and section II-B.), the asymmetric amplifier comprises at least one transistor (Fig. 3a (S1 to S10); and section 11-B) that amplifies a full wave rectified sinus signal (Fig. 3a and 3b; and sections II-A and II-B. The Vbus signal provided by the transistors S1-S10 to the SPFB inverter is said to "approximate the rectified waveform of the commanded sinusoidal voltage".) that is transformed by the H bridge module into a sinewave signal that is provided to the load (Fig. 3a (SPFB inverter) and 3b; and section II-B.
Concerning claims 9 and 12, Su discloses in section II-B and figures 3a and 3b that different combinations of the transistors S1 to S10 are used to produce the different voltage levels of the full wave rectified sinus signal. Each time a new transistor (which was in off stage) is added (while the others are in on stage) to increase the voltage level, it must pass through its "linear amplification stage" and per claims 10 and 13, the asymmetric amplifier (the diode clamped leg) comprises the same number of DC voltage sources (capacitors form a voltage divider and as such each capacitor adds a new voltage level) as the number of transistors (thus for 11 levels set by 10 transistors with 5 on each side of the sine wave, see Fig. 3(b)) and per claims 11 and 14, each voltage source (i.e. each capacitor provides the same additional voltage value, the step sizes are equal).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
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