DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/14/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 5, 6 and 11 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Regarding claim 5, Currently claim 5 does not further limit the scope of claim 1 as currently amended claim 1 includes all of the limitations recited in claim 5. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Regarding claim 6, Currently claim 6 includes an option in which claim 6 would not further limit claim 1. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Regarding claim 11, Currently claim 11 does not further limit the scope of claim 10 as currently amended claim 10 includes all of the limitations recited in claim 11. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 6 and 11, a first barrier sub-layer, a second barrier sub-layer, a first groove structure and a second groove structure are recited in claims 6 and 11. However, claims 1 and 10, from which claims 6 and 11 depend from, respectively, also recite a first barrier sub-layer, a second barrier sub-layer, a first groove structure and a second groove structure. Therefore, it is unclear whether the “a first barrier sub-layer”, “a second barrier sub-layer”, “a first groove structure” and “a second groove structure” recited in claims 6 and 11 are the same structures as the “a first barrier sub-layer”, “a second barrier sub-layer”, “a first groove structure” and “a second groove structure”, respectively, recited in claims 1 and 10. Appropriate correction is required to clarify the language. For purposes of compact prosecution the Examiner interprets the a first barrier sub-layer, a second barrier sub-layer, a first groove structure and a second groove structure recited in respective claims 6 and 11 to be the same structures as the a first barrier sub-layer, a second barrier sub-layer, a first groove structure and a second groove structure recited in claims 1 and 10.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 6, 10, 11, 14, 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Azize et al. (US 2016/0351564) hereinafter “Azize” in view of Lavanga et al. (US 2018/0151681) hereinafter “Lavanga”.
Regarding claim 1, Fig. 8 of Azize teaches a GaN-based High Electron Mobility Transistor (HEMT) structure (Paragraph 0041) having a multi-threshold voltage, comprising a channel layer (Item 606) and a barrier layer (Item 608; Paragraph 0080 where Item 608 is formed using materials and processes similar for barrier layers), wherein a Two- dimensional Electron Gas (2DEG) is formed between the channel layer and the barrier layer (Paragraph 0064); the barrier layer is at least provided with a first source area (Item 816 in Item 810), a second source area (Item 816 in Item 820), a first gate area (Item 812), a second gate area (Item 822), a first drain area (Item 818 in Item 810), and a second drain area (Item 818 in Item 820); the first source area, the first gate area, and the first drain area cooperate with each other to form a first HEMT unit (Item 810), and the first HEMT unit (Item 810) has a first threshold voltage (Paragraph 0080); the second source area, the second gate area, and the second drain area cooperate with each other to form a second HEMT unit (Item 820), and the second HEMT unit (Item 820) has a second threshold voltage (Paragraph 0080); and a thickness of the barrier layer (Item 608) in the first gate area (Area under gate Item 812) is less than a thickness of the barrier layer in the second gate area (Area under gate Item 822) to enable the first threshold voltage to be higher than the second threshold voltage (Paragraph 0090) and wherein a thickness from a bottom- most surface (Bottom of Item 619) to a top-most surface the barrier layer (Top of Item 611) in the first HEMT unit (Item 810) is equal to a thickness from a bottom-most surface (Bottom of Item 619) to a top-most surface (Top of Item 611) of the barrier layer in the second HEMT unit (Item 820), wherein the barrier layer (Item 608) comprises a first barrier sub-layer and a second barrier sub-layer disposed on the first barrier sub-layer (Paragraph 0080), and wherein a groove structure is formed in at least one of the first gate area and the second gate area of the barrier layer, the groove structure comprises a first groove structure and a second groove structure, and the first groove structure is formed in the first barrier sub-layer.
Azize does not teach where a local area of the second barrier sub-layer is present in the first groove structure to form the second groove structure.
Fig. 3 of Lavanga teaches where a barrier layer is formed having a first barrier layer (Item 108) and a second barrier layer (Item 118), where a local area of the second barrier layer is present in a groove structure in the first barrier layer to form a second groove.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a local area of the second barrier sub-layer be present in a first groove structure to form a second groove structure because this is known to form a trench for a gate in a HEMT device (Lavanga Paragraph 0025).
The process limitation of “and a local area of the second barrier sub-layer sinks into the first groove structure to form the second groove structure” found in product claim 1 invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Anticipation of claim 1 does not require a local area of the second barrier sub-layer to sink into the first groove to form the second groove, but simply that a second barrier layer is present within a groove of the first barrier sub-layer when forming the trench. However, Lavanga does disclose a local area of the second barrier sub-layer sinks into the first groove structure to form the second groove structure (Fig. 3; Paragraph 0026).
Regarding claim 5, Fig. 8 of Azize further teaches where the barrier layer (Item 608) comprises a plurality of barrier sub-layers (Paragraph 0080) sequentially arranged (Where the layers are vertically arranged) on the channel layer (Item 606).
Regarding claim 6, Fig. 8 of Azize further teaches where wherein a groove structure is formed in at least one of the first gate area (Item 812) and the second gate area (Item 822) of the barrier layer; a notch of the groove structure is distributed on a surface of the barrier layer; and a groove bottom is distributed in one of the plurality of barrier sub-layers, at an interface of two adjacent barrier sub-layers.
Regarding claim 10, Fig. 8 of Azize teaches a method for preparing a GaN-based HEMT structure having a multi-threshold voltage (Paragraph 0041), comprising: sequentially growing a channel layer (Item 606) and a barrier layer (Item 608) on a substrate (Item 602), wherein sequentially growing the barrier layer (Item 608) comprises first growing a first barrier sub-layer, growing a second barrier sub-layer and etching the first and second barrier sub-layers to form the barrier layer; at least defining a first source area (Item 816 in Item 810), a second source area (Item 816 in Item 820), a first gate area (Item 812), a second gate area (Item 822), a first drain area (Item 818 in Item 810), and a second drain area (Item 818 in Item 820) on the barrier layer (Item 608), wherein the first source area, the first gate area, and the first drain area cooperate with each other to form a first HEMT unit (Item 810), the second source area, the second gate area, and the second drain area cooperate with each other to form a second HEMT unit (Item 820), the first HEMT unit has a first threshold voltage, and the second HEMT unit has a second threshold voltage (Paragraph 0090); and enabling a thickness of the barrier layer in the first gate area (Item 812) to be less than the thickness of the barrier layer in the second gate area (Item 822) to enable the first threshold voltage to be higher than the second threshold voltage and wherein a thickness from a bottom-most surface (Bottom of Item 619) to a top-most surface (Top of Item 611) the barrier layer in the first HEMT unit (Item 810) is equal to a thickness from a bottom-most surface (Bottom of Item 619) to a top-most surface (Top of Item 611) of the barrier layer in the second HEMT unit (Item 820).
Azize does not teach where sequentially growing the barrier layer comprises first growing a first barrier sub-layer, and etching a first groove structure in a selected area of the first barrier sub-layer, wherein the selected area corresponds to the first gate area; and then growing a second barrier sub-layer on the first barrier sub-layer, enabling a local area of the second barrier sub-layer to sink into the first groove structure, and forming a second groove structure to form the barrier layer.
Fig. 3 of Lavanga teaches where a barrier layer is formed by first growing a first barrier sub-layer (Item 108), and etching a first groove structure (Item 112) in a selected area of the first barrier sub-layer (Item 108), wherein the selected area corresponds to the first gate area; and then growing a second barrier sub-layer (Item 118) on the first barrier sub-layer (Item 108), enabling a local area of the second barrier sub-layer (Item 118) to sink into the first groove structure (Item 112), and forming a second groove structure to form the barrier layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have sequentially growing the barrier layer comprises first growing a first barrier sub-layer, and etching a first groove structure in a selected area of the first barrier sub-layer, wherein the selected area corresponds to the first gate area; and then growing a second barrier sub-layer on the first barrier sub-layer, enabling a local area of the second barrier sub-layer to sink into the first groove structure, and forming a second groove structure to form the barrier layer because this is known to form a trench for a gate in a HEMT device (Lavanga Paragraph 0025).
Regarding claim 11, the combination of Azize and Lavanga teaches all of the elements of the claimed invention as stated above.
Azize does not teach where sequentially growing the barrier layer comprises first growing a first barrier sub-layer, and etching a first groove structure in a selected area of the first barrier sub-layer, wherein the selected area corresponds to the first gate area; and then growing a second barrier sub-layer on the first barrier sub-layer, enabling a local area of the second barrier sub-layer to sink into the first groove structure, and forming a second groove structure to form the barrier layer.
Fig. 3 of Lavanga teaches where a barrier layer is formed by first growing a first barrier sub-layer (Item 108), and etching a first groove structure (Item 112) in a selected area of the first barrier sub-layer (Item 108), wherein the selected area corresponds to the first gate area; and then growing a second barrier sub-layer (Item 118) on the first barrier sub-layer (Item 108), enabling a local area of the second barrier sub-layer (Item 118) to sink into the first groove structure (Item 112), and forming a second groove structure to form the barrier layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have sequentially growing the barrier layer comprises first growing a first barrier sub-layer, and etching a first groove structure in a selected area of the first barrier sub-layer, wherein the selected area corresponds to the first gate area; and then growing a second barrier sub-layer on the first barrier sub-layer, enabling a local area of the second barrier sub-layer to sink into the first groove structure, and forming a second groove structure to form the barrier layer because this is known to form a trench for a gate in a HEMT device (Lavanga Paragraph 0025).
Regarding claim 14, Fig. 8 of Azize further teaches growing a gate dielectric layer (Item 814) on the barrier layer (Item 608), and enabling the gate dielectric layer to at least continuously cover an inner wall of the groove structure.
Regarding claim 15, Azize further teaches a method of an application of the GaN-based HEMT structure having the multi-threshold voltage according to claim 1 (See rejection of claim 1 above; For brevity the rejection of claim 1 will not be repeated here) in a manufacturing of high and low threshold logic circuits (Paragraphs 0041).
Regarding claim 20, Azize further teaches the barrier layer (Item 608) comprises a plurality of barrier sub-layeres sequentially arranged on the channel layer (Item 606).
Claims 2, 3, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Azize et al. (US 2016/0351564) hereinafter “Azize” in view of Lavanga et al. (US 2018/0151681) hereinafter “Lavanga” and in further view of Chern (US 2022/0130989) hereinafter “Chern”.
Regarding claim 2, the combination of Azize and Lavanga teaches all of the elements of the claimed invention as stated above except where the barrier layer is further provided with a third source area, a third gate area, and a third drain area; the third source area, the third gate area, and the third drain area cooperate with each other to form a third HEMT unit, and the third HEMT unit has a third threshold voltage.
Fig. 3P of Chern further teaches where the barrier layer (Combination of Items 331-333) is further provided with a third source area (Item 383), a third gate area (Item 353), and a third drain area (Item 393); the third source area (Item 383), the third gate area (Item 353), and the third drain area (Item 393) cooperate with each other to form a third HEMT unit, and the third HEMT unit has a third threshold voltage, where the first threshold voltage > the second threshold voltage (Paragraph 0017) and the second threshold voltage> the third threshold voltage (Fig. 2B; Paragraph 0060).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the barrier layer be further provided with a third source area, a third gate area, and a third drain area; the third source area, the third gate area, and the third drain area cooperate with each other to form a third HEMT unit, and the third HEMT unit has a third threshold voltage because this allows for multistage HEMT based drivers which can be used as an integrated circuit to minimize static current (Chern Paragraph 0014).
Chern does not specifically teach where the thickness of the barrier layer in the second gate area is less than a thickness of the barrier layer in the third gate area to enable the first threshold voltage > the second threshold voltage > the third threshold voltage.
However, Chern further teaches where a thickness of a AlGaN layer can be modified to change the threshold voltage such that the first threshold voltage > the second threshold voltage > the third threshold voltage (Paragraph 0017) .
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the second threshold voltage be higher than third threshold voltage by means of having the thickness of the barrier layer in the second gate area be less than a thickness of the barrier layer in the third gate area instead of modifying the Al composition of the barrier layer while maintaining a same thickness because the threshold voltage of a HEMT device is known to be modified by either tuning the Al composition of the barrier or the tuning the thickness of the barrier layer (Chern Paragraph 0017).
Further, the thickness of barrier layer in a HEMT device is a result effective variable (Chern Paragraph 0017 where modifying the thickness of a barrier layer is known to change the amount of spontaneous polarization and piezoelectric polarization between the AlGaN layer and the GaN layer which creates more or less amount of 2-DEG which either lowers or increases a threshold voltage). In In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), the CCPA held that a particular parameter must first be recognized as a result-effective variable, i.e., a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding (MPEP 2144.05).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to optimize the thickness of the barrier layer in the second and third gate areas, respectively, such that the thickness of the barrier layer in the second gate area is less than a thickness of the barrier layer in the third gate area to enable the first threshold voltage > the second threshold voltage > the third threshold voltage because "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP 2144.05).
Regarding claim 3, the combination of Azize and Lavanga teaches all of the elements of the claimed invention as stated above except a P-type layer, wherein the P-type layer is disposed on a plurality of gate areas of the barrier layer comprising the first gate area and the second gate area, and the P-type layer is configured to reduce or exhaust the 2DEG under the plurality of gate areas of the barrier layer.
Fig. 3P of Chern further teaches a P-type layer (Combination of Items 341 and 342), wherein the P-type layer is disposed on a plurality of gate areas of the barrier layer comprising the first gate area and the second gate area, and the P-type layer is configured to reduce or exhaust the 2DEG under the plurality of gate areas of the barrier layer (Paragraph 0073).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a P-type layer, wherein the P-type layer is disposed on a plurality of gate areas of the barrier layer comprising the first gate area and the second gate area, and the P-type layer is configured to reduce or exhaust the 2DEG under the plurality of gate areas of the barrier layer because the p-type layer modulates the dipole concentration in the AlGaN layers to result in changing the 2-DEG concentration in the channel (Chern Paragraph 0073).
Regarding claim 17, the combination of Azize and Lavanga teaches all of the elements of the claimed invention as stated above except where the barrier layer is further provided with a third source area, a third gate area, and a third drain area; the third source area, the third gate area, and the third drain area cooperate with each other to form a third HEMT unit, and the third HEMT unit has a third threshold voltage.
Fig. 3P of Chern further teaches where the barrier layer (Combination of Items 331-333) is further provided with a third source area (Item 383), a third gate area (Item 353), and a third drain area (Item 393); the third source area (Item 383), the third gate area (Item 353), and the third drain area (Item 393) cooperate with each other to form a third HEMT unit, and the third HEMT unit has a third threshold voltage, where the first threshold voltage > the second threshold voltage (Paragraph 0017) and the second threshold voltage> the third threshold voltage (Fig. 2B; Paragraph 0060).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the barrier layer be further provided with a third source area, a third gate area, and a third drain area; the third source area, the third gate area, and the third drain area cooperate with each other to form a third HEMT unit, and the third HEMT unit has a third threshold voltage because this allows for multistage HEMT based drivers which can be used as an integrated circuit to minimize static current (Chern Paragraph 0014).
Azize does not specifically teach where the thickness of the barrier layer in the second gate area is less than a thickness of the barrier layer in the third gate area to enable the first threshold voltage > the second threshold voltage > the third threshold voltage.
However, Chern further teaches where a thickness of a AlGaN layer can be modified to change the threshold voltage such that the first threshold voltage > the second threshold voltage > the third threshold voltage (Paragraph 0017) .
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the second threshold voltage be higher than third threshold voltage by means of having the thickness of the barrier layer in the second gate area be less than a thickness of the barrier layer in the third gate area instead of modifying the Al composition of the barrier layer while maintaining a same thickness because the threshold voltage of a HEMT device is known to be modified by either tuning the Al composition of the barrier or the tuning the thickness of the barrier layer (Chern Paragraph 0017).
Further, the thickness of barrier layer in a HEMT device is a result effective variable (Chern Paragraph 0017 where modifying the thickness of a barrier layer is known to change the amount of spontaneous polarization and piezoelectric polarization between the AlGaN layer and the GaN layer which creates more or less amount of 2-DEG which either lowers or increases a threshold voltage). In In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), the CCPA held that a particular parameter must first be recognized as a result-effective variable, i.e., a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding (MPEP 2144.05).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to optimize the thickness of the barrier layer in the second and third gate areas, respectively, such that the thickness of the barrier layer in the second gate area is less than a thickness of the barrier layer in the third gate area to enable the first threshold voltage > the second threshold voltage > the third threshold voltage because "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP 2144.05).
Regarding claim 18, the combination of Azize and Lavanga teaches all of the elements of the claimed invention as stated above except a P-type layer, wherein the P-type layer is disposed on a plurality of gate areas of the barrier layer comprising the first gate area and the second gate area, and the P-type layer is configured to reduce or exhaust the 2DEG under the plurality of gate areas of the barrier layer.
Fig. 3P of Chern further teaches a P-type layer (Combination of Items 341 and 342), wherein the P-type layer is disposed on a plurality of gate areas of the barrier layer comprising the first gate area and the second gate area, and the P-type layer is configured to reduce or exhaust the 2DEG under the plurality of gate areas of the barrier layer (Paragraph 0073).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a P-type layer, wherein the P-type layer is disposed on a plurality of gate areas of the barrier layer comprising the first gate area and the second gate area, and the P-type layer is configured to reduce or exhaust the 2DEG under the plurality of gate areas of the barrier layer because the p-type layer modulates the dipole concentration in the AlGaN layers to result in changing the 2-DEG concentration in the channel (Chern Paragraph 0073).
Claims 4 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Azize et al. (US 2016/0351564) hereinafter “Azize” in view of Lavanga et al. (US 2018/0151681) hereinafter “Lavanga” and Chern (US 2022/0130989) hereinafter “Chern” and in further view of Cheng (US 2023/0387284) hereinafter “Cheng”.
Regarding claim 4, the combination of Azize, Lavanga and Chern teaches all of the elements of the claimed invention as stated above except where a groove structure is formed in at least one of the plurality of gate areas of the barrier layer; and the P-type layer distributed on the plurality of gate areas is at least partially filled in the groove structure.
Fig. 1 of Cheng teaches a HEMT device comprising a groove structure (Item 3) is formed in a gate area (Item 5) of a barrier layer (Item 202); and a P-type layer (Item 4) distributed on the gate area (Item 5) is at least partially filled in the groove structure (Item 3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a groove structure is formed in at least one of the plurality of gate areas of the barrier layer; and the P-type layer distributed on the plurality of gate areas is at least partially filled in the groove structure because the presence of a groove in the barrier layer allows a gap between a p-type layer and a 2DEG to be smaller which improves the controllability of a gate electrode (Cheng Paragraph 0004).
Regarding claim 19, the combination of Azize, Lavanga and Chern teaches all of the elements of the claimed invention as stated above except where a groove structure is formed in at least one of the plurality of gate areas of the barrier layer; and the P-type layer distributed on the plurality of gate areas is at least partially filled in the groove structure.
Fig. 1 of Cheng teaches a HEMT device comprising a groove structure (Item 3) is formed in a gate area (Item 5) of a barrier layer (Item 202); and a P-type layer (Item 4) distributed on the gate area (Item 5) is at least partially filled in the groove structure (Item 3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a groove structure is formed in at least one of the plurality of gate areas of the barrier layer; and the P-type layer distributed on the plurality of gate areas is at least partially filled in the groove structure because the presence of a groove in the barrier layer allows a gap between a p-type layer and a 2DEG to be smaller which improves the controllability of a gate electrode (Cheng Paragraph 0004).
Alternately, Claims 6, 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Azize et al. (US 2016/0351564) hereinafter “Azize” in view of Lavanga et al. (US 2018/0151681) hereinafter “Lavanga” and Cheng (US 2023/0387284) hereinafter “Cheng” and in further view of Sun et al. (US 2021/0005739) hereinafter “Sun”.
Regarding claim 6, the combination of Azize, Lavanga and Cheng teaches all of the elements of the claimed invention as stated above except the GaN-based HEMT structure further comprises at least one insertion layer, and the at least one insertion layer is distributed between the-two barrier sub-layers.
Fig. 1 of Cheng teaches a HEMT device comprising a groove structure (Item 3) is formed in a gate area (Item 5) of a barrier layer (Item 202); and a P-type layer (Item 4) distributed on the gate area (Item 5) is at least partially filled in the groove structure (Item 3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a groove structure formed in at least one of the plurality of gate areas of the barrier layer because the presence of a groove in the barrier layer allows a gap between a p-type layer and a 2DEG to be smaller which improves the controllability of a gate electrode (Cheng Paragraph 0004).
Fig. 13 of Sun teaches where an insertion layer (Item “AlN insertion layer”) is present between barrier sub-layers (Items “low Al component barrier layer” and “high Al component barrier layer”) to form a barrier layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include at least one insertion layer distributed between two barrier sub-layers because this structure is known to be used in a high precision recessed gate preparation (Sun Paragraph 0019).
Regarding claim 7, the combination of Azize, Lavanga, Cheng and Sun teaches all of the elements of the claimed invention as stated above.
Azize does not teach where the groove structure is formed in at least one of the first gate area and the second gate area of the barrier layer; the notch of the groove structure is distributed on the surface of the barrier layer; and the groove bottom is distributed in the at least one insertion layer or an interface of the at least one insertion layer and an adjacent barrier sub-layer.
However, Cheng teaches where the depth of a groove is a result effective variable (Cheng Paragraph 0004 where a reduction in distance between a p-type gate and a 2DEG [which is in direct proportion to the depth of the groove] is known to directly impact the controllability of gate for the 2DEG).In In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), the CCPA held that a particular parameter must first be recognized as a result-effective variable, i.e., a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding (MPEP 2144.05).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to optimize the depth of the groove such that the groove structure is formed in at least one of the first gate area and the second gate area of the barrier layer; the notch of the groove structure is distributed on the surface of the barrier layer; and the groove bottom is distributed in the at least one insertion layer or an interface of the at least one insertion layer and an adjacent barrier sub-layer because "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (MPEP 2144.05).
Regarding claim 16, the combination of Azize and Lavanga teaches all of the elements of the claimed invention as stated above except sequentially growing a plurality of barrier sub-layers on the channel layer and growing an insertion layer between at least two of the plurality of barrier sub-layers to form the barrier layer.
Fig. 13 of Sun teaches where an insertion layer (Item “AlN insertion layer”) is present between barrier sub-layers (Items “low Al component barrier layer” and “high Al component barrier layer”) to form a barrier layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to sequentially grow a plurality of barrier sub-layers on the channel layer and grow an insertion layer between at least two of the plurality of barrier sub-layers to form the barrier layer because this structure is known to be used in a high precision recessed gate preparation (Sun Paragraph 0019).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Azize et al. (US 2016/0351564) hereinafter “Azize” in view of Lavanga et al. (US 2018/0151681) hereinafter “Lavanga” and in further view of Cheng (US 2023/0387284) hereinafter “Cheng”.
Regarding claim 8, the combination of Azize and Lavanga teaches all of the elements of the claimed invention as stated above.
Fig. 8 of Azize teaches a groove in a barrier layer, where an inner wall of the groove structure is at least coated with continuous gate dielectric layers (Item 714), and each of the continuous gate dielectric layers (Item 714) is configured to separate a gate (Item 712) and the groove structure.
Azize does not teach where a groove structure is formed in at least one of the first gate area and the second gate area of the barrier layer; a notch of the groove structure is distributed on a surface of the barrier layer, and a groove bottom is distributed on a surface of the channel layer.
Fig. 1 of Cheng teaches a groove structure (Item 3) is formed in a gate area of a barrier layer (Item 202); a notch of the groove structure is distributed on a surface of the barrier layer (Item 202), and a groove (Item 3) bottom is distributed on a surface of the channel layer (Item 201).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a groove structure is formed in at least one of the first gate area and the second gate area of the barrier layer; a notch of the groove structure is distributed on a surface of the barrier layer, and a groove bottom is distributed on a surface of the channel layer because the presence of a groove allows a gap between a p-type layer and a 2DEG to be smaller which improves the controllability of a gate electrode (Cheng Paragraph 0004).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Azize et al. (US 2016/0351564) hereinafter “Azize” in view of Lavanga et al. (US 2018/0151681) hereinafter “Lavanga” and in further view of Cheng (US 2023/0387284) hereinafter “Cheng”.
Regarding claim 9, the combination of Azize and Lavanga teaches all of the elements of the claimed invention as stated above.
Fig. 8 of Azize further teaches where a transition layer (Item 604), the channel layer (Item 606), a band-offset layer (Item 630) and the barrier layer (Item 608) are sequentially grown on a substrate (Item 602).
Azize does not specifically teach a withstand voltage layer between the transition layer and the channel layer.
Fig. 6 of Chen teaches a withstand voltage layer (Item 106) between a transition layer (Item 104) and a channel layer (Item 108).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a withstand voltage layer between the transition layer and the channel layer because the withstand voltage layer forms an isolation structure at the bottom of the channel layer (Chen Paragraph 0029).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Azize et al. (US 2016/0351564) hereinafter “Azize” in view of Lavanga et al. (US 2018/0151681) hereinafter “Lavanga” and in further view of Sun et al. (US 2021/0005739) hereinafter “Sun”.
Regarding claim 12, the combination of Azize and Lavanga teaches all of the elements of the claimed invention as stated above except sequentially growing a plurality of barrier sub-layers on the channel layer and growing an insertion layer between at least two of the plurality of barrier sub-layers to form the barrier layer.
Fig. 13 of Sun teaches where an insertion layer (Item “AlN insertion layer”) is present between barrier sub-layers (Items “low Al component barrier layer” and “high Al component barrier layer”) to form a barrier layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to sequentially grow a plurality of barrier sub-layers on the channel layer and grow an insertion layer between at least two of the plurality of barrier sub-layers to form the barrier layer because this structure is known to be used in a high precision recessed gate preparation (Sun Paragraph 0019).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Azize et al. (US 2016/0351564) hereinafter “Azize” in view of Lavanga et al. (US 2018/0151681) hereinafter “Lavanga”, Chern (US 2022/0130989) hereinafter “Chern” and Cheng (US 2023/0387284) hereinafter “Cheng” and in further view of Tai (US 2023/0420498) hereinafter “Tai”.
Regarding claim 13, the combination of Azize and Lavanga teaches all of the elements of the claimed invention as stated above except where growing a P- type layer on the barrier layer to fill a local area of the P-type layer in the groove structure; and then removing a rest area of the P-type layer other than the gate areas by etching to reduce or exhaust 2DEG under the barrier sub-layers of the barrier layer.
Chern further teaches growing a P-type layer on the barrier layer to fill a local area of the P-type layer in the groove structure; and then removing a rest area of the P-type layer other than the gate areas by etching to reduce or exhaust 2DEG under the barrier sub-layers of the barrier layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to grow a P- type layer on the barrier layer to fill a local area of the P-type layer in the groove structure; and then remove a rest area of the P-type layer other than the gate areas by etching to reduce or exhaust 2DEG under the barrier sub-layers of the barrier layer because the p-type layer modulates the dipole concentration in the AlGaN layers to result in changing the 2-DEG concentration in the channel (Chern Paragraph 0073).
Cheng further teaches growing a P-type layer on the barrier layer to fill a local area of the P-type layer in the groove structure; and then removing a rest area of the P-type layer to reduce or exhaust 2DEG under the barrier layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to grow a P-type layer on the barrier layer to fill a local area of the P-type layer in the groove structure; and then removing a rest area of the P-type layer by etching to reduce or exhaust 2DEG under the barrier sub-layers of the barrier layer because the presence of a groove in the barrier layer allows a gap between a p-type layer and a 2DEG to be smaller which improves the controllability of a gate electrode (Cheng Paragraph 0004).
Azize does not teach removing a rest area of the P-type layer other than the gate areas.
Tai teaches where the outermost sides of the p-type layer (Item 25) are coincident with the outermost sides of the gate layer (Item 26) such that when the p-type layer is formed, portions of the p-type layer (Item 25) outside the orthographic projection of the gate layer (Item 26) on a substrate (Item 21) are removed.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to remove a rest area of the p-type layer other than the gate areas because this forms a p-type layer that extends laterally the same width as a gate layer (Tai Paragraph 0043).
Response to Arguments
Applicant’s arguments, see Applicant’s Remarks/Arguments, filed 05/14/2026, with respect to the rejection(s) of claim(s) 1 and 10 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lavanga.
Conclusion
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/ERIC K ASHBAHIAN/ Primary Examiner, Art Unit 2891
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