DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Examiner acknowledges the amendments made to claims 1,8 and 10. Claim 2 has been cancelled. No new claims have been added.
Response to Arguments
Applicant's arguments filed 08/05/2026 have been fully considered but they are not persuasive.
Applicant states that the Office Action has not established that Hirose discloses a current blocking region that includes a photonic crystal layer as required by claim 1.
Hirose shows the electrode [23] and contact layer [14] structure with a window [14a], the claimed application discloses that the current blocking region is a region in which current is less likely to flow than in the light emitting region. The electrode structure of the top electrodes [23] of Hirose to the bottom electrode [22] of Hirose show the current more likely to flow within the middle region shown by [14a] between top electrodes [23] than in the regions outside of [14] in Fig. 25. This is further supported in paragraph [0179] of Hirose which discloses that the structure [21] of Hirose causes current to not pass through, therefore reinforcing that current is more likely to flow in the region shown by [14a] between electrodes [23] in Fig. 25 of Hirose compared to the regions outside of [14] in Fig. 25.
Applicant notes that Hirose fails to disclose the recited thyristor structure and therefore does not anticipate amended claim 1. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). In the instant case, the Mihashi reference is used to anticipate the limitation of the thyristor structure.
Claim Rejections - 35 USC § 112
The previous rejection of claim 8 under 35 U.S.C. § 112(a) has been withdrawn in light of the amendments made to claim 8.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1,3,4,6,7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Hirose et al. (hereinafter Hirose) (US 20200373739 A1) in view of Mihashi (EP 0527547 A2).
Regarding claim 1, Hirose discloses in Fig. 25,
A photonic crystal surface-emitting laser [1C] (Para. [0172]) comprising:
a light emitting region [region shown by space 14a] (Para. [0175]) from which light is emitted in a direction crossing an in-plane direction (Para. [0175]); and
a current blocking region [regions outside of 14 Fig. 25] (Para. [0175]) in which current is less likely to flow than in the light emitting region [14a] (Paras. [0175,1076]), the current blocking region being adjacent to the light emitting region in the in-plane direction [see Fig. 25],
wherein the light emitting region and the current blocking region each include a photonic crystal layer [15] (Para. [0086]),
the photonic crystal layer [15] has a first region [15a] (Para. [0086]) and second regions [15b] (Para. [0086]) periodically arranged in the in-plane direction in the first region (Para. [0086]),
a refractive index of each of the second regions [15b] is different from a refractive index of the first region [15a] (Para. [0086]),
the light emitting region includes a first semiconductor layer [10] having a first conductivity type [n-type] (Para. [0178]), an active layer [12] (Para. [0173]) having an optical gain (Para. [0088]), and a second semiconductor layer [13] (Para. [0178]) having a second conductivity type [p-type] (Para. [0178]),
the first semiconductor layer [10], the active layer [12], and the second semiconductor layer [13] are sequentially stacked on top of one another in an emission direction of the light [Z-direction Fig. 25] (Para. [0172]),
wherein the current blocking region [regions outside of 14 Fig. 25] includes the first semiconductor layer [10], a third semiconductor layer [21 p-type layer in pn junction] (Para. [0179]) having the second conductivity type [21 p-type layer in pn junction] (Para. [0179]) a fourth semiconductor layer [21 n-type layer in pn junction] (Para. [0179]) having the first conductivity type [n-type] (Para. [0179]), and a fifth semiconductor layer [13] having the second conductivity type (Para. [0178]), and
the first semiconductor layer [10], the third semiconductor layer [21 p-type layer in pn junction] (Para. [0179]), the fourth semiconductor layer [21 n-type layer in pn junction] (Para. [0179]), and the fifth semiconductor layer [13] are sequentially stacked on top of one another in the emission direction of the light [Z-direction Fig. 25] (Para. [0172]).
Examiner notes the interpretation of the cladding layer [13] of Hirose as both the second semiconductor layer and the fifth semiconductor layer as shown with the interpretation of layer [22] of claimed application as both the second semiconductor layer and the fifth semiconductor layer.
Hirose fails to disclose,
the first semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer are sequentially stacked on top of one another in the emission direction of the light to form a thyristor.
Mihashi discloses in Fig. 1,
a four layer n-p-n-p thyristor structure (Col. 2, line 65- Col. 3, line 12)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the thyristor structure of Mihashi in the device of Hirose for the purpose of suppressing leakage of current flow. (Mihashi Col. 2, line 65- Col. 3, line 12)
Regarding claim 3, Hirose in view of Mihashi as applied to claim 1 above further discloses in Hirose Fig. 25,
wherein the current blocking region [regions outside of 14 Fig. 25] (Para. [0175]) includes a sixth semiconductor layer [region of 13 subjected to ion implantation] (Para. [0179]), and
the sixth semiconductor layer is insulated (Para. [0179]).
Regarding claim 4, Hirose in view of Mihashi as applied to claim 1 above further discloses in Hirose Fig. 25,
wherein the active layer [12] is included in the light emitting region [region shown by space 14a] and the current blocking region [regions outside of 14 Fig. 25] (Para. [0176]).
Regarding claim 6, Hirose in view of Mihashi as applied to claim 1 above further discloses in Hirose Fig. 25,
wherein the current blocking region [regions outside of 14 Fig. 25] (Para. [0175]) surrounds a whole periphery of the light emitting region [region shown by space 14a Fig. 25] (Para. [0175]) in the in-plane direction.
Regarding claim 7, Hirose in view of Mihashi as applied to claim 1 above further discloses in Hirose Fig. 25,
wherein the light emitting region includes an eighth semiconductor layer [14] (Para. [0174]) stacked on the second semiconductor layer [13] (Para. [0174]) and having the second conductivity type (Para. [0178]) and
at least a portion of the current blocking region [regions outside of 14 Fig. 25] is exposed from the eighth semiconductor layer [14] (Para. [0174]).
Regarding claim 10, Hirose discloses in Fig. 25,
A method for manufacturing a photonic crystal surface-emitting laser [1C] (Para. [0172]), the method comprising:
forming a light emitting region [region shown by space 14a] (Para. [0175]) from which light is emitted in a direction crossing an in-plane direction (Para. [0175]); and
forming a current blocking region [regions outside of 14 Fig. 25] (Para. [0175]) in which current is less likely to flow than in the light emitting region (Paras. [0175,1076]), the current blocking region being adjacent to the light emitting region in the in-plane direction [see Fig. 25],
wherein the forming the light emitting region and the forming the current blocking region each include providing a photonic crystal layer [15] (Para. [0086]),
the photonic crystal layer [15] has a first region [15a] (Para. [0086]) and second regions[15b] (Para. [0086]) periodically arranged in the in-plane direction in the first region (Para. [0086]),
a refractive index of each of the second regions [15b] is different from a refractive index of the first region [15a] (Para. [0086]),
the forming the light emitting region includes sequentially stacking a first semiconductor layer [10] (Para. [0172]) having a first conductivity type [n-type] (Para. [0178]), an active layer [12] (Para. [0173]) having an optical gain (Para. [0088]), and a second semiconductor layer [13] (Para. [0178]) having a second conductivity type [p-type] (Para. [0178]) on top of one another (Para. [0172]).
the current blocking region [regions outside of 14 Fig. 25] includes the first semiconductor layer [10], a third semiconductor layer [21 p-type layer in pn junction] (Para. [0179]) having the second conductivity type [21 p-type layer in pn junction] (Para. [0179]) a fourth semiconductor layer [21 n-type layer in pn junction] (Para. [0179]) having the first conductivity type [n-type] (Para. [0179]), and a fifth semiconductor layer [13] having the second conductivity type (Para. [0178]), and
the first semiconductor layer [10], the third semiconductor layer [21 p-type layer in pn junction] (Para. [0179]), the fourth semiconductor layer [21 n-type layer in pn junction] (Para. [0179]), and the fifth semiconductor layer [13] are sequentially stacked on top of one another in the emission direction of the light [Z-direction Fig. 25] (Para. [0172]).
Examiner notes the interpretation of the cladding layer [13] of Hirose as both the second semiconductor layer and the fifth semiconductor layer as shown with the interpretation of layer [22] of claimed application as both the second semiconductor layer and the fifth semiconductor layer.
Hirose fails to disclose,
the first semiconductor layer, the third semiconductor layer, the fourth semiconductor layer, and the fifth semiconductor layer are sequentially stacked on top of one another in the emission direction of the light to form a thyristor.
Mihashi discloses in Fig. 1,
a four layer n-p-n-p thyristor structure (Col. 2, line 65- Col. 3, line 12)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the thyristor structure of Mihashi in the device of Hirose for the purpose of suppressing leakage of current flow. (Mihashi (Col. 2, line 65- Col. 3, line 12)
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hirose in view of Mihashi as applied to claim 1 above and further in view of Lin et al. (hereinafter Lin) (US 6674778 B1).
Regarding claim 5, Hirose in view of Mihashi discloses the device outlined in the rejection of claim 1 above but fails to disclose,
wherein the current blocking region includes a seventh semiconductor layer, and
the seventh semiconductor layer is adjacent to the active layer in the in-plane direction and has a bandgap greater than an energy of the light.
Lin discloses in Fig. 3A,
A semiconductor layer [157] (Col. 4, lines 28-35) adjacent to an active layer [156] (Col. 4, lines 28-35) in an in-plane direction and has a bandgap greater than an energy of a light (Col. 4, lines 28-35).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the apertured active layer structure shown in Lin in the modified structure of Hirose for the purpose of preventing absorption of light in the active layer. (Lin Col. 4, lines 28-35)
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hirose in view of Mihashi as applied to claim 1 above and further in view of Kitatani et al. (hereinafter Kitatani) (JP 2007207804 A).
Examiner notes an attached machine translation will be used for the claim mapping of Kitatani, see PTO-892 form.
Regarding claim 8, Hirose in view of Mihashi discloses the device outlined in the rejection of claim 7 above and further discloses in Hirose Fig. 25,
further comprising:
a first electrode [23] (Para. [0174]) disposed on an upper surface of the eighth semiconductor layer [14] (Para. [0174]) and in the light emitting region (Para. [0174]); and
a second electrode [22] (Para. [0174]) disposed on a surface of the first semiconductor layer [10] (Para. [0174]), the surface being located on a side opposite to a side on which the active layer [12] (Para. [0173]) is disposed [bottom surface of 10 Fig. 25] (Para. [0174]),
Hirose in view of Mihashi fails to disclose,
wherein the first electrode has a ring-like shape in the in-plane direction, and
the eighth semiconductor layer is exposed at a portion of the light emitting region, the portion being surrounded by the first electrode.
Kitatani discloses in Fig. 3A,
An electrode [310] (Para. [0021]) with a ring-like shape (Para. [0021]) surrounding a contact layer [311] (Para. [0021]) in a light emitting region [space between 310]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the ring shape electrode surrounding an exposed contact layer as shown in Kitatani in the device of Hirose for the purpose of allowing emission of light without interfering with the electrode.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hirose in view of Mihashi as applied to claim 1 above and further in view of Yoshimoto et al. (hereinafter Yoshimoto) (US 20090047751A1)
Regarding claim 9, Hirose in view of Mihashi discloses the device outlined in the rejection of claim 1 above and further discloses in Hirose Fig. 25,
wherein the first semiconductor layer [10], the photonic crystal layer [15], the active layer [12], and the second semiconductor layer are sequentially stacked on top of one another [Fig. 25] (Para. (Para. [0172]),
the photonic crystal layer [15] has the first conductivity type [n-type] (Para. [0178]),
the second regions [15b] of the photonic crystal layer [15] are air holes (Para. [0134]), and
Hirose in view of Mihashi fails to disclose,
the photonic crystal surface-emitting laser includes a ninth semiconductor layer provided between the photonic crystal layer and the active layer and having the first conductivity type,
an end portion of each of the air holes on the active layer side is covered with the ninth semiconductor layer.
Yoshimoto discloses in Fig. 2(c),
an n-type semiconductor layer [23] (Para. [0031]) between a photonic crystal layer [17a] (Para. [0032]) and an active layer [27] (Para. [0033]),
where an end portion of air holes [25] (Para. [0031]) on an active layer [27] side is covered with the n-type semiconductor layer [23]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement an n-type semiconductor layer covering the air holes of the photonic crystal structure of Hirose as shown in Yoshimoto for the purpose of closing the air openings to form voids. (Yoshimoto Para. [0031])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Examiner notes (US 8379686 B2) which discloses a photonic crystal laser with a light emitting region and current blocking region. See PTO-892 form.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNTER J NELSON whose telephone number is (571)270-5318. The examiner can normally be reached Mon-Fri. 8:30am-5:00 ET.
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/H.J.N./Examiner, Art Unit 2828 /TOD T VAN ROY/Primary Examiner, Art Unit 2828
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