Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant's election with traverse of Species E, corresponding to claims 1-38, readable on Figure 5 in the reply filed on 27 April 2026 is acknowledged. The traversal is on the ground(s) that FIGS. 1-6 do not correspond to separate patentably distinct species, but rather to a single related system and device architecture, with different drawings showing the system, different bitstream-communication paths for that system, a portion of the multi-instrument device, and a sub-portion of that same device. This is found persuasive, and hence, the Requirement for Restriction/Election mailed on 26 February 2026 has been withdrawn.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 14 September 2023, 15 October 2024, 20 November 2024, 12 September 2025, 21 November 2025 and 26 May 2026 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 14-27 and 33-38 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shaddock et al (WO 2020/046645 A1).
Shaddock et al disclose the following claimed features:
Regarding claim 1, a system (Figures 1-4), comprising: a multi-instrument device (110) including: a static reconfigurable portion (paragraphs [0024], [0025], [0059]), a plurality of dynamic reconfigurable portions (Figure 4, element 408), each of the plurality of dynamic reconfigurable portions (408) configured as a test and measurement device (paragraphs [0024], [0069], and a controller (Figure 1, element 102), coupled with the static reconfigurable portion and the plurality of dynamic reconfigurable portions, configured to: process at least one bitstream to reconfigure at least one of the plurality of dynamic reconfigurable portions as a test and measurement device (paragraph [0057]); and a server (106) including: memory (140) configured to store the at least one bitstream, and at least one processor configured to: receive a request from the multi-instrument device for providing the at least one bitstream (Figure 2, elements 210, 212, 214; paragraph [0044]); and responsive to the request, retrieve the at least one bitstream from the memory and transmit at least a portion of the at least one bitstream to the multi-instrument device (Figure 2, elements 210, 212, 214; paragraph [0044]).
Regarding claim 2, wherein the multi-instrument device (110) is configured to: receive a request from a user device to load a desired test and measurement device, and responsive to the request from the user device, communicate the request to the server for providing the at least one bitstream corresponding to the desired test and measurement device (Figure 2, elements 210, 212, 214; paragraph [0044]).
Regarding claim 3, wherein the request for providing the at least one bitstream is a first request, wherein the at least one bitstream is a first at least one bitstream, wherein the at least one processor is configured to: receive a second request for providing a second at least one bitstream, and responsive to the second request, retrieve a second at least one bitstream from the memory and transmit the second at least one bitstream to the multi-instrument device; and wherein the controller is configured to: based on the second at least one bitstream, reconfigure at least one of the plurality of dynamic reconfigurable portions from one test and measurement device to another test and measurement device (paragraphs [0059], [0063], [0064]).
Regarding claim 4, wherein the multi-instrument device further includes: a data interface configured to output a data stream associated with each of the plurality of dynamic reconfigurable portions to a separate physical output port (paragraphs [0040], [0059]).
Regarding claim 5, wherein the multi-instrument device further includes: a data interface configured to output a data stream associated with each of the plurality of dynamic reconfigurable portions to at least one of a serial data port or a network port (paragraphs [0040], [0059]).
Regarding claim 6, wherein the static reconfigurable portion includes at least one data bus configured to carry signals from at least one dynamic reconfigurable portion of the plurality of dynamic reconfigurable portions to at least one another dynamic reconfigurable portion of the plurality of dynamic reconfigurable portions (paragraphs [0059], [0062]).
Regarding claim 7, wherein the static reconfigurable portion includes at least one multiplexer having inputs coupled with outputs of the plurality of dynamic reconfigurable portions, and at least one output coupled with an input of at least one dynamic reconfigurable portion of the plurality of dynamic reconfigurable portions, wherein the controller is configured to control the at least one multiplexer to allow at least one of the outputs of the plurality of dynamic reconfigurable portions to be provided to the input of the at least one dynamic reconfigurable portion of the plurality of dynamic reconfigurable portions (paragraphs [0051], [0059], [0069]).
Regarding claim 8, wherein at least one output of the plurality of dynamic reconfigurable portions provides a data stream representing a quantized near real-time analog signal (paragraphs [0031], [0032], [0038]).
Regarding claim 14, wherein at least one dynamic reconfigurable portion of the plurality of dynamic reconfigurable portions includes: at least one control register coupled with the controller via a control bus, and at least one memory unit coupled with the controller via the control bus, wherein the at least one control register and the at least one memory unit store configuration data received from the controller and wherein the at least one memory unit is larger in size than the at least one control register (paragraphs [0051], [0058], [0059], [0062]).
Regarding claim 15, wherein at least one dynamic reconfigurable portion of the plurality of dynamic reconfigurable portions includes: at least one multiplexer, at least one input of which is coupled with data stream outputs of one or more other dynamic reconfigurable portions of the plurality of dynamic reconfigurable portions, and at least one processor, at least one input of which is coupled with at least output of the at least one multiplexer (paragraphs [0051], [0059], [0069]).
Regarding claim 16, the user device communicably coupled with the multi-instrument device and communicably coupled with the server, the user device configured to send a request to the server for providing another at least one bitstream, receive a transmission from the server including the another at least one bitstream, and transmit the another at least one bitstream to the multi-instrument device (Figure 2, elements 210, 212, 214; paragraph [0044]).
Regarding claim 17, wherein the static reconfigurable portion includes at least one analog-to-digital converter (ADC) and at least one digital-to-analog converter (DAC), wherein each of the plurality of dynamic reconfigurable portions is selectively coupled with the at least one ADC and selectively coupled with the at least one DAC (paragraph [0036]).
Regarding claim 18, a multi-instrument device (Figures 1-4, element 110), comprising: a static reconfigurable portion (paragraphs [0024], [0025], [0059]); a plurality of dynamic reconfigurable portions (Figure 4, element 408), at least one of the plurality of dynamic reconfigurable portions (408) configured as a test and measurement device (paragraphs [0024], [0069]; and a controller (Figure 1, element 102), coupled with the static reconfigurable portion and the plurality of dynamic reconfigurable portions, configured to reconfigure at least one of the plurality of dynamic reconfigurable portions as a test and measurement device based on at least one bitstream (paragraph [0057]), and reconfigure the static reconfigurable portion to provide data streams generated by each of the plurality of dynamic reconfigurable portions at a plurality of output ports, wherein the controller (102) is further configured to receive instructions to reconfigure at least one of the plurality of dynamic reconfigurable portions from a user device, and responsive to receiving instruction, request a server to provide the at least one bitstream (Figure 2, elements 210, 212, 214; paragraph [0044]).
Regarding claim 19, wherein the plurality of output ports include a plurality of physical output ports, and wherein each physical output port of the plurality of physical output ports is selectively coupled to any one of the plurality of dynamic reconfigurable portions (paragraphs [0040], [0059]).
Regarding claim 20, further comprising: a plurality of input ports; and a plurality of analog-to-digital converters (ADCs) coupled with the plurality of input ports, wherein the static reconfigurable portion includes at least one input bus coupled with the plurality of ADCs and configured to selectively provide digital signals from each of the plurality of ADCs to each of the plurality of dynamic reconfigurable portions (paragraphs [0036], [0044]).
Regarding claim 21, further comprising: a plurality of output ports; and a plurality of digital-to-analog converters (DACs) coupled with the plurality of output ports, wherein the static reconfigurable portion includes at least one output bus coupled with the plurality of DACs and configured to selectively provide output signals from each of the plurality of dynamic reconfigurable portions to each of the plurality of DACs (paragraphs [0036], [0044]).
Regarding claim 22, wherein the at least one bitstream is a first at least one bitstream, wherein the at least one controller is configured to: receive a second at least one bitstream over a data interface, and reconfigure the at least one of the plurality of dynamic reconfigurable portions from one test and measurement device to another test and measurement device based on the second at least one bitstream (paragraphs [0040], [0059]).
Regarding claim 23, further comprising: an output interface configured to output a data stream associated with each of the plurality of dynamic reconfigurable portions to a separate physical output port (paragraphs [0040], [0059]).
Regarding claim 24, further comprising: a network interface configured to output a data stream associated with each of the plurality of dynamic reconfigurable portions to at least one of a serial data port or a network port (paragraphs [0040], [0059]).
Regarding claim 25, wherein the static reconfigurable portion includes at least one data bus configured to carry signals from at least one dynamic reconfigurable portion of the plurality of dynamic reconfigurable portions to at least one another dynamic reconfigurable portion of the plurality of dynamic reconfigurable portions (paragraphs [0059], [0062]).
Regarding claim 26, wherein the static reconfigurable portion includes at least one multiplexer having inputs coupled with outputs of the plurality of dynamic reconfigurable portions, and at least one output coupled with an input of at least one dynamic reconfigurable portion of the plurality of dynamic reconfigurable portions, wherein the controller is configured to control the at least one multiplexer to allow at least one of the outputs of the plurality of dynamic reconfigurable portions to be provided to the input of the at least one dynamic reconfigurable portion of the plurality of dynamic reconfigurable portions (paragraphs [0051], [0059], [0069]).
Regarding claim 27, wherein at least one output of the plurality of dynamic reconfigurable portions provides a data stream representing a quantized near real-time analog signal (paragraphs [0031], [0032], [0038]).
Regarding claim 33, wherein the at least one dynamic reconfigurable portion of the plurality of dynamic reconfigurable portions includes: at least one control register coupled with the controller via a control bus, and at least one memory unit coupled with the controller via the control bus, wherein the at least one control register and the at least one memory unit store configuration data received from the controller and wherein the at least one memory unit is larger in size than the at least one control register (paragraphs [0051], [0058], [0059], [0062]).
Regarding claim 34, wherein the at least one dynamic reconfigurable portion of the plurality of dynamic reconfigurable portions includes: at least one multiplexer, at least one input of which is coupled with data stream outputs of one or more other dynamic reconfigurable portions of the plurality of dynamic reconfigurable portions, and at least one processor, at least one input of which is coupled with at least output of the at least one multiplexer (paragraphs [0051], [0059], [0069]).
Regarding claim 35, further comprising: a memory interface coupled with a memory storage storing the least one bitstream received from the server, wherein the controller is configured to access the at least one bitstream from the memory storage over the memory interface (paragraph [0071]).
Regarding claim 36, wherein the controller is configured to: receive additional instructions for reconfiguring the at least one of the plurality of dynamic reconfigurable portions from the user device via an interface, and responsive to the receipt of the additional instructions, access another at least on bitstream from the memory storage over the memory interface (paragraphs [0079], [0080]).
Regarding claim 37, further comprising: at least one digital input port, wherein the static reconfigurable portion includes at least one input bus coupled with the at least one digital input port and configured to selectively provide digital signals from each of the at least one digital input port to each of the plurality of dynamic reconfigurable portions (paragraphs [0051], [0059], [0069]).
Regarding claim 38, further comprising: at least one digital output port, wherein the static reconfigurable portion includes at least one output bus coupled with the at least one digital output and configured to selectively provide output signals from each of the plurality of dynamic reconfigurable portions to each of the at least one digital output port (paragraphs [0051], [0059], [0069]).
Allowable Subject Matter
Claims 9-13 and 28-32 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowance of claims 9-13 and 28-32 is the inclusion of the limitations of the system/the multi-instrument device that includes the static reconfigurable portion that has: at least one channel buffer coupled with at least one dynamic reconfigurable portion of the plurality of dynamic reconfigurable portions, each of the at least one channel buffer coupled with a channel output of a corresponding one of the plurality of dynamic reconfigurable portions, the at least one channel buffer configured to buffer a channel data stream output by the channel output and provide a buffered channel data stream to a memory of the multi-instrument device. It is these limitations found in the claims, as they are claimed in the combination of, that has not been found, taught or suggested by the prior art of record which makes these claims allowable over the prior art.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Shah et al (US 11,983,140) disclose a reconfigurable data processor that includes a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Purandare et al (US 11,907,828) disclose a field programmable gate array (FPGA) that determines different precision configurations of the trained DNN. A precision configuration of the precision configurations may define second number representations of a subset of the set of parameters. For each precision configuration of the determined precision configurations a bitstream file may be provided. The bitstream files may be stored so that the FPGA may be programmed using one of the stored bitstream files for inference of the trained DNN. Seshadri (US 11,836,171) discloses a system and method for processing queries including splitting a query into sub-queries, mapping the sub-queries to respective sets of filter properties, mapping the sets of filter properties to respective reconfiguration bitstreams, configuring a plurality of filters within a field programmable gate array (FPGA) according to respective ones of the respective reconfiguration bitstreams, wherein each filter is formed in a respective reconfigurable region of the FPGA.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AN H DO whose telephone number is (571)272-2143. The examiner can normally be reached on M-F 7:00am-4:00pm.
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/AN H DO/Primary Examiner, Art Unit 2853
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