DETAILED ACTION
Response to Arguments
Applicant’s arguments, filed 03/13/2026, with respect to claims 18 and 23-25 have been fully considered and are persuasive. The 35 U.S.C 112(b) rejection of claims 18 and 23-25 has been withdrawn.
Applicant’s arguments in regard to claims 1 and 17 filed 03/13/2026 have been fully considered and are persuasive. However, a new rejection has been made in view of Lee et al. (US 2022/0148983 A1; hereinafter “Lee”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 12-14, 17-18, 20, and 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Kim ( KR 20170132495 A) as applied to claim 1 above, and further in view of Lee et al. (US 2022/0148983 A1; hereinafter “Lee”).
In regard to claim 1, Kim teaches a system in package (SiP) module (an image sensor module 500) (Fig. 4 and paragraph 23), comprising:
a substrate (a multilayer substrate 501) (Fig. 3 and paragraph 24);
an image sensor (a first image sensor chip 510) being disposed on one surface of the substrate (the first image sensor chip 510 is shown on the multilayer substrate 501 in Fig. 3) (Fig. 3 and paragraph 24); and
a serializer (a digital circuit chip 530) being embedded inside the substrate (the digital circuit chip 530 may be disposed inside the multi-layer substrate 501) (Fig. 3 and paragraph 37),
wherein the substrate includes a via hole (a first via VIA1) that penetrates through the substrate in order to electrically connect the image sensor and the serializer (the first wiring EL1 is disposed inside the multilayer substrate 501 and connects the digital circuit chip 530 and the first via VIA1) (Fig. 1 and paragraph 41),
wherein the serializer is disposed to be overlapped with the image sensor in an optical axis (the digital circuit chip 530 is shown overlapped with the first image sensor chip 510 in the optical direction in Fig. 2 and Fig. 9)
wherein the substrate comprises first to third regions defined along the optical axis direction (a first layer LY1, a second layer LY2, and a third layer LY3 form the first to third regions) (Fig. 3 and paragraph 47),
wherein the substrate comprises the first region being disposed with the image sensor (a first layer LY1 is shown disposed with the first image sensor chip 510 in Fig. 3), the second region being disposed to surround the serializer (the second layer LY2 is shown surrounding the digital circuit chip 530 in Fig. 3), and the third region being disposed below the serializer (the third layer LY3 is shown below the digital circuit chip 530 in Fig. 3),
wherein the first region and the third region of the substrate do not overlap the serializer in a direction perpendicular to the optical axis (the first layer LY1, the second layer LY2, and the third layer LY3 are shown not overlapping in a direction perpendicular to the optical axis in Fig. 3), and
However, Kim doesn’t explicitly teach wherein a resistor is disposed to face an outer side surface of the serializer.
Lee teaches a system in package (SiP) module (SIP 168) (Fig. 5f and paragraph 35), wherein a resistor is disposed to face an outer side surface of a serializer (electrical components 130a-130d can include a resistor which faces the outer bottom side surface of a Bi-directional multiplexer/switch 170 disposed on substrate 120) (Fig. 5f and paragraphs 27 and 36).
It would’ve been obvious to one skilled in the art to combine the teachings of Kim with the teachings of Lee to have a resistor is disposed to face an outer side surface of the serializer since passive electrical components, such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions as taught by Lee (paragraph 19).
In regard to claim 3, Kim teaches a heat dissipation pad (an insulating layer DLY2) being disposed in other surface of the substrate (Fig. 3 and paragraph 52), wherein the serializer is disposed to be overlapped with the heat dissipation pad in the optical axis direction (the insulating layer DLY2 is shown overlapping the digital circuit chip 530 in Fig. 3).
In regard to claim 12, Kim doesn’t explicitly teach wherein an adhesive member is applied to one surface and the other surface of the second layer. However, the Examiner takes official notice that due to the layers having attached components formed of different materials there would need to be adhesive layers that connect said components such as the insulating layer DLY2 and the image sensor chip 510 to the first and fourth layers LY1 and LY4 in order to accommodate for the wire bonds of the image sensor chip 510 and the lamination structure of the multilayer substrate 501 (paragraphs 37 and 46).
In regard to claim 13, Kim teaches a bump (the portion of the first sensor chip 510 wire bonded to the multilayer substrate 501) formed on a lower surface of the image sensor (it would be known to one skilled in the art the wire bonds would be on the bottom surface of the first image sensor chip 510) (Fig. 3 and paragraph 37), wherein the bump is bonded to the substrate (the first and second image sensor chips 510 and 520 of the image sensor chip 502 may be mounted on the multi-layer substrate 501 by a wire bonding method) (Fig. 3 and paragraph 37).
In regard to claim 14, Kim teaches wherein an adhesive member (the material used to form a wire bond) is applied to a certain space formed between the image sensor and the substrate (the first and second image sensor chips 510 and 520 of the image sensor chip 502 may be mounted on the multi-layer substrate 501 by a wire bonding method) (Fig. 3 and paragraph 37).
In regard to claim 17, Kim teaches a camera module (a dual camera module 110) (Fig. 1 and paragraph 21), comprising:
a first substrate (a first layer LY1, a second layer LY2, and a third layer LY3 of the multi-layer substrate 501 form the first substrate) (Fig. 3 and paragraph 47);
an image sensor (a first image sensor chip 510) being disposed on one surface of the first substrate (the first image sensor chip 510 is shown on the top surface of the second layer LY2 in Fig. 3);
a serializer (a digital circuit chip 530) being embedded inside the first substrate (the digital circuit chip 530 is shown inside the second layer LY2 in Fig. 3) (Fig. 3 and paragraph 37); and
a second substrate having one surface and another surface (a fifth layer LY5 of the multi-layer substrate 501 is shown with a top and bottom surface in Fig. 3), being disposed with the first substrate on one surface thereof (the fifth layer LY5 of the multi-layer substrate 501 is formed under the third layer LY3 as shown in Fig. 3) (Fig. 3 and paragraph 47),
wherein the first substrate includes a via hole (a first via VIA1) penetrating the first substrate in order to electrically connect the image sensor and the serializer (the first wiring EL1 is disposed inside the multilayer substrate 501 and connects the digital circuit chip 530 and the first via VIA1) (Fig. 1 and paragraph 41), and
wherein the serializer is disposed to be overlapped with the image sensor in an optical axis (the digital circuit chip 530 is shown overlapped with the first image sensor chip 510 in the optical direction in Fig. 2 and Fig. 9).
wherein the first substrate comprises first to third regions defined along the optical axis direction (the first layer LY1, the second layer LY2, and the third layer LY3 form the first to third regions),
wherein the substrate comprises the first region being disposed with the image sensor (a first layer LY1 is shown disposed with the first image sensor chip 510 in Fig. 3), the second region being disposed to surround the serializer (the second layer LY2 is shown surrounding the digital circuit chip 530 in Fig. 3), and the third region being disposed below the serializer (the third layer LY3 is shown below the digital circuit chip 530 in Fig. 3),
wherein the first region and the third region of the first substrate do not overlap the serializer in a direction perpendicular to the optical axis (the first layer LY1, the second layer LY2, and the third layer LY3 are shown not overlapping in a direction perpendicular to the optical axis in Fig. 3), and
However, Kim doesn’t explicitly teach wherein a resistor is disposed to face an outer side surface of the serializer.
Lee teaches a camera module (electronic device 300 that can be part of a digital camera) (Fig. 14 and paragraph 51), wherein a resistor is disposed to face an outer side surface of a serializer (electrical components 130a-130d can include a resistor which faces the outer bottom side surface of a Bi-directional multiplexer/switch 170 disposed on substrate 120) (Fig. 5f and paragraphs 27 and 36).
It would’ve been obvious to one skilled in the art to combine the teachings of Kim with the teachings of Lee to have a resistor is disposed to face an outer side surface of the serializer since passive electrical components, such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions as taught by Lee (paragraph 19).
In regard to claim 18, Kim teaches a power block (A / D converter 514) and a connector (output interface 517) are disposed on the other surface of the second substrate (due to the output interface 517 and the A / D converter 514 being within the first image sensor chip 510, they are considered disposed on the top surface of the fourth layer LY4 of the multi-layer substrate 501) (Fig. 1, Fig. 3, and 66 and 72).
In regard to claim 20, Kim teaches a heat dissipation pad (a fourth layer LY4 of the multi-layer substrate 501) being disposed between the first substrate and the second substrate (the fourth layer would absorb heat generated electrical components and is shown between the third layer LY3 and fifth layer LY5 as shown in Fig. 3),
wherein the serializer is disposed to be overlapped with the heat dissipation pad in the optical axis direction (the digital circuit chip 530 is shown overlapped with the third layer of the multi-layer substrate 501 in Fig. 3).
In regard to claim 23, Kim doesn’t explicitly teach wherein an adhesive member is applied to one surface and the another surface of the second region. However, the Examiner takes official notice that due to the layers having attached components formed of different materials there would need to be adhesive layers that connect said components such as the insulating layer DLY2 and the image sensor chip 510 to the first and fourth layers LY1 and LY4 in order to accommodate for the wire bonds of the image sensor chip 510 and the lamination structure of the multilayer substrate 501 (paragraphs 37 and 46).
In regard to claim 24, Kim teaches a bump (the portion of the first sensor chip 510 wire bonded to the multilayer substrate 501) being formed on a lower surface of the image sensor (it would be known to one skilled in the art the wire bonds would be on the bottom surface of the first image sensor chip 510) (Fig. 3 and paragraph 37), wherein the bump is bonded to the first substrate (the first and second image sensor chips 510 and 520 of the image sensor chip 502 may be mounted on the multi-layer substrate 501 by a wire bonding method) (Fig. 3 and paragraph 37).
In regard to claim 25, Kim teaches wherein an adhesive member (the material used to form a wire bond) is applied to a certain space formed between the image sensor and the first substrate (the first and second image sensor chips 510 and 520 of the image sensor chip 502 may be mounted on the multi-layer substrate 501 by a wire bonding method) (Fig. 3 and paragraph 37).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lee as applied to claim 1 above, and further in view of Koehler (US 2010/0259672 A1).
In regard to claim 15, Kim in view of Lee doesn’t explicitly teach wherein the serializer is any one among a low voltage differential signaling (LVDS), V-by-One HS, HD-Base-T, and MIPI A-PHY chip sets.
Koehler teaches (an image acquisition system) a camera module and a manufacturing method (Fig. 2 and paragraph 8), wherein the serializer (an LVDS chip) is any one among a low voltage differential signaling (LVDS), V-by-One HS, HD-Base-T, and MIPI A-PHY chip sets (the LVDS chip functions as the serializer within camera K to enable the data captured by the sensor to reach the chip so that the latter can process and/or store and/or forward said data) (Fig. 2 and paragraphs 12 and 42).
It would have been obvious to one skilled in the art to combine the teachings of Kim in view of Lee with the teachings of Koehler to have the serializer be any one among a low voltage differential signaling (LVDS), V-by-One HS, HD-Base-T, and MIPI A-PHY chip sets since these are well known high speed communication elements within devices transmitting data.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lee as applied to claim 1 above, and further in view of Dogiamis et al. (US 20200168972 A1; hereinafter “Dogiamis”)
In regard to claim 16, Kim teaches the image sensor is one image sensor among a plurality types of image sensors (the first image sensor chip 510 and the second image sensor chip 520 are both within the device) (Fig. 3 and paragraph 25.
However, Kim in view of Lee doesn’t explicitly teach wherein a pin is formed at a position corresponding to a connecting terminal configured with one pin map on one surface of the substrate.
Dogiamis teaches a SiP module (an electronic control unit (ECU) 210) (Fig. 4A and paragraph 43), wherein a pin (a single output pin) is formed at a position corresponding to a connecting terminal configured with one pin map on one surface of a substrate (the single output pin of the digital interconnect interface die 446 would be on the surface of the packaging substrate 462 as shown in Fig. 4A) (Fig. 4A and paragraph 44).
It would have been obvious to one skilled in the art to combine the teachings of Kim with the teachings of Dogiamis to have a pin formed at a position corresponding to a connecting terminal configured with one pin map on one surface of the substrate since this layout of a serializer is well known amongst those skilled in the art as the primary function of a serializer is to have multiple data inputs convert into a single output data line.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lee as applied to claim 17 above, and further in view of Dogiamis.
In regard to claim 26, Kim teaches the image sensor is one image sensor among a plurality types of image sensors (the first image sensor chip 510 and the second image sensor chip 520 are both within the device) (Fig. 3 and paragraph 25.
However, Kim in view of Lee doesn’t explicitly teach wherein a pin is formed at a position corresponding to a connecting terminal configured with one pin map on one surface of the substrate.
Dogiamis teaches a SiP module (an electronic control unit (ECU) 210) (Fig. 4A and paragraph 43), wherein a pin (a single output pin) is formed at a position corresponding to a connecting terminal configured with one pin map on one surface of a substrate (the single output pin of the digital interconnect interface die 446 would be on the surface of the packaging substrate 462 as shown in Fig. 4A) (Fig. 4A and paragraph 44).
It would have been obvious to one skilled in the art to combine the teachings of Kim with the teachings of Dogiamis to have a pin formed at a position corresponding to a connecting terminal configured with one pin map on one surface of the substrate since this layout of a serializer is well known amongst those skilled in the art as the primary function of a serializer is to have multiple data inputs convert into a single output data line.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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