Prosecution Insights
Last updated: April 19, 2026
Application No. 18/283,013

RESISTOR, VARIABLE RESISTOR, AND METHOD FOR MANUFACTURING RESISTOR

Non-Final OA §102§103
Filed
Sep 20, 2023
Examiner
LEE, KYUNG S
Art Unit
2831
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tokyo Cosmos Electric Co., Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
2y 2m
To Grant
92%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
984 granted / 1129 resolved
+19.2% vs TC avg
Minimal +5% lift
Without
With
+4.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
33 currently pending
Career history
1162
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
39.2%
-0.8% vs TC avg
§102
41.4%
+1.4% vs TC avg
§112
10.7%
-29.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1129 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tepper et al. (US Pub. 2009/0206979). Regarding claim 1, Tepper teaches a resistor (resistor comprises of an electrically conductive stack 10; see at least paragraph 0019 and figs. 1 and 2) disposed on an insulating layer (insulator plate 3; see paragraph 0026), wherein: the resistor comprises a more-conductor-containing layer (layer 12 comprising of Al, Cu, steel, Ag or Sn; see paragraph 0027) and a more-insulator-containing layer (layer 14 comprising of mix of conductive materials and ceramic; see paragraphs 0028-0034), the more-conductor-containing layer containing more conductors than insulators (composed of metal layer, thus contain more conductor compared to the more-insulator-containing layer; see paragraph 0027), the more-insulator-containing layer being free of lead and containing more insulators than conductors (may comprise of metal, non-metal, cermet and/or ceramic, thus containing more insulator than the more-conductive-containing layer; see paragraphs 0028-0034); and the more-conductor-containing layer includes a polished surface (surface where the movable contact 20 slides is “polished” to make it planar; see paragraphs 0052-0053). Regarding claim 2, Tepper teaches, the resistor according to claim 1, wherein a film thickness of the more-conductor-containing layer (12) in a low-resistance region (resistance is less than 10% of the layer 14; see paragraph 0041) is thicker than a film thickness of the more-insulator-containing layer in a high-resistance region (the ceramic layer 14 is between 0.1 to 1 times the thickness of layer 12; see paragraph 0047), the low-resistance region being a low-resistance region in which a resistance value is equal to or lower than a prescribed value (as a “prescribed value” resistance for layer 12 is less than 10% of the layer 14; see paragraph 0041), the high-resistance region being a high-resistance region in which the resistance value is higher than the prescribed value (as a “prescribed value” resistance for layer 12 is less than 10% of the layer 14; see paragraph 0041). Regarding claim 3, Tepper teaches a moveable contact 20 moving along the resistor 10 (see fig. 2 and paragraphs 0052-0053). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Louis (US Pat. 3,393,390). Regarding claim 4, Louis teaches a method of manufacturing a resistor (potentiometer; see the Abstract and figs. 1-5), comprising: forming a coating film (resistance coating 30) on an insulating layer (insulating substrate 10) by using a resistor ink free of lead (silver paint to form the resistance track 30; see col. 4, lines 25-34); and polishing a film surface of the coating film to calibrated to desired tolerance for resistance (col. 4, lines 35-37) and to provide proper uniformity of resistance along its length (col. 2, lines 57-66). Louis teaches the claimed invention except a polishing amount of the coating film being in a range of 0.1% to 10% with respect to a coating film amount of the coating film. It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to have polished the coating in an amount ranging between 0.1 to 10%, since Louis teaches that polishing allows for reaching a desired resistance and forming a uniform resistance surface along the resistive length for smoother/reduced noise operation. Regarding claim 5, Louis teaches the method, wherein the polishing amount is determined based on an increased amount in a resistance value of the coating film after the polishing with respect to the resistance value of the coating film before the polishing (polishing is performed on the film surface of the coating film to calibrated to desired tolerance for resistance [col. 4, lines 35-37] and to provide proper uniformity of resistance along its length [col. 2, lines 57-66]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYUNG S LEE whose telephone number is (571)272-1994. The examiner can normally be reached 7AM-3PM M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Renee Luebke can be reached at 571-272-2009. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KYUNG S LEE/Primary Examiner, Art Unit 2833
Read full office action

Prosecution Timeline

Sep 20, 2023
Application Filed
Jan 21, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603198
SURFACE-MOUNTED POLYMER PCT OVERCURRENT PROTECTION ELEMENT HAVING SMALL PACKAGE SIZE
2y 5m to grant Granted Apr 14, 2026
Patent 12592328
RESISTOR TRIMMING DEVICE AND ELECTRONIC DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12586698
DEVICES AND METHODS RELATED TO MOV HAVING MODIFIED EDGE
2y 5m to grant Granted Mar 24, 2026
Patent 12580104
SHUNT RESISTOR AND SHUNT RESISTANCE DEVICE
2y 5m to grant Granted Mar 17, 2026
Patent 12580105
MULTILAYER VARISTOR AND METHOD FOR MANUFACTURING THE SAME
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
92%
With Interview (+4.8%)
2y 2m
Median Time to Grant
Low
PTA Risk
Based on 1129 resolved cases by this examiner. Grant probability derived from career allow rate.

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