DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“measurement unit”, “timing adjustment information calculation unit” and “timing adjustment information setting unit” in claim 1;
“switching unit” in claim 2;
“communication unit” in claim 3;
“rewriting unit” in claim 4.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Objections
In claims 1 and 5 the acronym “PLC” is recited. The acronym’s full name should be described, at least once, before the acronym can be used to avoid ambiguity. For continuing examination purpose, the acronym “PID” in claims 1 and 5 has been construed as “PLC (Programmable Logic Controller)”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 5 recites a limitation “at least one of the first PLC and the second PLC”. The plain meaning of phrase “at least one of A and B” is “at least one of A and at least one of B” (for more details please see Ex parte Jung, 2016-008290 (PTAB Mar. 22, 2017) and/or SuperGuide Corp. v. DirecTV Enters., Inc., 358 F.3d 870 (Fed. Cir. 2004)). According to the disclosure of the specification, the intended meaning of the limitation should be at least one of the first PCL or the second PLC. For continuing examination purpose, this limitation in the claims has been construed as "at least one of the first PLC [[and]] or the second PLC””.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Canedo (US 20200050167 A1, hereinafter as “Canedo”) in view of Sugimoto (US 6281698 B1, hereinafter as “Sugimoto”).
Regarding claim 1, Canedo teaches:
A PLC (Programmable Logic Controller) apparatus (PLC bank 1 in FIG. 1) comprising a first PLC (PLC 1 in FIG. 1) and a second PLC (PLC 2 in FIG. 1), the PLC apparatus causing a PLC execution unit of each of the first PLC and the second PLC to perform execution of a sequence program (FIG. 1 and [0010]: “The duplicate inputs programming component creates a copy of the sensor inputs for a first group of PLCs in a first PLC bank and transfers the copy the sensor inputs to each PLC in the first group of PLCs. The PLC input port receives processing results from each PLC in the first group of PLCs in response to transferring the copy of the sensor inputs”. This teaches PLC 1 and PLC 2 perform execution of a sequence program for same sensor input).
Canedo teaches all the limitations except performing test execution of a sequence program to match the execution timing between PLC 1 and PLC 2. Specifically, Canedo does not teach the PLC apparatus comprising a measurement unit configured to measure time required by the PLC execution unit of each of the first PLC and the second PLC from start to end of the sequence program; a timing adjustment information calculation unit configured to calculate, based on the time measured by the measuring unit, timing adjustment information including at least either execution time or execution cycles in cyclic execution of the sequence program in the first PLC and the second PLC; and a timing adjustment information setting unit configured to set the timing adjustment information calculated by the timing adjustment information calculation unit; wherein the timing adjustment information is set for at least any one of the first PLC and the second PLC.
However, Sugimoto teaches in an analogous art:
a measurement unit (skew board 100 in FIG. 12) configured to measure time required by the I/O channel execution unit of each of the first I/O channel and the second I/O channel from start to end of a transmission sequence program ([Col. 2 Lines 20-45]: “The timing calibration of the conventional LSI testing apparatus is carried out with the standard circuit 106 of the skew board 100 connected individually to each of the I/O terminals 22. When a single I/O terminal 22 is connected to the standard circuit 106, two processes are performed: one for synchronizing the timings of signals output from a plurality of I/O terminals 22, … The process for synchronizing the output timings is performed while the switching relay 104 is being set to the standard comparator 110. In that case, the signal output from the particular I/O terminal 22 is fed to the standard comparator 110. The standard comparator 110 determines the value of the output signal in synchronized relation with the reference signal CLK. For timing calibration, the result of the determination above is used as a basis for adjusting the delay time of the skew circuit 30 in such a manner that the turning timing of the output signal is synchronized with a standard timing. When the process above has been carried out on all I/O terminals 22, the turning timings of the output signals are synchronized on all terminals 22”. This teaches to measure time required by the I/O channel of each of the first and second I/O channels from start to end of a transmission sequence program);
a timing adjustment information calculation unit configured to calculate, based on the time measured by the measuring unit, timing adjustment information including at least either execution time or execution cycles in cyclic execution of the sequence program in the first I/O channel and the second I/O channel ([Col. 2 Lines 35-45]: “ The standard comparator 110 determines the value of the output signal in synchronized relation with the reference signal CLK. For timing calibration, the result of the determination above is used as a basis for adjusting the delay time of the skew circuit 30 in such a manner that the turning timing of the output signal is synchronized with a standard timing. When the process above has been carried out on all I/O terminals 22, the turning timings of the output signals are synchronized on all terminals 22”. This teaches to calculate, based on the time measured by the measuring unit, timing adjustment information including execution time of the transmission sequence program in the I/O channels); and
a timing adjustment information setting unit (skew circuit 30 in FIG. 12) configured to set the timing adjustment information calculated by the timing adjustment information calculation unit ([Col. 2 Lines 35-45]: “The standard comparator 110 determines the value of the output signal in synchronized relation with the reference signal CLK. For timing calibration, the result of the determination above is used as a basis for adjusting the delay time of the skew circuit 30 in such a manner that the turning timing of the output signal is synchronized with a standard timing”. This teaches to adjust timing of the skew circuit 30 calculated based on measurement);
wherein the timing adjustment information is set for at least any one of the first I/O channel and the second I/O channel ([Col. 2 Lines 35-45]: “The standard comparator 110 determines the value of the output signal in synchronized relation with the reference signal CLK. For timing calibration, the result of the determination above is used as a basis for adjusting the delay time of the skew circuit 30 in such a manner that the turning timing of the output signal is synchronized with a standard timing. When the process above has been carried out on all I/O terminals 22, the turning timings of the output signals are synchronized on all terminals 22”. This teaches to set the timing adjustment information for all I/O channels).
Sugimoto’s teaching about matching the timing of parallel processing channels can be incorporated into Canedo to match the processing timing of the parallel circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Canedo based on the teaching of Sugimoto, to make the PLC apparatus to further comprise a measurement unit configured to measure time required by the PLC execution unit of each of the first PLC and the second PLC from start to end of a test sequence program; a timing adjustment information calculation unit configured to calculate, based on the time measured by the measuring unit, timing adjustment information including at least either execution time or execution cycles in cyclic execution of the sequence program in the first PLC and the second PLC; and a timing adjustment information setting unit configured to set the timing adjustment information calculated by the timing adjustment information calculation unit; wherein the timing adjustment information is set for at least any one of the first PLC and the second PLC. One of ordinary skill in the art would have been motivated to do this modification since “signals output by the individual I/O terminals 22 should be consistent and in synchronism”, as Sugimoto teaches in [Col. 1 Lines 53-55].
Regarding claim 3, Canedo-Sugimoto teach(es) all the limitations of its base claim from which the claim depends on.
Sugimoto further teaches:
a communication unit configured to transmit the timing adjustment information of the first I/O channel and the second I/O channel calculated by the timing adjustment information calculation unit, to an external apparatus, and receive a setting instruction for the transmitted timing adjustment information, from the external apparatus (FIG. 12 and [Col. 2 Lines 20-45]: “The timing calibration of the conventional LSI testing apparatus is carried out with the standard circuit 106 of the skew board 100 connected individually to each of the I/O terminals 22. When a single I/O terminal 22 is connected to the standard circuit 106, two processes are performed: one for synchronizing the timings of signals output from a plurality of I/O terminals 22, … The process for synchronizing the output timings is performed while the switching relay 104 is being set to the standard comparator 110. In that case, the signal output from the particular I/O terminal 22 is fed to the standard comparator 110. The standard comparator 110 determines the value of the output signal in synchronized relation with the reference signal CLK. For timing calibration, the result of the determination above is used as a basis for adjusting the delay time of the skew circuit 30 in such a manner that the turning timing of the output signal is synchronized with a standard timing. When the process above has been carried out on all I/O terminals 22, the turning timings of the output signals are synchronized on all terminals 22”. The timing adjustment information is transmitted from the skew board 100, via a communication unit, to an external apparatus to convert to a delay time setting for the skew circuit 30 which is applied to the skew circuit 30), wherein
the timing adjustment information setting unit sets the timing adjustment information to at least any of the first I/O channel and the second I/O channel based on the received setting instruction (FIG. 12 and [Col. 2 Lines 20-45]: “The timing calibration of the conventional LSI testing apparatus is carried out with the standard circuit 106 of the skew board 100 connected individually to each of the I/O terminals 22. When a single I/O terminal 22 is connected to the standard circuit 106, two processes are performed: one for synchronizing the timings of signals output from a plurality of I/O terminals 22, … The process for synchronizing the output timings is performed while the switching relay 104 is being set to the standard comparator 110. In that case, the signal output from the particular I/O terminal 22 is fed to the standard comparator 110. The standard comparator 110 determines the value of the output signal in synchronized relation with the reference signal CLK. For timing calibration, the result of the determination above is used as a basis for adjusting the delay time of the skew circuit 30 in such a manner that the turning timing of the output signal is synchronized with a standard timing. When the process above has been carried out on all I/O terminals 22, the turning timings of the output signals are synchronized on all terminals 22”. Based on the received delay time setting, the delay time of the skew circuit 30 is adjusted for all I/O channels).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have further modified Canedo based on the teaching of Sugimoto, to make the PLC apparatus to further comprise a communication unit configured to transmit the timing adjustment information of the first PLC and the second PLC calculated by the timing adjustment information calculation unit, to an external apparatus, and receive a setting instruction for the transmitted timing adjustment information, from the external apparatus, wherein the timing adjustment information setting unit sets the timing adjustment information to at least any of the first PLC and the second PLC based on the received setting instruction. One of ordinary skill in the art would have been motivated to do this modification since “signals output by the individual I/O terminals 22 should be consistent and in synchronism”, as Sugimoto teaches in [Col. 1 Lines 53-55].
Claim 5 recites a non-transitory computer readable medium encoded with a program comprising operational steps conducted by the PLC apparatus of claim 1 with patentably the same limitations. Therefore, claim 5 is rejected for the same reason recited in the rejection of claim 1.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Canedo in view of Khoshgard (US 10389374 B1, hereinafter as “Khoshgard”).
Regarding claim 2, Canedo-Sugimoto teach(es) all the limitations of its base claim from which the claim depends on, but do not teach a switching unit configured to switch between a mode for performing the test execution and a mode for performing the cyclic execution to which the timing adjustment information is applied.
However, Khoshgard teaches in an analogous art:
a switching unit (switch 104 in FIG.s 1 and 4) configured to switch between a mode for performing the test execution (FIG. 1 and [Col. 3 Lines 40-70]: during “calibration mode”, switch 104 is in the second position to calibrate the time-offsets between ADC channels) and a mode for performing the cyclic execution to which the timing adjustment information is applied (FIG. 4 and [Col. 7 Lines 30-55] during “operating mode”, switch 104 is in the first position to sample ADC input with “optimized time-offset calibration data”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Canedo-Sugimoto based on the teaching of Khoshgard, to make the PLC apparatus to further comprise a switching unit configured to switch between a mode for performing the test execution and a mode for performing the cyclic execution to which the timing adjustment information is applied. One of ordinary skill in the art would have been motivated to do this modification since it can help optimize “time-offset calibration data”, as Khoshgard teaches in [Col. 2 Lines 15-20].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Canedo in view of MARUYAMA (US 20220317648 A1, hereinafter as “MARUYAMA”).
Regarding claim 4, Canedo-Sugimoto teach(es) all the limitations of its base claim from which the claim depends on, but do not teach a rewriting unit configured to execute, in order to reproduce a predetermined situation in the test execution, rewriting of the sequence program, rewriting of a signal state in the PLC apparatus, or rewriting of program variables, based on an instruction from the external apparatus via the communication unit.
However, MARUYAMA teaches in an analogous art:
a rewriting unit configured to execute, in order to reproduce a predetermined situation in execution, rewriting of the sequence program, rewriting of a signal state in the PLC apparatus, or rewriting of program variables, based on an instruction from external apparatus (FIG. 2 and [0077]: “there may be a real-time monitoring application that monitors a device or a variable, which is a monitoring target, in real time, an operation record analysis application that analyzes an operation record for reproducing an operation state of the PLC 1 and generates an analysis report, and the like”. This teaches a unit to rewrite the sequence program of PCL to reproduce a predetermined state of the PLC according to an instruction based on historical operation record from external PC).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Canedo-Sugimoto based on the teaching of MARUYAMA, to make the PLC apparatus to further comprise a rewriting unit configured to execute, in order to reproduce a predetermined situation in the test execution, rewriting of the sequence program, rewriting of a signal state in the PLC apparatus, or rewriting of program variables, based on an instruction from the external apparatus via the communication unit. One of ordinary skill in the art would have been motivated to do this modification since it can help “reproducing an operation state of the PLC”, as MARUYAMA teaches in [0077].
Conclusion
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
IKEGAMI (US 20150293515 A1): teaches, in FIG. 2, PLC 11A connected in parallel with PLC 12A to form a redundant architecture to reliably prevent an emergency stop of the PLC due to a failure.
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/CHARLES CAI/Primary Patent Examiner, Art Unit 2115