Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This communication is in response to the application filed 22 September 2023 and the preliminary amendment filed 22 September 2023. Claims 1-17 and 19-21 are pending. The rejections are as stated below.
Information Disclosure Statement
The Information Disclosure Statements (IDSs) submitted in this application on 22 September 2023 and 22 January 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDSs are being considered by the examiner. The initialed copies of the1449s are enclosed herewith.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-17 and 19-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. In particular, claims are directed to a judicial exception (abstract idea) without significantly more.
Claim 1 (exemplary) recites a series of steps for managing instructions by switching memory tables from a first table to a second.
The claim is directed to a process, which is a statutory category of invention.
The claim is then analyzed to determine whether it is directed to a judicial exception. The claim recites the limitations of switching a page table from a first table to a second table in response to an instruction sending request for sending an instruction; obtaining a code according to the second table, the code being a code related to sending the instruction; and executing the code.
The claimed system simply describes series of steps for managing instructions by switching memory tables from a first table to a second. These limitations, as drafted, are processes that, under its broadest reasonable interpretation, covers performances and concepts performed in the human minds (including observation; evaluation; judgment; opinion); and a method of organizing human activity which includes fundamental economic principles or practices (including mitigating risk), and managing personal behavior or relationships or interactions between people (including following rules or instructions) that enhance managing instructions between memory tables , fall within the certain methods of organizing human activity category of the USPTO’s Guidance. See 2019 Revised Guidance, 84 Fed. Reg. at 52 n.14. Observations and evaluation occur when the system periodically switches memory tables, obtains and executes the instructions. mitigating risk occurs because the system prevents hacker attempts and manages personal behavior (including following rules or instructions). If a claim limitation, under its broadest reasonable interpretation, covers concepts performed in the human mind, fundamental economic principles or practices, and/or managing personal behavior or abstract ideas, then it falls within the “mental processes” and “a method of organizing human activity” in the 2019 PEG grouping of abstract ideas. Accordingly, these claims recite an abstract idea.
Next, the claim is analyzed to determine if it is integrated into a practical application. The recited judicial exception may be integrated into a practical application by identifying whether there are any additional elements recited in the claim beyond the judicial exception and evaluating those additional elements individually and in combination to determine whether they integrate the exception into a practical application. The claim recites the additional limitation of a first processor, an extended page table (EPT), a first EPT, a second EPT, a second processor and making the first processor send a target instruction to the second processor to perform the steps. The processor in the steps is recited at a high level of generality, i.e., as a generic processor performing a generic computer function of processing data. This generic processor limitation is no more than mere instructions to apply the exception using generic computer component. Merely adding generic computer components to perform abstract ideas does not integrate those ideas into a practical application. See 2019 Revised Guidance, 84 Fed. Reg. at 55 (identifying “merely includ[ing] instructions to implement an abstract idea on a computer” as an example of when an abstract idea has not been integrated into a practical application). Also, these limitations are an attempt to limit the abstract idea to a particular technological environment. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to the abstract idea.
Next, the claim is analyzed to determine if there are additional claim limitations that individually, or as an ordered combination, ensure that the claim amounts to significantly more than the abstract ideas (whether claim provides inventive concept). As discussed above, the recitation of the claimed limitations amounts to mere instructions to implement the abstract idea on a computer (using the computer as a tool to implement the abstract idea). Taking the additional elements individually and in combination, the computer at each step of the process performs purely generic computer functions. As such, there is no inventive concept sufficient to transform the claimed subject matter into a patent-eligible application. The same analysis applies here, i.e., mere instructions to apply an exception using a generic computer component cannot integrate a judicial exception into a practical application at or provide an inventive concept.
Viewing the limitations as an ordered combination does not add anything further than looking at the limitations individually. When viewed either individually, or as an ordered combination, the additional limitations do not amount to significantly more than the abstract idea itself. Therefore, the claim does not amount to significantly more than the recited abstract idea. Therefore, the claim is not patent eligible.
The analysis above applies to the statutory category of invention of claims 1, 19 (specification, ¶ 0194 excludes transitory media) and 20. Furthermore, the dependent claims 2-17 and 21 do not resolve the issues raised in the independent claims.
Dependent claims 2-17 and 21 include the additional elements of a springboard code, a GPA, HPA, GVA, EPTP switch and IPI instructions. As discussed above with respect to the independent claims The additional elements in the steps are recited at a high level of generality, i.e., as generic elements performing generic computer function of processing data. The limitations are an attempt to limit the abstract idea to a particular technological environment.
Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to the abstract idea.
As discussed above, the recitation of the claimed limitations amounts to mere instructions to implement the abstract idea on a computer (using the computer as a tool to implement the abstract idea). Taking the additional elements individually and in combination, the computer at each step of the process performs purely generic computer functions. As such, there is no inventive concept sufficient to transform the claimed subject matter into a patent-eligible application. The same analysis applies here, i.e., mere instructions to apply an exception using a generic computer component cannot integrate a judicial exception into a practical application at or provide an inventive concept.
The remaining dependent claims do not add limitations that meaningfully limit the abstract idea. Dependent claims, recite additional limitations and steps. However, as mentioned above with respect to the independent claims, the claimed limitations are no more than mere instructions to apply the exception using generic computer component. Also, these limitations are an attempt to limit the abstract idea to a particular technological environment. Accordingly, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to the abstract idea.
These claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements are simply steps performed by a generic computer. The claim merely amounts to the application or instructions to apply the abstract idea on a device, and is considered to amount to nothing more than requiring a generic device to merely carry out the abstract idea itself.
The dependent claims do not impart patent eligibility to the abstract idea of the independent claims. Therefore, none of the dependent claims alone or as an ordered combination add limitations that qualify as integrating the abstract idea into a practical application or amounts to significantly more than the abstract idea itself.
Accordingly, claims 1-17 and 19-21 are rejected as ineligible for patenting under 35 U.S.C. 101 based upon the same analysis.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Examiner’s Note, since the reference does not have paragraph numbers or page numbers, the examiner cited the abstract, summary of invention and detailed description). Once the document is obtained with page numbers, more specific citations will be provided.
Claims 1, 2, 5, 9-12, 17, 19, 20 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LIU et al. (WO 2016192483 A1), hereinafter “LIU”.
Regarding claims 1, 19 and 20, LIU discloses an instruction sending method and a corresponding apparatus including a memory and a first processor, comprising the steps of:
switching an extended page table (EPT) from a first EPT to a second EPT, in response to
an instruction sending request for sending a target instruction to a second processor (abstract, summary of invention);
obtaining a target code according to the second EPT, the target code being a code related
to sending the target instruction (abstract, summary of invention); and
executing the target code, to make the first processor send the target instruction to the
second processor (abstract, summary of invention).
Regarding claim 2, LIU discloses the switching the EPT from the first EPT to the second EPT comprises:
obtaining a springboard code according to the first EPT; and
executing the springboard code, to switch the EPT from the first EPT to the second EPT. (abstract, summary of invention).
Regarding claim 5, LIU discloses subsequent to said executing the target code:
obtaining a springboard code according to the second EPT; and
executing the springboard code, to switch the EPT from the second EPT to the first EPT (abstract, summary of invention).
Regarding claim 9, LIU discloses saving a second register context, the second register context being a context of a register of the first processor after switching the EPT from the first EPT to the second EPT; and restoring the context of the register of the first processor to the second register context after switching the EPT from the second EPT to the first EPT (abstract, summary of invention and detailed description).
Regarding claim 10, LIU discloses turning off a local interrupt of the first processor before saving the second register context; and turning on the local interrupt of the first processor after restoring the context of the register of the first processor to the second register context (detailed description).
Regarding claim 11 and 21, LIU discloses the springboard code comprises: an EPTP switch instruction; and
said executing the springboard code comprises:
calling the EPTP switch instruction in the springboard code (summary of invention and detailed description).
Regarding claim 12, LIU discloses subsequent to said executing the springboard code: performing security check on the second processor; and
terminating, in response to the security check failing, sending the target instruction to the
second processor (detailed description).
Regarding claim 17, LIU discloses the target instruction is an inter-processor interrupt IPI instruction; and the target code is a code related to sending the IPI instruction (detailed description).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Goldsmith et al. (US 20160188354A1) discloses “Embodiments of an invention for efficient enabling of EPTs are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and execution hardware. The instruction hardware is to receive a plurality of instructions, including an instruction to switch an extended page table pointer (EPTP) in a non-root mode. The control logic is logic to determine, in response to receiving the instruction, whether to cause a first virtual machine exit, wherein the determination is based on whether a valid entry is found in an active EPTP list. The execution hardware is to execute a virtual machine monitor, wherein the virtual machine monitor is to activate a populated EPTP list in response to determining that extended page tables are being used and to activate an unpopulated EPTP list in response to determining that extended page tables are not being used.”
Banginwar et al. (US 20250390443 A1) discloses “A data processing system (DPS) uses platform protection technology (PPT) to protect some or all of the code and data belonging to certain software modules. The PPT may include a virtual machine monitor (VMM) to enable an untrusted application and a trusted application to run on top of a single operating system (OS), while preventing the untrusted application from accessing memory used by the trusted application. The VMM may use a first extended page table (EPT) to translate a guest physical address (GPA) into a first host physical address (HPA) for the untrusted application. The VMM may use a second EPT to translate the GPA into a second HPA for the trusted application. The first and second EPTs may map the same GPA to different HPAs. Other embodiments are described and claimed”.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hani Kazimi whose telephone number is (571) 272-6745. The examiner can normally be reached Monday-Friday from 8:30 AM to 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Abhishek Vyas can be reached on (571) 270-1836. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Respectfully Submitted
/HANI M KAZIMI/
Primary Examiner, Art Unit 3691