Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The applicant has amended their application as follows:
Amended: 1 and 10
Cancelled: 12 and 18-19
Added: None
Therefore, claims 1-11, 13-17 and 20-23 are currently pending in the instant application.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 10-11, 13-17 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 11,004,385 B1, hereinafter “Li”) in view of Xiong et al. (US 2021/0287614 A1, hereinafter “Xiong”).
As to claim 1, Li (‘345) (Fig. 17) discloses a pixel driving circuit, comprising: a driving circuit (230) and an initialization circuit (260, 250);
wherein the driving circuit (240) is connected to a first node (N2), a second node (N1), and a third node (Node between 240 and 230); and
wherein the initialization circuit (260) is connected to the first node (N2), the initialization circuit (210) is further connected to the second node (N1, electrically connected) and/or the third node, and the initialization circuit (250, 260) is configured to provide a first initialization voltage (Vref) to the first node (N2), provide a first reset voltage (Vref) to the second node (N1) and/or provide a second reset voltage to the third node, so as to control a driving transistor (230) in the driving circuit to be turned on;
wherein a voltage difference between the first node (N2) and the third node (Node between 230 and 240) is greater than a threshold voltage of the driving transistor (Vth of 230; inherently the P-type transistor is turned off when the Vgs is greater than the Vth), and a voltage difference between the first node (N2) and the second node (N1) is less than the threshold voltage of the driving transistor (the voltage difference between the gate and drain of the transistor 230 is less than the threshold voltage when 230 is turned off),
the pixel driving circuit further comprises a data writing circuit (240), and a control electrode of the data writing circuit is connected to a gate driving signal terminal (S2-P);
the pixel driving circuit further comprises a third reset circuit (210), and a control electrode of the third reset circuit is connected to a first reset control signal line (S1);
a control electrode of a first reset circuit (260) of the initialization circuit is connected to a second reset control signal line (S1-n);
during a time period of each frame (Fig. 19 element Write frame), both a first time period (T1) in which the second reset control signal line (second scan signal; Col. 13 lines 17-18, S1-n is a second scan signal) provides a turn-on level signal (Col. 17 lines 36-42, a initialization unit 260 is turned on) and a second time period (T2) in which the gate driving signal terminal (third scan signal; Col. 13 lines 19-20, S2-P is a third scan signal) provides a turn-on level signal (Col. 17 lines 42-52, a data writing unit 240 is turned on during T2 ) are within a third time period (T1+T2) in which the first reset control signal line (S1) provides a turn-on level signal (Col. 17 lines 26-52, initialization circuit 210 is turned on during T1 and T2).
the pixel driving circuit further comprises a threshold compensation circuit (250);
wherein the data writing circuit (240) is connected to a first preset node (source of 230), a data signal terminal (Vdata) and the gate driving signal terminal (S2-P), and configured to write a data voltage provided by the data signal terminal to the first preset node in response to control of a signal of the gate driving signal terminal (S2-P);
wherein the threshold compensation circuit (250) is connected to a second preset node (N1), the first node (N2) and a gate driving signal terminal (S2-n), and configured to connect the second preset node to the first node in response to the control of the signal of the gate driving signal terminal; and
wherein one of the first preset node (source of 230) and the second preset node (N1) is the second node (N1), and the other of the first preset node (source of 230) and the second preset node (N1) is the third node (node between 230 and 240).
Li does not disclose wherein the threshold compensation circuit (250) is connected to a second preset node (Fig. 17; N1), the first node (N2) and the gate driving signal terminal, and configured to connect the second preset node to the first node in response to the control of the signal of the gate driving signal terminal.
However, Xiong (Fig. 7) teaches wherein the threshold compensation circuit (213) is connected to a second preset node (N3), the first node (N1) and the gate driving signal terminal (S2), and configured to connect the second preset node to the first node in response to the control of the signal of the gate driving signal terminal (Para. 0062).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Xiong to connect the data writing circuit and the compensation circuit to the same gate driving signal in the device disclosed by Li. The motivation would have been to compensate the threshold voltage of the transistor during the data writing phase (Xiong; Para. 0064).
As to claim 2, Li (Fig. 17) discloses the pixel driving circuit according to claim 1, wherein the driving circuit (230) comprises the driving transistor (driving transistor); and
the driving transistor comprises a control electrode connected to the first node (N2), a first electrode (drain) connected to the second node (N1), and a second electrode (source) connected to the third node (node between 230 and 240).
As to claim 3, Li (Fig. 17) discloses the pixel driving circuit according to claim 1, wherein the initialization circuit (260, 250) comprises the first reset circuit (260);
the first reset circuit (260) is connected to a first control signal terminal (S1-n), the first node (N2), and a first voltage supply terminal (Vref), and configured to transmit the first initialization voltage (Vref) provided from the first voltage supply terminal to the first node (N2) in response to control of a signal of the first control signal terminal (S1-n; Col. 13 lines 40-42).
Li does not expressly disclose the initialization circuit further comprises a second reset circuit (210) and/or a fourth reset circuit (This limitation is considered optional.);
the second reset circuit (210) is connected to a second control signal terminal (S1), the second node (N1), and a second voltage supply terminal (Vref), and is configured to transmit the first reset voltage (Vref) provided from the second voltage supply terminal to the second node (N1) in response to control of a signal of the second control signal terminal (S1; Col. 13 lines 26-46); and
the fourth reset circuit is connected to a third control signal terminal, the third node, and a third voltage supply terminal, and is configured to transmit the second reset voltage provided from the third voltage supply terminal to the third node in response to control of a signal of the third control signal terminal (This limitation is not considered.).
As to claim 4, Li (Fig. 17) discloses the pixel driving circuit according to claim 3, wherein the first reset circuit (260) comprises a first transistor (M7); and
the first transistor (M7) comprises a control electrode connected to the first control signal terminal (S1-n), a first electrode connected to the first voltage supply terminal (Vref), and a second electrode connected to the first node (N2).
As to claim 5, Li discloses the pixel driving circuit according to claim 4, wherein the first transistor is a metal oxide transistor (Col. 22 lines 63-65).
As to claim 6, Li (Fig. 17) discloses the pixel driving circuit according to claim 3, wherein the second reset circuit (210) comprises an eighth transistor (M3); and
the eighth transistor (M3) comprises a control electrode connected to the second control signal terminal (S1), a first electrode connected to the second voltage supply terminal (Vref), and a second electrode connected to the second node (N1, electrically connected).
As to claim 7, Li (Fig. 17) discloses the pixel driving circuit according to claim 3, wherein the fourth reset circuit comprises a ninth transistor (M3); and the ninth transistor comprises a control electrode connected to the third control signal terminal (S1), a first electrode connected to the third voltage supply terminal (Vref), and a second electrode connected to the third node (node between 230 and 240; This limitation is not considered in above claim 3.).
As to claim 10, Li (Fig. 17) discloses the pixel driving circuit according to claim 1,wherein the threshold compensation circuit comprises a second transistor (M6), and the data writing circuit comprises a fourth transistor (M5);
the second transistor (M6) comprises a control electrode connected to the gate driving signal terminal (S2-n), a first electrode connected to the first node (N2), and a second electrode connected to the second preset node (N1); and
the fourth transistor (M5) comprises a control electrode connected to the gate driving signal terminal (S2-P), a first electrode connected to the data signal terminal (Vdata), and a second electrode connected to the first preset node (S2-P).
As to claim 11, Li (Fig. 17) discloses the pixel driving circuit according to claim 3, wherein the first voltage supply terminal (Vref) is connected to a first initialization voltage supply line (supply line for Vref), and the first control signal terminal (S1-n) is connected to the second reset control signal line (supply line for S1-n); \the initialization circuit comprises the second reset circuit (210), the second voltage supply terminal (Vref) is connected to the first node (N2), and the second control signal terminal (S1) is connected to the first reset control signal line (supply line for S1) or
wherein the first voltage supply terminal (Vref) is connected to the second node (electrically connected to the node between 230 and 240 through 230), and the first control signal terminal (S1-n) is connected to the first reset control signal line (supply line for S1-n); and
the initialization circuit comprises the second reset circuit (210), the second voltage supply terminal (Vref) is connected to a first power supply terminal (supply line for Vref), and the second control signal terminal (S1) is connected to the second reset control signal line (supply line for S1).
As to claim 13, Li (Fig. 17) discloses the pixel driving circuit according to claim 11,
wherein the data writing circuit (240) is connected to the third node (node between 240 and 230), a data signal terminal (Vdata) and the gate driving signal terminal (S2-P), and is configured to write a data voltage provided by the data signal terminal to the third node in response to control of a signal of the gate driving signal terminal (Col. 13 lines 46-52).
As to claim 14, Li (Fig. 17) discloses the pixel driving circuit according to claim 13, wherein the data writing circuit (240) comprises a fourth transistor (M5); and
the fourth transistor comprises a control electrode connected to the gate driving signal terminal (S2-P), a first electrode connected to the data signal terminal (Vdata), and a second electrode connected to the third node (node between 230 and 240).
As to claim 15, Li (Fig. 17) discloses the pixel driving circuit according to claim 1, further comprising a control circuit (270, 220) and a coupling circuit (280);
wherein the control circuit (270, 220) is connected to an enabling signal terminal (Emit), a second power supply terminal (PVDD), the second node (N1), the third node (node between 270 and 230) and a fourth node (node between PVDD and 230), and is configured to transmit a power supply voltage (PVDD) provided by the second power supply terminal to the second node (N1) and to connect the third node (node between 270 and 230) to the fourth node (node between PVDD and 230), in response to control of a signal of the enabling signal terminal (Emit; Col. 13 lines 52-67); and
wherein the coupling circuit (280) is connected between the first node (N2) and the fourth node (node between PVDD and 270).
As to claim 16, Li (Fig. 17) discloses the pixel driving circuit according to claim 15, wherein the control circuit comprises a fifth transistor (M8) and a sixth transistor (M4), and the coupling circuit comprising a capacitor (280);
the fifth transistor (M4) comprises a control electrode connected to the enabling signal terminal (Emit), a first electrode connected to the second power supply terminal (electrically connected to PVDD), and a second electrode connected to the second node (N1);
the sixth transistor (M8) comprises a control electrode connected to the enabling signal terminal (Emit), a first electrode connected to the third node (node between 270 and 230), and a second electrode connected to the fourth node (node between PVDD and 270); and
the capacitor (280) comprises a first terminal connected to the first node (N2), and a second terminal connected to the fourth node (node between PVDD and 270).
As to claim 17, Li (Fig. 17) discloses the pixel driving circuit according to claim 15,
wherein the third reset circuit (210) is connected to the first reset control signal line (S1), a second initialization voltage supply line (Vref) and the fourth node (node between PVDD and 270), and is configured to transmit a second initialization voltage (Vref) supplied from the second initialization voltage supply line to the fourth node in response to control of a signal of the second reset control signal line (Col. 17 lines 34-67);
wherein the third reset circuit comprises a seventh transistor (M3); and the seventh transistor comprises a control electrode connected to the first reset control signal line (S1), a first electrode connected to the second initialization voltage supply line (Vref), and a second electrode connected to the fourth node (electrically connected to the node between PVDD and 270); and
wherein the seventh transistor is a metal oxide transistor (Col. 22 lines 63-65).
As to claim 21, Li discloses a method for driving a pixel driving circuit (Fig. 17), wherein the pixel driving circuit is the pixel driving circuit according to claim 1, and the method comprises:
in a reset phase (Fig. 19 element T1), providing, by the initialization circuit, the first initialization voltage (Vref) to the first node (N2; Col. 17 lines 36-42), while providing, by the initialization circuit, the first reset voltage (Vref) to the second node (N2; Col. 17 lines 36-42) and/or the second reset voltage to the third node, so as to control the driving transistor in the driving circuit to be turned on (Col. 17 lines 42-52),
provide a first reset voltage (Vref) to the second node (N2; Col. 17 lines 36-42) and/or provide a second reset voltage to the third node, so as to control a driving transistor in the driving circuit to be turned on (Col. 17 lines 42-52);
As to claim 22, Li discloses a display panel, comprising the pixel driving circuit according to claim 1 (Fig. 27).
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Li and Xiong as applied to claim 1 above, and further in view of Kang et al. (US 2022/0066587 A1, hereinafter “Kang”).
As to claim 20, Li in view of Xiong does not disclose the pixel driving circuit according to claim 1, wherein the driving transistor is a top-gate type transistor, the top-gate type transistor is configured with a conductive light shielding pattern, the conductive light shielding pattern is located on a side, which is distal to a control electrode of the top-gate type transistor, of an active layer of the top-gate type transistor, and an orthogonal projection of the conductive light shielding pattern on a plane where the active layer is located completely covers a channel region of the active layer; and
the conductive light shielding pattern is connected to the control electrode of the top-gate type transistor or a fourth power supply terminal.
However, Kang (Fig.4) teaches wherein the driving transistor is a top-gate type transistor (25; Para. 0046), the top-gate type transistor is configured with a conductive light shielding pattern (29), the conductive light shielding pattern is located on a side, which is distal to a control electrode of the top-gate type transistor (25, the light shielding layer is on the other side of the gate electrode 25) of an active layer (27) of the top-gate type transistor, and an orthogonal projection of the conductive light shielding pattern (29) on a plane where the active layer (27) is located completely covers a channel region (“the channel layer would be between the drain 23 and the source21”) of the active layer (the light shielding layer completely covers the channel as seen in the figure); and
the conductive light shielding pattern (29) is connected to the control electrode of the top-gate type transistor or a fourth power supply terminal (Para. 0061, the layer would be inherently connected to a voltage source).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Kang to include a light shielding layer in the device disclosed by Li/Xiong. The motivation would have been to prevent light from entering the active layer of the transistor (Kang; Para. 0046).
Claim(s) 23 is rejected under 35 U.S.C. 103 as being unpatentable over Li and Xiong as applied to claim 1 above, and further in view of Park et al. (US 2019/0114966 A1, hereinafter “Park”).
As to claim 23, Li in view of Xiong does not disclose the pixel driving circuit according to claim 1, wherein a difference between the first reset voltage and the second reset voltage is greater than 2V.
However, Park (Fig. 5) teaches wherein a difference between the first reset voltage (VINT1) and the second reset voltage (VINT2) is greater than 2V (Para. 0063).
It would have been obvious to one of ordinary skill in the art to combine the teaching of Park to apply different reset voltages in the device disclosed by Li/Xiong. The combination would have merely yielded predictable results of improve display quality (Park; Para. 0006).
Allowable Subject Matter
Claim 8 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art does not teach the limitation “in a case where the initialization circuit comprises the fourth reset circuit, the third voltage supply terminal is connected to a second reset voltage supply line, and the third control signal terminal is connected to the second reset control signal line” when combined with other limitations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant‘s disclosure.
Li (US 2019/0304371 A1) discloses a second reset circuit (Fig. 3 element 12).
Zhang et al. (US 2024/0119897 A1) discloses a third reset circuit (Fig. 5A).
Kato (US 2018/0211630 A1) discloses a third reset period (Fig. 16).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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BIPIN GYAWALI
Examiner
Art Unit 2625
/BIPIN GYAWALI/ Examiner, Art Unit 2625
/WILLIAM BODDIE/ Supervisory Patent Examiner, Art Unit 2625