DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/20/2026 has been entered.
Response to Amendment
The Amendment filed on 06/23/2026 in which claims 1, 8, 12 and 14-15 have been amended, claims 5, 7, and 13 have been cancelled and entered of record.
Claims 1-4, 6, 8-12, and 14-15 are pending for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 6, 8-10, 12, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Elliott et al., (US 20110115460), hereinafter Elliott in view of Lam et al. (US 20100039038 A1), hereinafter Lam.
Regarding claim 1, Elliott discloses a circuit (Fig. 3 and Fig. 12)
A resistive voltage divider (Fig. 3, 40) and (Fig. 12, R10, R11) [0112] comprising:
a first resistor (Fig. 12, R10) connected in series with a second resistor (Fig. 12, R11), wherein a first side of the first resistor (Fig. 12, side of R10 that connected to 115) comprises an input (Fig. 12, input that connected to line voltage 115) configured to receive an AC voltage of an AC network (Fig. 3, 20) (Fig. 12, line voltage 115) [0073], and a second side of the first resistor (Fig. 12, side of R10 that connected to R11) is connected to a first side of the second resistor (Fig. 12, side of R10 that connected to R11);
wherein an output of the resistive voltage divider (Fig. 12, side of R10 that connected to R11 and D10) is arranged between the first resistor (Fig. 12, R10) and the second resistor (Fig. 12, R11), the output (Fig. 12, output of D10) configured to provide a divided voltage of the AC voltage ([0112] feature of voltage divider); and
wherein a resistance value of the first resistor is constant (Fig. 12, R10 is a constant resistant according to conventional disclosure unless explicitly disclosed as a variable resistor) and a resistance value of the second resistor is adjustable, or vice versa; and
a controller (Fig. 3, 14) comprising:
a second input (Fig. 3, input of 14) (Fig. 12, output of the opto isolator connected to the controller as shown in Fig. 9) connected to the output of the voltage divider (Fig. 3, output of 40) (Fig. 12, output of D10 connected to the output of the opto isolator through the isolator) and configured to receive the divided voltage (Fig. 12, output of D10 is the divided voltage which connected to the controller as shown in Fig. 9 through the opto isolator for isolating the noise and the capacitor C10 acts as a filter [0112]),
a control output (Fig. 3, output of 14) connected to the power consumer and/or the power source (Fig. 3, 12 and 18) for controlling the power consumer and/or the power source [0061] [0063];
wherein the controller is configured to use the divided voltage (Fig. 12, output of D10 is the divided voltage) and a threshold trigger voltage ([0113] “one diode voltage drop”) of the controller ([0113] “one diode voltage drop” is the trigger voltage for the controller to control the output signal, thus consider part “of the controller) for providing a control signal to the power consumer and/or the power source [0061] [0063] at an offset time period being a time period when the divided voltage crosses a threshold trigger voltage previous to or after a zero crossing of the AC voltage (Fig. 12, [0112]-[0114] the capacitor hold the divided voltage until the negative half cycle and the diodes D11-D13 generate a voltage offset that would create time offset to the signal when to turn on or off with respect to the zero crossing of the input AC voltage), for connect or disconnect the power consumer and/or the power source to the AC network [0063].
Elliott does not disclose the resistance value of the second resistor is adjustable. Lam discloses a voltage divider circuit having a second resistor is adjustable (Fig. 17B, R1 is constant while Rvar is adjustable). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Elliott to incorporate the teaching of Lam and have the second resistor is adjustable. Doing so would allow users to change the ratio if the system is connected to a different voltage source having higher or lower input voltage.
Regarding claim 2, the combination of Elliott and Lam discloses the circuit according to claim 1 above, Elliott also discloses an absolute value of the threshold trigger voltage is larger than zero ([0113] “one diode voltage drop”).
Regarding claim 3, the combination of Elliott and Lam discloses the circuit according to claim 1 above, Elliott also discloses the amplitude of the divided voltage is smaller than the amplitude of the AC voltage (voltage divider in Fig. 12 divides voltage, thus the output voltage is smaller than the input voltage).
Regarding claim 4, the combination of Elliott and Lam discloses the circuit according to claim 1 above, Elliott also discloses the divided voltage has the same periodicity as the AC voltage (voltage divider in Fig. 12 is a passive/resistive voltage divider, thus no effect on phase or frequency).
Regarding claim 6, the combination of Elliott and Lam discloses the circuit according to claim 5 above, Elliott also discloses the offset time period is dependent on a control time delay being a sum of all time delays contributing to a total time period for connecting or disconnecting the power consumer and/or the power source to the AC network at the zero crossing of the AC voltage [0120]-[0122].
Regarding claim 8, the combination of Elliott and Lam discloses the circuit according to claim 1 above, Elliott also discloses a second side of the second resistor is configured to receive a DC voltage ([0113] “one diode voltage drop”), and wherein a value of the DC voltage is dependent on an offset time period being a time period when the divided voltage crosses the threshold trigger voltage previous to or after the zero crossing of the AC voltage [0120]-[0122].
Regarding claim 9, the combination of Elliott and Lam discloses the circuit according to claim 8 above, Elliott also discloses the DC voltage is constant when the offset time period is smaller than an offset threshold time period; or
the DC voltage alternates between a low value and a high value when the offset time period is larger than an offset threshold time period (Fig. 12, in positive cycle has one diode drop through D11 and in negative cycle has two diodes drop through D12 and D13).
Regarding claim 10, the combination of Elliott and Lam discloses the circuit according to claim 9 above, Elliott also discloses the DC voltage alternates between a low value and a high value, and wherein the DC voltage has a low value when the AC voltage waveform has a negative incline, and a high value when the AC voltage waveform has a positive incline (Fig. 12, in positive cycle has one diode drop through D11 and in negative cycle has two diodes drop through D12 and D13).
Regarding claim 12, the combination of Elliott and Lam discloses the circuit according to claim 1 above, Elliott also discloses the second side of the second resistor is connected to a DC output of the controller, and wherein the DC output is configured to provide the DC voltage to the voltage divide
Regarding claim 15, Elliott discloses a method (Fig. 3 and Fig. 12) for providing a control signal connecting or disconnecting (Fig. 3, 12) a power consumer and/or a power source (Fig. 3, 12 and 18) to an AC network (Fig. 3, 20) (Fig. 12, line voltage 115) [0073], the method comprising:
receiving an AC voltage of the AC network (Fig. 3, 20) (Fig. 12, line voltage 115) [0073],
dividing the AC voltage (Fig. 3, 40) and (Fig. 12, R10, R11) [0112] for obtaining a divided voltage of the AC voltage (Fig. 12, output of D10 is also a divided voltage) using a resistive voltage divider (Fig. 12, R10, R11) [0112] comprising a first resistor (Fig. 12, R10) connected in series with a second resistor (Fig. 12, R11), wherein a first side of the first resistor (Fig. 12, side of R10 that connected to R11) comprises an input (Fig. 12, input that connected to line voltage 115) configured to receive the AC voltage of the AC network (Fig. 3, 20) (Fig. 12, line voltage 115) [0073], and a second side of the first resistor (Fig. 12, side of R10 that connected to R11) is connected to a first side of the second resistor Fig. 12, side of R10 that connected to R11);
wherein an output of the resistive voltage divider (Fig. 12, side of R10 that connected to R11 and D10) is arranged between the first resistor (Fig. 12, R10) and the second resistor (Fig. 12, R11), the output (Fig. 12, output of D10) being configured to provide a divided voltage of the AC voltage ([0112] feature of voltage divider); and
wherein a resistance value of the first resistor is constant (Fig. 12, R10 is a constant resistant according to conventional disclosure unless explicitly disclosed as a variable resistor) and a resistance value of the second resistor is adjustable, or vice versa; and
using the divided voltage (Fig. 12, output of D10) and a threshold trigger voltage ([0113] “one diode voltage drop”) of the controller ([0113] “one diode voltage drop” is the trigger voltage for the controller to control the output signal, thus consider part “of the controller) for providing a control signal (Fig. 3, output of 14) to the power consumer and/or the power source (Fig. 3, 12 and 18) for connect or disconnect the power consumer and/or the power source to the AC network when the divided voltage crosses a threshold trigger voltage [0061] [0063], wherein the controller provides the control signal at an offset time period being a time period when the divided voltage crosses the threshold trigger voltage previous to or after a zero crossing of the AC voltage (Fig. 12, [0112]-[0114] the capacitor hold the divided voltage until the negative half cycle and the diodes D11-D13 generate a voltage offset that would create time offset to the signal when to turn on or off with respect to the zero crossing of the input AC voltage, thus the controller output a control signal that offset from the time when the AC voltage crossing zero).
Elliott does not disclose the resistance value of the second resistor is adjustable. Lam discloses a voltage divider circuit having a second resistor is adjustable (Fig. 17B, R1 is constant while Rvar is adjustable). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Elliott to incorporate the teaching of Lam and have the second resistor is adjustable. Doing so would allow users to change the ratio if the system is connected to a different voltage source having higher or lower input voltage.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Elliott and Lam in view of Price US Patent Publication 20010026159; hereinafter “Price”.
Regarding claim 11, Elliott discloses the circuit according to claim 10 above, Elliott also discloses the high voltage value is dependent on the trigger threshold voltage of the controller (Fig. 12, R10, R11) [0112] [0120]-[0122]. Elliott does not disclose the low voltage value is 0 V. Price discloses a circuit for detecting zero-crossing having a reference at zero volt (Fig. 3, the divider resistor is connected to ground). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to have modified Elliott to incorporate the teaching of Price and have low voltage value is 0 V. Doing so would allow detecting the zero-crossing when the AC voltage waveform has an negative incline without any time offset.
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAI H TRAN whose telephone number is (571)270-0668. The examiner can normally be reached M - F 8:30 - 5:00.
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/THAI H TRAN/Examiner, Art Unit 2836
/REXFORD N BARNIE/Supervisory Patent Examiner, Art Unit 2836
