DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Applicant’s Preliminary Amendment filed on 03/04/2026 in which claims 1, 6, 11 and 15 have been amended, claim 5 has been cancelled and entered of record.
Claims 1-4 and 6-15 are pending for examination.
Response to Argument
Applicant argues that: Elliott does not have a controller in the meaning of a controller according to the claimed invention. The controller according to the claimed invention requires signal processing for generating a control signal. Thus, the controller in the claimed invention is configured to:
Receive a divided voltage;
Provide a control signal based on the received divided voltage; and
Provide the control signal at an offset time period.
“[t]he function of providing a control signal in Elliott is provided by passive components without any signal processing, which is obvious from the circuit shown in Fig. 12. There is no signal processing device in this circuit in which a divided voltage is used for producing a control signal” and “Elliott is completely silent about using divided voltage as input to a controller for providing a control signal for connecting or disconnecting the power consumer 210 and/or the power source 220 to the AC network 300. In contrast to the present invention as now claimed, the divided voltage is used in Elliott for charging a capacitor for a power supply” (see Applicant’s remarks on pages 5-6).
In response, the arguments have been fully considered but are not persuasive. Examiner respectfully disagree because Elliott clearly disclosed a controller for performing the claimed invention:
Receive a divided voltage: (the control circuit D10, C10, opto-isolator 119 etc. receive the divided voltage of R10 and R11)
Provide a control signal based on the received divided voltage (output of opto-isolator 119 to feed a detected zero crossing switching signal to a controller; and
Provide the control signal at an offset time period (the divided voltage that does not immediately activate the opto-isolator 119. The opto-isolator is delayed and only turn on after the input waveform reached negative half cycle (see Elliott par. [0112]-[0114]).
Clearly, Elliott uses the divided voltage of R10 and R11 while the capacitor holds the charge at the divided signal and act as a delay to turn-on after the input power source signal reached negative half; the capacitor does not act as a power supply.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-10, 12-13, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Elliott et al., US Patent Publication 20110115460; hereinafter “Elliott”.
Regarding claim 1, Elliott discloses a circuit (Fig. 3 and Fig. 12)
a voltage divider (Fig. 3, 40) and (Fig. 12, R10, R11) [0112] comprising:
an input (Fig. 12, line voltage 115) configured to receive an AC voltage of an AC network (Fig. 3, 20) (Fig. 12, line voltage 115) [0073],
an output (Fig. 12, output of D10) configured to provide a divided voltage of the AC voltage ([0112] feature of voltage divider);
a controller (Fig. 3, 14) comprising:
a second input (Fig. 3, input of 14) (Fig. 12, output of the opto isolator connected to the controller as shown in Fig. 9) connected to the output of the voltage divider (Fig. 3, output of 40) (Fig. 12, output of D10 connected to the output of the opto isolator through the isolator) and configured to receive the divided voltage (Fig. 12, output of D10 is the divided voltage which connected to the controller as shown in Fig. 9 through the opto isolator for isolating the noise and the capacitor C10 acts as a filter [0112]),
a control output (Fig. 3, output of 14) connected to the power consumer and/or the power source (Fig. 3, 12 and 18) for controlling the power consumer and/or the power source [0061] [0063];
wherein the controller is configured to use the divided voltage (Fig. 12, output of D10 is the divided voltage) and a threshold trigger voltage ([0113] “one diode voltage drop”) of the controller ([0113] “one diode voltage drop” is the trigger voltage for the controller to control the output signal, thus consider part “of the controller) for providing a control signal to the power consumer and/or the power source [0061] [0063] at an offset time period being a time period when the divided voltage crosses a threshold trigger voltage previous to or after a zero crossing of the AC voltage (Fig. 12, [0112]-[0114] the capacitor hold the divided voltage until the negative half cycle and the diodes D11-D13 generate a voltage offset that would create time offset to the signal when to turn on or off with respect to the zero crossing of the input AC voltage), for connect or disconnect the power consumer and/or the power source to the AC network [0063].
Regarding claim 2, Elliott discloses the circuit according to claim 1 above, Elliott also discloses an absolute value of the threshold trigger voltage is larger than zero ([0113] “one diode voltage drop”).
Regarding claim 3, Elliott discloses the circuit according to claim 1 above, Elliott also discloses the amplitude of the divided voltage is smaller than the amplitude of the AC voltage (voltage divider in Fig. 12 divides voltage, thus the output voltage is smaller than the input voltage).
Regarding claim 4, Elliott discloses the circuit according to claim 1 above, Elliott also discloses the divided voltage has the same periodicity as the AC voltage (voltage divider in Fig. 12 is a passive/resistive voltage divider, thus no effect on phase or frequency).
Regarding claim 6, Elliott discloses the circuit according to claim 1 above, Elliott also discloses the offset time period is dependent on a control time delay being a sum of all time delays contributing to a total time period for connecting or disconnecting the power consumer and/or the power source to the AC network at the zero crossing of the AC voltage [0120]-[0122].
Regarding claim 7, Elliott discloses the circuit according to claim 1 above, Elliott also discloses the voltage divider is a resistive voltage divider (Fig. 12, R10, R11) [0112] comprising
a first resistor (Fig. 12, R10) connected in series with a second resistor (Fig. 12, R11), wherein a first side of the first resistor (Fig. 12, side of R10 that connected to 115) is connected to the AC network for receiving the AC voltage of the AC network (Fig. 12, line voltage 115) [0073] and a second side of the first resistor (Fig. 12, side of R10 that connected to R11) is connected to a first side of the second resistor (Fig. 12, side of R10 that connected to R11); and wherein
the output of the voltage divider is arranged between the first resistor and the second resistor (Fig. 12, output is connected to D10).
Regarding claim 8, Elliott discloses the circuit according to claim 7 above, Elliott also discloses a second side of the second resistor is configured to receive a DC voltage ([0113] “one diode voltage drop”), and wherein a value of the DC voltage is dependent on an offset time period being a time period when the divided voltage crosses the threshold trigger voltage previous to or after the zero crossing of the AC voltage [0120]-[0122].
Regarding claim 9, Elliott discloses the circuit according to claim 8 above, Elliott also discloses the DC voltage is constant when the offset time period is smaller than an offset threshold time period; or
the DC voltage alternates between a low value and a high value when the offset time period is larger than an offset threshold time period (Fig. 12, in positive cycle has one diode drop through D11 and in negative cycle has two diodes drop through D12 and D13).
Regarding claim 10, Elliott discloses the circuit according to claim 9 above, Elliott also discloses the DC voltage alternates between a low value and a high value, and wherein the DC voltage has a low value when the AC voltage waveform has a negative incline, and a high value when the AC voltage waveform has a positive incline (Fig. 12, in positive cycle has one diode drop through D11 and in negative cycle has two diodes drop through D12 and D13).
Regarding claim 12, Elliott discloses the circuit according to claim 7 above, Elliott also discloses the second side of the second resistor is connected to a DC output of the controller, and wherein the DC output is configured to provide the DC voltage to the voltage dividevoltage drop is an output of the controller, and the diodes are referenced to ground, thus, generate DC voltages).
Regarding claim 13, Elliott discloses the circuit according to claim 7 above, Elliott also discloses
a resistance value of the first resistor is constant and a resistance value of the second resistor is adjustable, or vice versa; or
a resistance value of the first resistor is a first constant value and a resistance value of the second resistor is a second constant value (Fig. 12, R10 and R11 symbols are constant value symbol).
Regarding claim 15, Elliott discloses a method (Fig. 3 and Fig. 12) for providing a control signal connecting or disconnecting (Fig. 3, 12) a power consumer and/or a power source (Fig. 3, 12 and 18) to an AC network (Fig. 3, 20) (Fig. 12, line voltage 115) [0073], the method comprising:
receiving an AC voltage of the AC network (Fig. 3, 20) (Fig. 12, line voltage 115) [0073],
dividing the AC voltage (Fig. 3, 40) and (Fig. 12, R10, R11) [0112] for obtaining a divided voltage of the AC voltage (Fig. 12, output of D10 is also a divided voltage); and
using the divided voltage (Fig. 12, output of D10) and a threshold trigger voltage ([0113] “one diode voltage drop”) of the controller ([0113] “one diode voltage drop” is the trigger voltage for the controller to control the output signal, thus consider part “of the controller) for providing a control signal (Fig. 3, output of 14) to the power consumer and/or the power source (Fig. 3, 12 and 18) for connect or disconnect the power consumer and/or the power source to the AC network when the divided voltage crosses a threshold trigger voltage [0061] [0063], wherein the controller provides the control signal at an offset time period being a time period when the divided voltage crosses the threshold trigger voltage previous to or after a zero crossing of the AC voltage (Fig. 12, [0112]-[0114] the capacitor hold the divided voltage until the negative half cycle and the diodes D11-D13 generate a voltage offset that would create time offset to the signal when to turn on or off with respect to the zero crossing of the input AC voltage, thus the controller output a control signal that offset from the time when the AC voltage crossing zero).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Elliott in view of Price US Patent Publication 20010026159; hereinafter “Price”.
Regarding claim 11, Elliott discloses the circuit according to claim 10 above, Elliott also discloses the high voltage value is dependent on the trigger threshold voltage of the controller (Fig. 12, R10, R11) [0112] [0120]-[0122]. Elliott does not disclose the low voltage value is 0 V. Price discloses a circuit for detecting zero-crossing having a reference at zero volt (Fig. 3, the divider resistor is connected to ground). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to have modified Elliott to incorporate the teaching of Price and have low voltage value is 0 V. Doing so would allow detecting the zero-crossing when the AC voltage waveform has an negative incline without any time offset.
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAI H TRAN whose telephone number is (571)270-0668. The examiner can normally be reached M - F 8:30 - 5:00.
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/THAI H TRAN/Examiner, Art Unit 2836
/REXFORD N BARNIE/Supervisory Patent Examiner, Art Unit 2836
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