DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
USC § 101
Claim 1 is directed to a concrete circuit structure, specifically a thermal
management integrated circuit, and recites a particular arrangement and interconnection of hardware modules and ports. The claim explicitly identifies physical circuit components, including a controllable current source sequence, an analog-to-digital converter (ADC), a register bank with interface and control logic, a clock generator, non-volatile memory, and a local temperature-sensing transistor, and further specifies how these components are electrically connected to one another and to defined external ports (e.g., Aip/Ain ports, PWM port, TACH port, SCL/SDA ports, status indication port, and mater-slave mode port).
Moreover, the claims recite structural relationships at the circuit nodes level, such as an output terminal of the controllable current source being connected to a Vip pin of the ADC, an emitter of the local temperature sensing transistor being connected to the ADC, the base and the collector of the transistor being shorted and grounded, and specific signal paths (e.g., Dtemp and DNTC signals) being provided from the ADC to the register bank and the control logic. These limitations define how the circuit is physically organized and wired, rather than merely describing a desired function or result.
Accordingly, the claim is not directed to an abstract idea, mathematical, or mental process. As such, the claim as a whole is more than a drafting effort designed to monopolize the exception and instead to a specific integrated circuit architecture that implements thermal management functionality through defined hardware modules and electrical interconnections.
Claims 2-14 depend, either directly or indirectly, from claim 1.
Therefore, claims 1-14, are considered to be eligible under 35 USC 101.
Claim Objections
Claims 1-14 are objected to because of the following informalities:
In claim 1, line 2, change “comprising” to -comprising: -
Throughout the claims change “a register bank & interface & control logic module” to - a register bank, interface and control logic module-.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over
Radhakrishnan et al. (Pub. No. US 2022/0320991) (hereinafter Radhakrishnan) in view of Hussain et al. (Patent No. US 6,172,611) (hereinafter Hussain) and further in view of Mays, II (Patent No. US 6,545,438) (hereinafter Mays).
As per claim 1, Radhakrishnan teaches controllable current-based remote temperature sensing techniques, including forcing different currents through a temperature-sensitive device and acquiring temperature information based on corresponding voltage measurements (see ¶¶ [0033]-[0039] and [0082]-[0085], [0084]: “the remote temperature sensor 502 engages a current source 509. The current source 509 includes a high current source 510 and a low current source 512, which are alternately selected by a switch 514 and input to the emitter 182 of the transistor 180 by way of the first node 124”). However, Radhakrishnan does not disclose a thermal management integrated circuit having a resister bank, serial host interface, non-volatile memory, clock generator, Dtemp and DNTC signals of the ADC module are sent to the register bank& interface & control logic module, or fan control and monitoring interfaces.
Hussain, however, discloses a thermal management integrated circuit that receives temperature signals from an external temperature-sensitive element, converts the received analog signals using an analog-to-digital converter, stores temperature data in registers, and communicates with an external host via a two-wire serial bus (SMBus) (see col. 4, lines 18-27, col. 5, lines 28-41, col. 6, lines 20-31 and col. 7, lines 21-32) (examiner notes that SMBus includes a serial clock line (SCL) and a serial line (SDA)). Hussain further describes thermal management that includes “active cooling such as turning on or controlling the speed of a fan”, and provides alert or status outputs indicative of thermal conditions (see col. 4, line 63 through col. 5, line 5). However, Hussain does not disclose circuitry for directly generating pulse-width-modulated fan control signals or monitoring fan speed using a tachometer input.
Hussain further teaches a local temperature sensing element integrated on the thermal management IC, disclosed as an on-chip temperature sensing diode that produces an analog voltage indicative of the local temperature, which is provided to an analog-to-digital converter for conversion in digital temperature data (see col. 4, lines 28-38, i.e., temperature sensing diode 146; ADC 143). As well understood in the art, such an integrated temperature sensing diode is inherently implemented using a bipolar transistor in a diode-connected configuration in which the base and collector are coupled together and the emitter provides the temperature-dependent voltage to the ADC. Hussain further discloses receiving an analog voltage from an external temperature sensing diode remote from the IC and converting both internal and external analog temperature signals into corresponding digital temperature values, which are stored in internal temperature registers (see col. 6, lines 20-46, e.g., INT_TEMP and EXT_TEMP registers). Hussain further teaches that these digital temperature values are accessed by interface and control logic via communication interface (e.g., SMBus) to evaluate thermal conditions and control system operation (see col. 6, line 52 through col. 7, line 5). Thus, Hussain teaches an emitter of a local temperature sensing transistor connected to an ADC module with the base and collector coupled together and grounded, and teaches sending digital temperature signals corresponding to internal and external temperature measurements (Dtemp and DNTC) from the AdC module to a register bank and interface and control logic module.
Mays, however, discloses integrated fan control and monitoring circuitry (see col. 5, lines 33-34), including controlling fan speed using a pulse-width-modulated (PWM) signal and determining fan rotational speed using a tachometer signal (see col. 18, lines 34-49 and col. 22, line 66 through col. 23, line 6), as well as internal control logic and registers for command and status reporting (see col. 4, lines 5-14, i.e., “By sensing the various pulses generated on the tachometer output, the rotational speed of the fan may be determined, and an RPM (revolutions per minute) indication may be computed, or a fault condition, such as a stuck or locked rotor, may also be detected”).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the controllable current-based remote temperature sensing techniques of Radhakrishnan with the thermal management IC architecture of Hussain and the fan control and monitoring circuitry of Mays, because Hussain explicitly teaches that a thermal management includes active cooling by controlling fan speed and discloses a thermal management IC coupled to a two-wire serial bus for host communication, while Mays teaches integrating PWM-based fan speed control and tachometer-based fan speed monitoring as part of fan control circuitry, thereby yielding a single thermal management chip that integrates remote and local temperature acquisition and conversion with external fan control and monitoring.
In particular, Hussain’s SMBus interface (see col. 4, lines 54-62 and col. 8, lines 25-34) corresponds to the claimed SCL (serial clock) and SDA (serail data) ports, and its alert or status outputs correspond to the claimed status indication port, Hussain further teaches remote temperature sensing via an external temperature-sensitive diode coupled to the thermal management IC and conversion of the sensed analog signal using ADC (see col. 4, lines 18-28), corresponding to the claimed ADC input interface (Aip/Ain).
Mays further teaches fan speed control via a pulse-width-modulated signal and fan speed determination via a tachometer signal (see col. 18, lines 34-49 and col. 22, line 66 through col. 23, line 6), corresponding to the claimed PWM and TACH ports for controlling and monitoring an external fan. Mays further discloses fan control circuitry implemented as a powered module (see col. 11, lines 15-19), corresponding to the claimed power supply connection. Finally, Hussain’s host/device communication over SMBus and Mays’s command-and-status (i.e., accept commands and report status) fan control architecture would have made it an obvious design choice to provide a configuration logic for selecting operational modes in multi-device thermal management systems, consistent with the claimed master-slave mode select port.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over
Radhakrishnan in view of Hussain and further in view of Mays and Zanft et al. (WO 2022034091) (hereinafter Zanft).
As per claim 2, the combination of Radhakrishnan, Hussain and Mays teach the system as stated above except for a plurality of sets of Aip ports and Ain ports are arranged in parallel for connecting a plurality of temperature sensing devices.
In particular, while Hussain discloses an analog-to-digital converter configured to receive analog temperature signals via input terminals corresponding to Aip and Ain for a temperature sensing device, the combination does not explicitly disclose providing multiple Aip/Ain input ports arranged in parallel for connecting a plurality of temperature sensing devices.
Zanft, however, discloses thermal management systems that monitor a plurality of temperature sensors using a plurality of respective input ports. For example, Zanft teaches “a controller comprising a processor, a plurality of temperature input ports each communicatively coupled to a respective temperature sensor” and receiving temperature data from each temperature sensor to perform thermal management (see ¶ [0023]). Zanft therefore teaches a desirability of providing multiple independent temperature sensing channels within a thermal management controller. It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to modify the thermal chip taught by the combination of Radhakrishnan, Hussain and Mays to include a plurality of sets of Aip and Ain ports arranged in parallel, each set corresponding to a respective temperature sensing device, because Zanft teaches monitoring multiple temperature sensing devices using respective input ports in a thermal management system and because Hussain already teaches acquiring temperature information using ADC input terminals (Aip/Ain), thereby yielding a predictable extension of known temperature sensing architecture to support multiple temperature sensing devices within a single thermal management chip.
Allowable Subject Matter
Claims 3-14 are objected to as being dependent upon a rejected base claim, but
would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and overcoming the objections made above.
Regarding claim 3, none of the prior art of record teaches or fairly suggests a thermal management system with a built-in interface host, comprising the thermal 11 management chip with the built-in interface host according to claim 1 and further comprising a remote temperature sensing device, a fan unit, and a master-slave mode select switch, wherein the remote temperature sensing device is separately connected to a Vip port and a Vin port of the thermal management chip; the fan unit is separately connected to the PWM port and the TACH port; and the master-slave mode select switch is connected to the master-slave mode select port, in combination with the rest of the claim limitations as claimed and defined by the applicant.
Dependent claims 4-14, depending from claim 3, are objected to as being dependent upon a rejected base claim for the same reasons as in claim 3.
Prior art
The prior art made record and not relied upon is considered pertinent to applicant’s
disclosure:
Wyatt [030] discloses a system and method for thermal management of a memory
device is described. In an embodiment, one or more thermal sensors sends a signal to a thermal control module indicating that a pre-determined temperature threshold for a memory device or devices has been reached. The thermal control module may then begin tracking memory thermals or initiate thermal management operations based on the signal and history of memory device temperatures over time.
Balakrishnan et al. [‘609] discloses a hardware implemented thermal watchdog module that includes a thermal watch dog processor, hardware thermal watchdog firmware, an I2C watchdog, an I2C system management bus, and a dedicated thermal watchdog temperature sensor. The thermal watch dog processor is not the BMC processor where BMC firmware is executed. The thermal watch dog processor is an independent processor where the hardware thermal watchdog firmware is executed. The hardware implemented thermal watchdog module runs independent of BMC thermal management operation. If the BMC thermal management operation fails, or the BMC malfunctions, the hardware thermal watchdog module 601 still can detect the working temperature of the host computer, and shuts down the host computer if the host computer overheats.
Contact information
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to MOHAMED CHARIOUI whose telephone number is (571)272-2213. The examiner can normally be reached Monday through Friday, from 9 am to 6 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Schechter can be reached on (571) 272-2302. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Mohamed Charioui
/MOHAMED CHARIOUI/Primary Examiner, Art Unit 2857