DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
circuit processing module; topological mapping module; in claim 7.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 2, 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Smith et al., Pub. No.: US11010145B1 in view of Gambetta et al., Pub. No.: US20200342344A1.
Regarding claim 1, Smith teaches: A quantum circuit compilation method, for application to a compilation framework comprising a circuit processing module and
(Smith, (col.10 line [46 – 49]), “In some examples, the quantum processor 206 [A quantum circuit compilation method, for application to a compilation framework comprising a circuit processing module] includes a quantum circuit system. The quantum circuit system may include qubit devices, resonator devices and possibly other devices that are used to store and process quantum information.”)
a topological mapping module, and comprising:
(Smith, (col.16 line [27 – 32]), “Such intermediate information may include a number of qubits in the quantum processor 206, availability of quantum gates, types of qubits (e.g., superconducting, tunable, fixed, etc.), topology of the quantum processor 206 [a topological mapping module] (i.e., how the qubits are connected), and coherence times of individual qubits.”)
determining, upon receiving a compilation instruction, a topological structure of a target quantum chip and a supportable logic gate set supported by the target quantum chip according to a configuration file in the compilation instruction;
(Smith, (col.2 line [12 – 23]), “The specification includes information [determining, upon receiving a compilation instruction] about the configuration of a quantum processor. The specification may also include information related to the calibration of the quantum processing system. For example, a specification may include a number of qubit devices in the quantum processor, identification of the types of each qubit, the coherence time of each qubit, topology of the qubit devices within the quantum processor [a topological structure of a target quantum chip], operations that the quantum processor supports, [a supportable logic gate set supported by the target quantum chip according to a configuration file in the compilation instruction] qubit device fidelity, operational fidelity of the quantum processing system, and identification of disabled qubit devices.”)
invoking the circuit processing module to process a to-be-complied circuit so as to generate a first supportable circuit, wherein logic gates in the first supportable circuit all belong to the supportable logic gate set, and
(Smith, (col.16 line [32 – 37]), “The quantum compilation module 300 uses this information [invoking the circuit processing module to process a to-be-complied circuit so as to generate a first supportable circuit] to determine logical operations that can be executed using the quantum processing system 200 [wherein logic gates in the first supportable circuit all belong to the supportable logic gate set]. In some embodiments, the quantum hardware specification 310 additionally includes explicit information about operations supported by the qubits in the quantum processor 206.”)
invoking the topological mapping module to map the first supportable circuit to a first operable circuit according to the topology structure,
(Smith, (col.16 line [32 – 37]), “In some embodiments, the qubit routing module 420 performs qubit allocation rather than qubit routing. Qubit allocation may occur when there are no conflicting allocations and when it is convenient to do a logical physical mapping of a qubit to a particular qubit device [invoking the topological mapping module to map the first supportable circuit to a first operable circuit according to the topology structure].”)
wherein the first operable circuit is a quantum circuit adapted to operate on the target quantum chip; or invoking the topological mapping module to map the to-be-complied circuit to a second operable circuit according to the topology structure,
(Smith, (col.4 line [16 – 21]), “The compiler uses the provided information about the quantum computing system to establish a compilation target (i.e., a set of operations supported by the current configuration of the quantum system to which to translate the program) [wherein the first operable circuit is a quantum circuit adapted to operate on the target quantum chip] and compiles the program using operations that are executable by the quantum system.”)
Smith does not teach:
wherein the second operable circuit is a quantum circuit adapted to operate on the target quantum chip; and invoking the circuit processing module to process the second operable circuit so as to generate a second supportable circuit, wherein logic gates in the second supportable circuit all belong to the supportable logic gate set.
Gambetta teaches:
wherein the second operable circuit is a quantum circuit adapted to operate on the target quantum chip; and invoking the circuit processing module to process the second operable circuit so as to generate a second supportable circuit, wherein logic gates in the second supportable circuit all belong to the supportable logic gate set.
(Gambetta, “[0012] … An embodiment identifies, using a pattern recognition technique, a portion of the first quantum circuit that can be transformed using a first transformation operation to satisfy a constraint on the quantum circuit design. An embodiment transforms, to a second quantum circuit [wherein the second operable circuit is a quantum circuit adapted to operate on the target quantum chip; and invoking the circuit processing module to process the second operable circuit so as to generate a second supportable circuit] according to the first transformation operation, the portion, wherein the first transformation operation comprises reconfiguring a gate in the first quantum circuit [wherein logic gates in the second supportable circuit all belong to the supportable logic gate set] such that a qubit used in the gate complies with the constraint on the quantum circuit design while participating in the second quantum circuit. An embodiment executes, using the quantum computing system, the second quantum circuit.”)
Gambetta and Smith are related to the same field of endeavor (i.e.: adaptive quantum circuit). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teaching of Gambetta with teachings of Smith to add gate transformation technique to enable more efficient satisfaction of hardware constrains (Gambetta, abstract).
Regarding claim 2, Smith in view of Gambetta teach the method of claim 1.
Gambetta further teaches: wherein the circuit processing module comprises a logic gate processing unit, and said "invoking the circuit processing module to process a to-be-complied circuit" comprises: obtaining a logic gate in the to-be-complied circuit or the second operable circuit as a to-be-processed logic gate, and
(Gambetta, “[0012] … An embodiment identifies, using a pattern recognition technique, a portion of the first quantum circuit that can be transformed using a first transformation operation to satisfy a constraint on the quantum circuit design. An embodiment transforms, to a second quantum circuit [obtaining a logic gate in the to-be-complied circuit or the second operable circuit as a to-be-processed logic gate] according to the first transformation operation, the portion, wherein the first transformation operation comprises reconfiguring a gate in the first quantum circuit such that a qubit used in the gate complies with the constraint on the quantum circuit design while participating in the second quantum circuit. An embodiment executes, using the quantum computing system, the second quantum circuit.”)
Smith further teaches: judging whether the to-be-processed logic gate belongs to the supportable logic gate set; and
(Smith, (col.16 line [41 – 49]), “Since the quantum hardware specification 310 may be input to the quantum compilation module 300 at the same time as a program 305, the quantum compilation module 300 can compile executable instructions in a target language (e.g., machine code) for any quantum processor 206, as long as operations needed to execute the program are available and can be determined from information included in the quantum hardware specification 310 [judging whether the to-be-processed logic gate belongs to the supportable logic gate set].”)
invoking the logic gate processing unit to convert the to-be-processed logic gate to a supportable logic gate if the to-be-processed logic gate does not belong to the supportable logic gate set.
(Smith, (col.13 line [17 – 23]), “Control system 202 generates control information (e.g., a digital waveform) that is delivered to the signaling hardware 204 and converted to control signals 208 [invoking the logic gate processing unit to convert the to-be-processed logic gate] (e.g., analog waveforms) for delivery to the quantum processor 206. The digital control information can be generated based on quantum instructions, for example, to execute quantum logic operations, readout operations, or other types of control[to a supportable logic gate if the to-be-processed logic gate does not belong to the supportable logic gate set].”)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the present application to combine the teachings of Gambetta with teachings of Smith for the same reasons disclosed for claim 1.
Regarding claim 7, Smith teaches: A quantum circuit compilation device, wherein the device applies to a compilation framework comprising a circuit processing module and a topological mapping module, and the quantum circuit compilation device comprises:
(Smith, (col.10 line [46 – 49]), “In some examples, the quantum processor 206 [A quantum circuit compilation device, wherein the device applies to a compilation framework comprising a circuit processing module and a topological mapping module, and the quantum circuit compilation device] includes a quantum circuit system. The quantum circuit system may include qubit devices, resonator devices and possibly other devices that are used to store and process quantum information.”)
The rest of the limitations are analogous to claim 1, so are rejected under similar rationale.
Regarding claim 9, Smith in view of Gambetta teach the method of claim 1.
Smith further teaches: An electronic device comprising a memory and a processor, wherein the memory stores a computer program therein, and the processor is configured for running the computer program to execute the method of claim 1.
(Smith, (col.10 line [43 – 46]), “In some instances, all or part of the quantum processor 206 functions as a quantum processor, a quantum memory [wherein the memory stores a computer program therein, and the processor is configured for running the computer program to execute the method of claim 1], or another type of subsystem. In some examples, the quantum processor 206 includes a quantum circuit system.”)
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Smith in view of Gambetta and in further view of Monroe et al., Pub. No.: US11195117B2.
Smith in view of Gambetta teach the method of claim 1.
Smith further teaches: wherein the logic gate processing unit comprises a decomposing subunit and a converting subunit, and said "invoking the logic gate processing unit to convert the to-be-processed logic gate to a supportable logic gate" comprises: when the to-be-processed logic gate is a basic logic gate, invoking the converting subunit to convert the to-be processed logic gate to a supportable logic gate according to a conversion rule in the configuration file; and
(Smith, (col.12 line [50 – 57]), “Generally, the control system 202 can interpret the quantum instructions generated by classical processing system 500 and generate a hardware-specific control sequences configured to execute the operations proscribed by the quantum machine instructions. For example, the control system 202 may generate control information that is delivered to the signaling hardware 204 and converted to control signals that control the quantum processor 206 [when the to-be-processed logic gate is a basic logic gate, invoking the converting subunit to convert the to-be processed logic gate to a supportable logic gate according to a conversion rule in the configuration file].”)
invoking the decomposing subunit to decompose the to-be-processed logic gate to a basic logic gate combination according to a decomposing rule in the configuration file,
(Smith, (col.18 line [16 – 24]), “This process of either exactly decomposing or approximating quantum gates helps to make programs 305 [invoking the decomposing subunit to decompose the to-be-processed logic gate to a basic logic gate combination according to a decomposing rule in the configuration file] portable across different quantum processing systems 200. A program 305 can include any quantum gates as long as the processor 206 for which the quantum compilation module 300 compiles the program 305 can execute quantum gates that can be combined to achieve the same or approximately the same operations as the quantum gates included in the program 305.”)
and invoking the converting subunit to convert every logic gate in the basic logic gate combination to a supportable logic gate according to the conversion rule.
(Smith, (col.17 line [55 – 62]), “Generally, the components of the architecture analysis module 350 convert a sequence of gates used in a program 305 [and invoking the converting subunit to convert every logic gate in the basic logic gate combination to a supportable logic gate according to the conversion rule] into an equivalent or near equivalent sequence of gates that are executable by the quantum processing system 200. (Here a near equivalent sequence of gates refers to a sequence of gates that while not exactly equivalent maintain the integrity of the program to be run such that a useful result can be obtained.)”)
Smith in view of Gambetta do not teach:
when the to-be-processed logic gate is a multi-control logic gate,
Monroe teaches:
when the to-be-processed logic gate is a multi-control logic gate,
(Monroe, (col.1 line 66 – col.2 line 3), “This eliminates the crosstalk between the memory qubits and communication qubits in each ELU module, and attains an optimized multi-mode couplings between trapped ion qubits in modular ELUs for an efficient scaling of the computer architecture [when the to-be-processed logic gate is a multi-control logic gate].”)
Monroe, Smith and Gambetta are related to the same field of endeavor (i.e.: adaptive quantum circuit). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teaching of Monroe with teachings of Smith and Gambetta to enable execution of quantum circuits on scalable quantum computing systems to improve qubit connectivity and hardware capabilities (Monroe, abstract).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Smith in view of Gambetta and in further view of WANG et al., Pub. No.: US20210247329A1.
Smith in view of Gambetta teach the method of claim 1.
Smith further teaches: wherein the circuit processing module further comprises a circuit optimizing unit, and said "invoking the circuit processing module to process the to-be-complied circuit or the second operable circuit" further comprises: determining a to-be-optimized logic gate in the to-be-complied circuit or the second operable circuit according to an optimization condition in the configuration file; and
(Smith, (col.17 line [37 – 42]), “ By optimizing the program 305 and scheduling instructions according to the quantum hardware specifications 310 for individual quantum machines, the compiler backend 330 can produce machine dependent optimizations of the program code that will execute on the differently configured quantum processors 206 [determining a to-be-optimized logic gate in the to-be-complied circuit or the second operable circuit according to an optimization condition in the configuration file].”)
Smith in view of Gambetta do not teach:
invoking the circuit optimizing unit to perform logic gate elimination and/or logic gate merging on the to-be-optimized logic gate according to an optimization rule in the configuration file.
WANG teaches:
invoking the circuit optimizing unit to perform logic gate elimination and/or logic gate merging on the to-be-optimized logic gate according to an optimization rule in the configuration file.
(WANG, “[0033] …The quantum logic can use quantum logic gates (or simply “quantum gates”) to create, remove, or modify qubits [invoking the circuit optimizing unit to perform logic gate elimination and/or logic gate merging on the to-be-optimized logic gate according to an optimization rule in the configuration file]. Mathematically, a quantum gate is a propagator acting on a quantum state. Physically, a quantum gate can be implemented as a hardware device capable of generating laser pulses, electromagnetic waves (e.g., microwave pulses), electromagnetic fields, or any means for changing, maintaining, or controlling the quantum states of the qubits…”)
WANG, Smith and Gambetta are related to the same field of endeavor (i.e.: adaptive quantum circuit). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teaching of WANG with teachings of Smith and Gambetta to improve compiler’s awareness of quantum processor condition to generate more reliable and optimized quantum circuits (WANG, abstract).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Smith in view of Gambetta and in further view of Amy et al., Pub. No.: US10664249B2 and Carter et al., Pub. No.: US11356247B1.
Smith in view of Gambetta teach the method of claim 1.
Smith further teaches: wherein the compilation framework further comprises a circuit equivalence-verifying module, and the method further comprises:
invoking the circuit equivalence-verifying module to judge whether the first supportable circuit and/or the second supportable circuit is/are equivalent to the to-be-complied circuit, and/or to judge whether the first operable circuit and/or the second operable circuit is/are equivalent to the to-be-complied circuit; and
(Smith, (col.2 line [24 – 32]), “The compiler uses information from the specification to customize the instructions in a target language it produces for the quantum processing system. To achieve customization, the compiler may perform a process of gate realization to determine available gates in the quantum processor that can produce equivalent or near equivalent operations to gates that are used in the program logic [invoking the circuit equivalence-verifying module to judge whether the first supportable circuit and/or the second supportable circuit is/are equivalent to the to-be-complied circuit]. The compiler may also perform qubit routing to adjust relative locations of qubit states within the quantum processor.”)
Smith in view of Gambetta do not teach:
generating a warning message of circuit compilation exception
when the first supportable circuit and/or the second supportable circuit and/or the first operable circuit and/or the second operable circuit is/are not equivalent to the to-be-complied circuit.
Carter teaches:
generating a warning message of circuit compilation exception
(Carter, (col. 20 line 65 – col. 21 line 3), “The term “control signal” refers to an electronic alert [generating a warning message of circuit compilation exception], notification, flag, or control signal configured to instruct, or cause, the quantum one-time pad system, or a QC detection system comprised by or in communication with the quantum one-time pad system, to perform an automated process or function without user interactivity.”)
Carter, Smith and Gambetta are related to the same field of endeavor (i.e.: adaptive quantum circuit). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teaching of Carter with teachings of Smith and Gambetta to enable compilation of programs that use entangled qubits and quantum storage resources while maintaining compatibility with that target quantum processor. (Carter, abstract).
Smith in view of Gambetta and Carter do not teach:
when the first supportable circuit and/or the second supportable circuit and/or the first operable circuit and/or the second operable circuit is/are not equivalent to the to-be-complied circuit.
Amy teaches:
when the first supportable circuit and/or the second supportable circuit and/or the first operable circuit and/or the second operable circuit is/are not equivalent to the to-be-complied circuit.
(Amy, (col.7 line [45 – 49]), “Verification of reversible circuits could be considered from the viewpoint of checking equivalence against a benchmark circuit or specification [when the first supportable circuit and/or the second supportable circuit and/or the first operable circuit and/or the second operable circuit is/are not equivalent to the to-be-complied circuit]. Such an approach can double as both program verification and translation validation, but every compiled circuit would need to be verified separately.”)
Amy, Smith, Gambetta and Carter are related to the same field of endeavor (i.e.: adaptive quantum circuit). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teaching of Amy with teachings of Smith, Gambetta and Carter to add reversible circuit compiler and verification techniques to improve correctness and efficiency of generated quantum circuits while reducing ancillary qubit usage. (Amy, abstract).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Smith in view of Gambetta and in further view of Curtis et al., Pub. No.: US10255555B2.
Smith in view of Gambetta teach the method of claim 1.
Smith further teaches: wherein said "invoking the topological mapping module to map the first supportable circuit to a first operable circuit according to the topology structure" comprises: obtaining a logic gate in the first supportable circuit as a target logic gate, and
(Smith, (col.4 line [16 – 21]), “The compiler uses the provided information about the quantum computing system to establish a compilation target (i.e., a set of operations supported by the current configuration of the quantum system to which to translate the program) [obtaining a logic gate in the first supportable circuit as a target logic gate] and compiles the program using operations that are executable by the quantum system.”)
judging whether target operation bits of the target logic gate are adjacent on the target quantum chip according to the topological structure; and
(Smith, (col.9 line [10 – 15]), “In particular, the quantum compilation module 300 determines an appropriate compilation target from information about a given specification of quantum hardware. A system administrator of the quantum cloud system 130 may update quantum hardware specifications associated with the quantum processing system 200.”)
Smith in view of Gambetta do not teach:
if the target operation bits are not adjacent on the target quantum chip, invoking the topological mapping module to swap the target operating bits to neighboring bits so as to map the first supportable circuit to the first operable circuit.
Curtis teaches:
if the target operation bits are not adjacent on the target quantum chip, invoking the topological mapping module to swap the target operating bits to neighboring bits so as to map the first supportable circuit to the first operable circuit
(Curtis, (col.6 line 61 – col.7 line 2), “For instance, the entangling quantum logic operations identified at 302 can be applied without having to perform swap gates with other data qubits [if the target operation bits are not adjacent on the target quantum chip, invoking the topological mapping module to swap the target operating bits to neighboring bits so as to map the first supportable circuit to the first operable circuit], without having to otherwise recompose the quantum logic operation in terms of other data qubits, etc. Accordingly, the entangling quantum logic operations identified at 302 may be considered low-level resources of the quantum information processor, for example, part of the machine-level computational structure of the quantum information processor hardware.”)
Curtis, Smith and Gambetta are related to the same field of endeavor (i.e.: adaptive quantum circuit). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teaching of Curtis with teachings of Smith and Gambetta to add quantum logic control sequence generation to control sequence to reflect the processor’s qubit connectivity and operations. (Curtis, abstract).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Itoko et al., Pub. No.: US11010518B2.
Itoko teaches Swap insertion in mapping logical qubits on a quantum circuit is performed by obtaining an operation sequence including a plurality of operations to be executed on a quantum circuit. The quantum circuit including a plurality of physical qubits and a plurality of couplings.
Greenberg et al., Pub. No.: US10803215B2.
Greenberg teaches detecting submission of a first quantum circuit for compilation, the first quantum circuit comprising a first set of quantum logic gates; generating a first gate index, the first gate index comprising an ordered table of a subset of the set of quantum logic gates, each quantum logic gate of the subset of quantum logic gates including a corresponding set of qubits acted on by the quantum logic gate;
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/M.T.M./ Examiner, Art Unit 2148
/MICHELLE T BECHTOLD/Supervisory Patent Examiner, Art Unit 2148
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