DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 14, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over CN112310044A, of record by Applicant.
Regarding independent claim 1, CN (‘044) teaches in figures 3, 4, and the corresponding text, an array substrate, comprising: a base substrate (10); a plurality of data signal lines (Data 1-4) arranged on the base substrate; a plurality of fan-out lines (41) arranged side-by-side on the base substrate and respectively lapped with the plurality of data signal lines through adapter holes (413, 414); and a first test lead wire (no # but the “L” shaped line at the bottom of part 301) arranged on the base substrate, wherein the first test lead wire comprises a first test pad (301), a first lead wire segment (no # but the long part of the “L”), and a second lead wire segment (short part of the “L”), the first lead wire segment is electrically connected to at least a part of the plurality of fan-out lines (via 411 and 412) and arranged in a same layer as the plurality of fan-out lines, and the second lead wire segment is electrically connected to the first test pad and lapped with the first lead wire segment.
CN (‘044) does not teach the second lead wire segment is electrically connected to the first lead wire segment through an adapter hole.
However, the entire reference teaches the use of adapter holes to connect wires for the purpose allowing automated machinery to hold, align, and process the wires efficiently.
Hence, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to use adaptor holes on CN (‘044) to connect the first lead wire to the second lead wire for the purpose allowing automated machinery to hold, align, and process the wires efficiently.
Regarding dependent claim 2, CN (‘044) teaches the plurality of fan-out lines, and the first lead wire segment and the second lead wire segment are arranged in a same layer and made of a same material.
Regarding dependent claim 3, CN (‘044) teaches the plurality of fan-out lines, the first lead wire segment, and the second lead wire segment are all located in a gate material layer (figure 2 shows the hole in the gate layer).
Regarding dependent claim 6, CN (‘044) teaches a second test lead wire (no # but the “L” shaped line at the bottom of part 302) arranged on the base substrate, wherein the second test lead wire comprises a second test pad (302) and a lead wire (no # but the long part of the “L”), the first lead wire segment is electrically connected to a part of the plurality of fan-out lines, and the lead wire is lapped with another part of the plurality of fan-out lines to the second test pad.
CN (‘044) does not teach the lead wire segment is electrically connected to the first lead wire segment through an adapter hole.
However, the entire reference teaches the use of adapter holes to connect wires for the purpose allowing automated machinery to hold, align, and process the wires efficiently.
Hence, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention to use adaptor holes on CN (‘044) to connect the lead wire to the first lead wire for the purpose allowing automated machinery to hold, align, and process the wires efficiently.
Regarding dependent claim 14, CN (‘044) teaches the array substrate has a display area (100) and a non-display area (202) at least partially surrounding the display area, the non-display area comprises a fan-out area and a test lead wire area, the plurality of fan-out lines are at least partially located in the fan-out area, and the first test lead wire is at least partially located in the test lead wire area.
Regarding dependent claim 19, CN (‘044) teaches a display panel, comprising the array substrate.
Regarding dependent claim 20, CN (‘044) teaches a display device, comprising the display panel.
Allowable Subject Matter
Claim 21 is allowed.
The following is an examiner’s statement of reasons for allowance:
The prior art of record neither shows nor suggest a method for manufacturing an array substrate, comprising: providing a base substrate; forming a plurality of data signal lines, a plurality of fan-out lines, and a first test lead wire on the base substrate, wherein the first test lead wire comprises a first test pad, a first lead wire segment, and a second lead wire segment, the first lead wire segment is electrically connected to at least part of the plurality of fan-out lines and arranged in a same layer as the plurality of fan-out lines, the second lead wire segment is electrically connected to the first test pad, the first lead wire segment is not electrically connected to the second lead wire segment; forming an insulating structure on a side of the plurality of data signal lines, the plurality of fan-out lines, and the first test lead wire away from the base substrate; forming adapter holes running through the insulating structure, at locations where the plurality of fan-out lines and the plurality of signal data lines are adjacent to each other, and at locations where the first lead wire segment and the second lead wire segment are adjacent to each other; and forming a conducting layer on a side of the insulating structure away from the base substrate, so that the conducting layer implements, through the adapter holes, lapping between the plurality of fan-out lines and the plurality of data signal lines, and lapping between the first lead wire segment and the second lead wire segment.
Claims 4, 5, 7-13, 15, 16, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2022/0406875 teaches the state of the art of using adapter holes to connect wires.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH L WILLIAMS whose telephone number is (571)272-2465. The examiner can normally be reached M-Th 6:30 AM- 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JAMES R. GREECE can be reached at (571) 272-3711. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JOSEPH L. WILLIAMS
Primary Examiner
Art Unit 2875
/JOSEPH L WILLIAMS/ Primary Examiner, Art Unit 2875