DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, 7, 9, 10, & 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zak et al. (WIPO Application Publication # WO2019/086058A1).
Regarding Claim 1, Zak discloses a current damper for a voltage transformer (i.e. transformers Tr_1 & Tr_2), comprising:
a first section (i.e. protective circuit 3) comprising at least one pair of diodes (i.e. diodes 14/15) arranged in an anti-parallel configuration;
a second section (i.e. limiting impedance 5) arranged parallel to the first section, and comprising at least one capacitor (i.e. capacitor C); and
the first section and the second section being configured to be coupled between a neutral connection (i.e. neutral point 1) of the voltage transformer and a ground potential (i.e. ground 2),
a capacitance of the at least one capacitor being dimensioned such that a voltage drop (i.e. voltage loss Uz between neutral point 1 & ground 2) of an AC current (i.e. current I0AC) from the neutral connection at the at least one capacitor is lower than a forward threshold voltage (i.e. minimum voltage UD necessary for opening the diode in a forward direction) of the diodes of the at least one pair of diodes (Fig. 1, 7; Abstract; Page 2, line 23-Page 5, line 25; Page 8, line 21-28; Page 9, line 7-Page 10, line 11; Page 18, line 4-28). Zak states that, when designing the value of capacity of the capacitor C, it is necessary to consider the required value of a voltage loss in the capacitor C. Thus, the capacitance of capacitors C is selected or dimensioned according to the required voltage drop/loss between a neutral point 1 and a ground 2. As stated in Zak, for the function of this circuit, the value of the voltage UD, which is the catalogue value of the minimum voltage necessary for the opening of a specifically used diode 14 in forward direction, is of key importance. If the amplitude of the voltage Uz is lower than n.UD, the diodes 15 will be closed during regular operating condition and will conduct current. Upon increasing the instantaneous value of the voltage Uz above the value n.UD, the diodes 15 will automatically close in reverse direction. Only the UD voltage will be present on individual diodes 14 in reverse direction, i.e. the voltage of the 14 diode in forward direction. After the current passes through zero, the opened diodes 15 will automatically close due to a change in the current direction. If an increase in the instantaneous value of the voltage Uz above the value n.UD occurs within the next half-cycle, the diodes connected in antiparallel 15 that were in the previous half-cycle in reverse direction will open.
Regarding Claim 3, Zak discloses that the transformer is a medium or high voltage transformer (i.e. transformers Tr_1 & Tr_2) (Page 1, line 15-20; Page 8, line 27-31; Page 20, line 10-11). The transformers are part of a high voltage network.
Regarding Claim 4, Zak discloses that the first section comprises a plurality of pairs of diodes (i.e. at least one pair of diodes 14/15 connected in antiparallel) (Fig. 1, 7; Page 2, line 23-Page 5, line 25; Claim 8).
Regarding Claim 5, Zak discloses that the diodes of each pair of diodes (i.e. at least one pair of diodes 14/15 connected in antiparallel) are arranged in an anti-parallel configuration (Fig. 1, 7; Page 2, line 23-Page 5, line 25; Claim 8).
Regarding Claim 7, Zak discloses that the at least one pair of diodes has a forward threshold voltage (i.e. minimum voltage UD necessary for opening the diode in a forward direction) of 0.5-1.2 V (i.e. 0.6-0.7 V) (Page 18, line 4-28).
Regarding Claim 9, Zak discloses a system for current damping comprising a plurality of current dampers (i.e. “n” pairs of diodes 14/15 connected in series) according to claim 1, wherein the plurality of current dampers is configured to be coupled in series between a neutral connection of the voltage transformer and a ground potential (Fig. 7; Page 18, line 1-28).
Regarding Claim 10, Zak discloses a medium voltage or high voltage transformer (i.e. transformers Tr_1 & Tr_2) comprising a current damper according to claim 1 (Page 1, line 15-20; Page 8, line 27-31; Page 20, line 10-11). The transformers are part of a high voltage network.
Regarding Claim 19, Zak discloses a medium voltage or high voltage transformer (i.e. transformers Tr_1 & Tr_2) comprising a system according to claim 9 (Page 1, line 15-20; Page 8, line 27-31; Page 20, line 10-11). The transformers are part of a high voltage network.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 8, 13, & 14 are rejected under 35 U.S.C. 103 as being unpatentable over Zak et al. (WIPO Application Publication # WO2019/086058A1).
Regarding Claim 2, Zak does not explicitly disclose that the AC current from the neutral connection is below 100 A. However, Zak states that said AC current (i.e. current I0AC) from the neutral point/connection is limited by the invention by using a limiting impedance comprising a capacitor. It would have been obvious to one skilled in the art to select a limiting impedance to limit an AC current from the neutral connection below 100 A, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). It has also been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding Claim 8, Zak discloses that the second section comprises a plurality of capacitors (i.e. capacitors C) (Page 9, line 7-Page 10, line 11).
Zak does not explicitly disclose that the plurality of capacitors is particularly arranged in parallel. However, Zak states that the capacitance of the capacitors C is particularly used in the limiting impedance and is selected or dimensioned according to the required voltage drop/loss between a neutral point 1 and a ground 2. It is also well known in the art to connect capacitors in parallel in order to increase the total capacitance since the capacitances of each capacitor are added together to obtain said total capacitance. Therefore, it would have been obvious to one skilled in the art to connect the capacitors C in parallel in order to effectively increase the capacitance according to the required voltage drop/loss between a neutral point 1 and a ground 2.
Regarding Claim 13, Zak discloses that the AC current from the neutral connection is below 50 A. However, Zak states that said AC current (i.e. current I0AC) from the neutral point/connection is limited by the invention by using a limiting impedance comprising a capacitor. It would have been obvious to one skilled in the art to select a limiting impedance to limit an AC current from the neutral connection below 50 A, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). It has also been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding Claim 14, Zak discloses that the AC current from the neutral connection is below 25 A. However, Zak states that said AC current (i.e. current I0AC) from the neutral point/connection is limited by the invention by using a limiting impedance comprising a capacitor. It would have been obvious to one skilled in the art to select a limiting impedance to limit an AC current from the neutral connection below 25 A, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). It has also been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claims 6, 11, 12, 15-18, & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zak et al. (WIPO Application Publication # WO2019/086058A1) in view of Schmidt et al. (European Patent Application Publication # EP3739712A1).
Regarding Claim 6, Zak discloses that the current damper is a DC current damper (Abstract; Page 8, line 21-Page 10, line 11; Claim 3). The limiting impedance is connected between the neutral point 1 of the network and ground 2 to limit the flow of the direct current (i.e. current IDC) through the neutral point 1 of the network.
Zak does not explicitly disclose that the DC current damper is particularly configured to block DC current up to 2 A.
Although Zak is silent on a specific DC current value which is blocked, it would have been obvious to one skilled in the art to select a limiting impedance and a pair of diodes to limit or block a DC current up to 2 A, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). It has also been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Alternatively, Schmidt teaches that the DC current damper is particularly configured to block DC current up to 2 A (Paragraph 0013, 0030, 0041). It would have been obvious to one skilled in the art to configure the DC current damper of Zak to block DC current up to 2 A, as taught by Schmidt, in order to prevent losses and noise.
Regarding Claim 11, Zak does not explicitly disclose a medium voltage or high voltage switchgear comprising a current damper according to claim 1.
Schmidt teaches a medium voltage or high voltage switchgear comprising a current damper according to claim 1 (Paragraph 0001, 0020, 0021, 0036).
Schmidt teaches that it is well known in the art to use a current damper such as the one disclosed by Zak in a medium voltage or high voltage switchgear in order to mitigate the effects of small and medium DC currents. It would have been obvious to use the current damper of Zak in a medium voltage or high voltage switchgear, as taught by Schmidt, in order to mitigate the effects of small and medium DC currents.
Regarding Claim 12, Zak does not explicitly disclose a medium voltage or high voltage switchgear comprising a medium voltage or high voltage transformer according to claim 10.
Schmidt teaches a medium voltage or high voltage switchgear comprising a medium voltage or high voltage transformer according to claim 10 (Paragraph 0001, 0020, 0021, 0036).
Schmidt teaches that it is well known in the art to use a transformer w/ a current damper such as the one disclosed by Zak in a medium voltage or high voltage switchgear in order to mitigate the effects of small and medium DC currents. It would have been obvious to use a transformer w/ a current damper such as the one disclosed by Zak in a medium voltage or high voltage switchgear, as taught by Schmidt, in order to mitigate the effects of small and medium DC currents.
Regarding Claim 15, Zak discloses that the current damper is a DC current damper (Abstract; Page 8, line 21-Page 10, line 11; Claim 3). The limiting impedance is connected between the neutral point 1 of the network and ground 2 to limit the flow of the direct current (i.e. current IDC) through the neutral point 1 of the network.
Zak does not explicitly disclose that the DC current damper is particularly configured to block DC current up to 5 A.
Although Zak is silent on a specific DC current value which is blocked, it would have been obvious to one skilled in the art to select a limiting impedance and a pair of diodes to limit or block a DC current up to 5 A, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). It has also been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Alternatively, Schmidt teaches that the DC current damper is particularly configured to block DC current up to 5 A (Paragraph 0013, 0030, 0041). It would have been obvious to one skilled in the art to configure the DC current damper of Zak to block DC current up to 5 A, as taught by Schmidt, in order to prevent losses and noise.
Regarding Claim 16, Zak discloses that the current damper is a DC current damper (Abstract; Page 8, line 21-Page 10, line 11; Claim 3). The limiting impedance is connected between the neutral point 1 of the network and ground 2 to limit the flow of the direct current (i.e. current IDC) through the neutral point 1 of the network.
Zak does not explicitly disclose that the DC current damper is particularly configured to block DC current up to 10 A.
Although Zak is silent on a specific DC current value which is blocked, it would have been obvious to one skilled in the art to select a limiting impedance and a pair of diodes to limit or block a DC current up to 10 A, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). It has also been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Alternatively, Schmidt teaches that the DC current damper is particularly configured to block DC current up to 10 A (Paragraph 0013, 0030, 0041). It would have been obvious to one skilled in the art to configure the DC current damper of Zak to block DC current up to 10 A, as taught by Schmidt, in order to prevent losses and noise.
Regarding Claim 17, Zak discloses that the current damper is a DC current damper (Abstract; Page 8, line 21-Page 10, line 11; Claim 3). The limiting impedance is connected between the neutral point 1 of the network and ground 2 to limit the flow of the direct current (i.e. current IDC) through the neutral point 1 of the network.
Zak does not explicitly disclose that the DC current damper is particularly configured to block DC current up to 20 A.
Although Zak is silent on a specific DC current value which is blocked, it would have been obvious to one skilled in the art to select a limiting impedance and a pair of diodes to limit or block a DC current up to 20 A, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). It has also been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Alternatively, Schmidt teaches that the DC current damper is particularly configured to block DC current up to 20 A (Paragraph 0013, 0030, 0041). It would have been obvious to one skilled in the art to configure the DC current damper of Zak to block DC current up to 20 A, as taught by Schmidt, in order to prevent losses and noise.
Regarding Claim 18, Zak does not explicitly disclose that the at least one pair of diodes has a forward threshold voltage of 0.8 V.
Schmidt teaches that the at least one pair of diodes has a forward threshold voltage (i.e. threshold voltage Vto) of 0.8 V (Paragraphs 0018, 0035, 0046, 0050).
Schmidt teaches that it is well known for power diodes to have a threshold voltage of 0.8 V. It would have been obvious to one skilled in the art to use diodes with a forward threshold voltage of 0.8 V in Zak, as taught by Zak, in order to increase the limit voltage at which the diodes will close and conduct current.
Regarding Claim 20, Zak does not explicitly disclose a medium voltage or high voltage switchgear comprising a system according to claim 9.
Schmidt teaches a medium voltage or high voltage switchgear comprising a system according to claim 1 (Paragraph 0001, 0020, 0021, 0036).
Schmidt teaches that it is well known in the art to use a system such as the one disclosed by Zak in a medium voltage or high voltage switchgear in order to mitigate the effects of small and medium DC currents. It would have been obvious to use the system of Zak in a medium voltage or high voltage switchgear, as taught by Schmidt, in order to mitigate the effects of small and medium DC currents.
Response to Arguments
Applicant's arguments filed 10/23/2025 have been fully considered but they are not persuasive. The Applicant argues that Zak does not teach or suggest a relationship between the AC voltage drop across the capacitor and the forward voltage of the diode pair as recited in claim 1. The Examiner respectfully disagrees. As stated above, Zak states that, when designing the value of capacity of the capacitor C, it is necessary to consider the required value of a voltage loss in the capacitor C. Thus, the capacitance of capacitors C is selected or dimensioned according to the required voltage drop/loss between a neutral point 1 and a ground 2. As stated in Zak, for the function of this circuit, the value of the voltage UD, which is the catalogue value of the minimum voltage necessary for the opening of a specifically used diode 14 in forward direction, is of key importance. If the amplitude of the voltage Uz is lower than n.UD, the diodes 15 will be closed during regular operating condition and will conduct current. Upon increasing the instantaneous value of the voltage Uz above the value n.UD, the diodes 15 will automatically close in reverse direction. Only the UD voltage will be present on individual diodes 14 in reverse direction, i.e. the voltage of the 14 diode in forward direction. After the current passes through zero, the opened diodes 15 will automatically close due to a change in the current direction. If an increase in the instantaneous value of the voltage Uz above the value n.UD occurs within the next half-cycle, the diodes connected in antiparallel 15 that were in the previous half-cycle in reverse direction will open. Furthermore, the Applicant admits that the topology taught by Zak in at least Fig. 7 resembles the damper of Claim 1. Two equivalent electronic/electrical topologies or circuits would perform the same function when used in a similar application. Therefore, one skilled in the art would expect the topology of Zak would perform said function in an equivalent way to the one claimed.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RHADAMES J ALONZO MILLER whose telephone number is (571)270-7829. The examiner can normally be reached Mon-Fri 10am-6pm PST.
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/RJA/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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