DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 6, 12, 16 and 17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Watanabe, US 2015/0263239.
Regarding Claim 1, Watanabe teaches a component comprising a carrier 7, at least one semiconductor chip LED 1, an intermediate layer 43 and a cover layer 49, wherein
- the semiconductor chip 1, the intermediate layer 43 and the cover layer 49 are arranged on the carrier 7,
- the cover layer 49 has at least one cavity (Fig. 13) wherein the semiconductor chip 1 is arranged,
- the intermediate layer 43 is electrically insulating (paragraph 48) and is arranged in regions along the vertical direction between the carrier 7 and the cover layer 49,
- the intermediate layer 43 extends along lateral direction into the cavity (Fig. 13)) and adjoins the semiconductor chip 1, and
- the cover layer 49 has a vertical height (Fig. 13) that varies depending on the lateral positions of the cover layer 49 and has a reduced vertical height (Fig. 13, regions 42 and 43 ) at the positions of the intermediate layer 43 with reference to Fig. 13 in paragraphs 63 and 64.
Regarding Claim 2, Watanabe teaches wherein the intermediate layer 43 completely surrounds the semiconductor chip 1 in lateral directions with reference to Figs. 25A, 22B, 25C in paragraphs 73 and 77.
Regarding Claim 3, Watanabe teaches the intermediate layer (43 in Fig. 13); has a lateral width (Fig. 13) which is larger than a lateral width of the semiconductor chip 1, the intermediate layer 43 enclosing the semiconductor chip 1 in lateral directions with reference to Fig. 13.
Regarding Claim 4, Watanabe teaches wherein the intermediate layer 43 has a lateral width smaller than a lateral width of the semiconductor chip 1, the intermediate layer 43 only partially covering a side surface of the semiconductor chip 1 with reference to Fig. 13.
Regarding Claim 5, Watanabe teaches semiconductor chip 1 has a front side facing away from the carrier 7 and terminating flush with the intermediate layer 43 in the vertical direction with reference to Fig. 13.
Regarding Claim 6, Watanabe teaches has a reflection layer 49c, 49d formed on inner walls of the cavity with reference to Fig. 13, the cavity consisting of the space for the semiconductor chip 1, phosphor 42 and between the inner sidewalls of
49c and 49d in Fig. 13, the reflection layer (49c and 49d) being formed from an electrically insulating material (resin) in paragraphs 48 and 63 – 65.
Regarding Claim 12, Watanabe teaches carrier 7, 5 has a main body 7, through contacts 5c, inner terminal layers 5a and 5b and outer terminal layers 5d, wherein
- the inner terminal layers 5a and the outer terminal layers 5d are arranged on opposite surfaces of the main body 7,
- the through contacts 5c extend through the main body 7, and
- the through contacts 5c each electrically connect one of the inner terminal layers (5a,b) to one of the outer terminal layers 5d with reference to Fig. 13.
Regarding Claim 16, Watanabe teaches a method for producing a component comprising a carrier 7, at least one semiconductor chip 1, an intermediate layer 3 and a cover layer 9, Fig. 11, the method comprising the following
steps:
- arranging the semiconductor chip 1 on the carrier 7;
- applying the intermediate layer (3 in figure 7C; 43 in figure 13) to the carrier 7, wherein the intermediate layer 3,43 laterally adjoins the semiconductor chip 1; and
- applying the cover layer (9 in figure 7D; 49 in figure 13) to the intermediate layer 3 and to the carrier 7, wherein
- at least one cavity (figure 7D; cavity consisting of the space for the semiconductor chip 1, phosphor 2; 42 in Fig. 13 and between the inner sidewalls of 9; 49 in Fig 13 is formed in the cover layer (9, 49 in Fig. 13), in which the semiconductor chip 1 is arranged,
- the intermediate layer (3; 43 Fig. 13) is embodied such that it is electrically insulating and is arranged
regionally between the carrier 7 and the cover layer (9, 49 in Fig. 13) along the vertical direction,
the intermediate layer (3; 43 in Fig. 13) extends into the cavity (figure 7D; cavity consisting of the space for the semiconductor chip 1, phosphor 2 and between the inner sidewalls of 9 along the lateral direction, and
- the cover layer (9; 49 in Fig. 13) has a vertical height (Fig. 7D) which varies depending on the lateral positions of the cover layer (9, 49 in Fig. 13) and has a reduced vertical height (in the boundary region at 2/3 in Fig 7D; 42/43 in Fig. 13) at the positions of the intermediate layer 3 with references to Figs. 1 – 14 throughout the disclosure.
Regarding Claim 17, Watanabe teaches semiconductor chip 1 is electrically wired (Figs, 7 A-B) before the cover layer (9 in Fig. 7D) is applied to the intermediate layer 3) and to the carrier 7 with references to Fig. 7.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7, 8, 13 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe, US 2015/0263239 in view of Suehiro, US 2003/0201451.
Regarding Claim 7, Watanabe teaches a reflection layer 49c and 49d formed on inner walls of the cavity (Fig. 13), but fails to teach the reflective layer being formed of an electrically conductive material.
Suehiro teaches that in addition to the transparent sealing material for sealing light emitting element other transparent silicone resin as used by Watanabe can be used and also highly reflective metallic reflecting surface (electrically conductive can be used ) in paragraphs 52 and 53 for the benefit of providing high reflectance in paragraphs 67 – 70.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Watanabe and form the reflective layer of an electrically conductive material for the benefit of providing high reflectance as taught by Suehiro in paragraphs 67 – 70.
Regarding Claim 8, Watanabe teaches reflection layer is electrically insulated from the semiconductor chip with reference to Fig. 13 in paragraphs 48 and 63 – 65.
Regarding Claim 13, Watanabe teaches using silicone or epoxy resins which are transparent materials. Suehiro teaches use of light transparent materials for sealing in paragraph 52.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Watanabe and form the intermediate layer from a radiation – transmitting (visible light) material for the benefit of using light transparent materials for sealing as taught by Suehiro in paragraph 52.
Claim(s) 9 – 11 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe, US 2015/0263239 in view of Weidner, US 2013/0307004.
Regarding these claims, Watanabe fails to teach the component comprises a first contact layer and a second contact layer for electrically contacting the semiconductor chip, wherein – the intermediate layer is arranged along the vertical direction in regions between the first contact layer and the second contact layer, and and the intermediate layer electrically insulates the first contact layer from the second contact layer (Claim 9); wherein - the semiconductor chip partially covers the first contact layer (51) in top view, - the first contact layer has at least one subregion which, in top view, protrudes laterally from the semiconductor chip and - the subregion is at least partially or completely covered by the intermediate layer in top view (Claim 10) and wherein the semiconductor chip is arranged in the vertical direction between the first contact layer and the second contact layer, and wherein the second contact layer is arranged on a front side of the semiconductor chip facing away from the carrier and covers the front side at least partially or completely (Claim 11) and wherein a planar contact layer is formed on a front side of the intermediate layer facing away from the carrier for electrically wiring the semiconductor chip.
Weidner teaches a component for LED packaging wherein it has a first contact layer 2 and a second contact layer 7 for electrically contacting the
semiconductor chip 4, wherein
- the intermediate layer 8 is arranged regionally between the first contact layer 2 and the second contact layer 7 along the vertical direction, and
- the intermediate layer 8 electrically insulates the first contact layer 2 from the second contact layer 7 with reference to Fig. 1; the semiconductor chip 4 partly covers the first contact layer 2 in plan view,
- the first contact layer 2 has at least one partial region (Fig. 1) which projects laterally from the semiconductor chip 4 in plan view, and
- the partial (subregion) region is at least partly or completely covered by the intermediate layer (8) in plan view; semiconductor chip 4 is arranged between the first contact layer 2 and the second contact layer 7 in the vertical direction, wherein the second contact layer 7 is arranged on a front side 8 of the semiconductor chip 4 facing away from the carrier 3 and at least partly or completely covers the front side with references to Figs. 1 – 4 in paragraphs 38 – 64 for the benefit of producing a component with improved radiation efficiency in paragraph 4.
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Watanabe and provide the contact layers in relation to the intermediate layer and the chip as enumerated in claims 9 – 11 and 18 for the benefit of producing a component with improved radiation efficiency as taught by Weidner in paragraph 4.
Regarding Claim 19, the limitations have been discussed earlier in rejecting Claims 1 and 13.
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe, US 2015/0263239.
Regarding Claim 14, Watanabe teaches the semiconductor chip has a vertical height, - the cavity has a vertical depth with reference to Fig. 13, but fails to teach
a ratio of vertical depth to vertical height from 2 to 20.
However, given the substantial teaching of Watanabe, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to judiciously adjust and control these parameters during the formation of the packaged product component through routine experimentation and optimization to achieve optimum benefits (see MPEP 2144.05) and it would not yield any unexpected results.
Note that the specification contains no disclosure of either the critical nature of the claimed processes or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen methods or upon another variable recited in a claim, the Applicant must show that the chosen methods or variables are critical (Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir., 1990)). See also In re Aller, Lacey and Hall (10 USPQ 233 – 237) “It is not inventive to discover optimum or workable ranges by routine experimentation”.
Regarding Claim 15, Watanabe fails to teach the component comprising a plurality of semiconductor chips, wherein the cover layer has a plurality of cavities and at least one or exactly one of the semiconductor chips is arranged in each of the cavities (40) whose inner walls are provided with a reflective layer.
However, given the substantial teaching of Watanabe, it would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to design an array of the LEDs to produce fixtures with robust illuminating capacities.
Conclusion
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/ASOK K SARKAR/Primary Examiner, Art Unit 2891 December 17, 2025