Prosecution Insights
Last updated: October 01, 2026
Application No. 18/287,948

FLUIDIC TRANSISTORS AND USES THEREOF

Non-Final OA §102§103§112
Filed
Oct 23, 2023
Priority
Apr 23, 2021 — provisional 63/178,672 +1 more
Examiner
HERON, VELVET ELIZABETH
Art Unit
1798
Tech Center
1700 — Chemical & Materials Engineering
Assignee
THE GENERAL HOSPITAL Corporation
OA Round
1 (Non-Final)
47%
Grant Probability
Moderate
1-2
OA Rounds
10m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 47% of resolved cases
47%
Career Allowance Rate
9 granted / 19 resolved
-17.6% vs TC avg
Strong +53% interview lift
Without
With
+52.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
32 currently pending
Career history
68
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
49.5%
+9.5% vs TC avg
§102
29.0%
-11.0% vs TC avg
§112
18.8%
-21.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 19 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Claims 2-3,5-8,10,13-14,17,19-20,23-24,28 and 63-69 in the reply filed on 06/5/2026 is acknowledged. Election was made without traverse in the reply filed on 03/05/2025. Claims 2-3,5-8,10,13-14,17,19-20,23-24,28 and 63-69 are pending examination in this response. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 64 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 64 recites “at least one of the fluidic transistors, wherein a gate region of the fluidic transistor” in line 3. This limitation is indefinite since it is unclear whether “a gate region” is associated with “at least one of the fluidic transistors” of the fluidic amplifier in claim 64 or the “one or more fluidic transistors” in claim 23. The limitation will be interpreted as “wherein a gate region of the at least one of the fluidic transistors Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 2-3,5-8,10,13-14,17,20,23-24,28 and 63-69 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Esfandyarpour et. al. (US 20190226021). Regarding claim 23, Esfandyarpour teaches “A fluidic network comprising;” (Para [0006], [0006] The embodiments described herein relate to systems and methods for extracting, amplifying and sequencing polynucleotides.) “one or more fluidic transistors” (Para [0154] As in FIG. 20, a microfluidic device 2000 ), “each fluidic transistor comprising: a flow region” (Para [0154], fluidic channels 2004 and fluidic channels 2104, shown in Fig.21) configured to transport a first fluid; ( para [0154], Fluids may be introduced through said ports 2006 to fluidic channels 2004.) a gate region (Para [0154], fluidic channels 2004 fluidic channels 2104 noted as lighter channels in which 2008 are within in fig. 20 and shown in Fig.21)) configured to contain a second fluid; (Para [0154], Fluids may be introduced through said ports 2006 to fluidic channels 2004) and a deformable region disposed between the flow and gate regions (Para [0154], valves 2008. Shown in Fig. 20 between the lighter and darker channels), wherein the deformable region is configured to induce flow-limitation as the first fluid is transported within the flow region. (Para [0154], Pressurizing the control lines 2002, deforms a wall between the control lines 2002 and the fluidic channels 2004, pinching off the fluidic channel and closing the valve 2008). Regarding claim 2, Esfandyarpour teaches all of claim 23 as above in addition to “wherein for at least one of the fluidic transistors, a deformation of the deformable region induces the flow- limitation of the first fluid in the flow region; (Para [0154], 0154] As in FIG. 20, a microfluidic device 2000 may have one or more input or output ports 2006. Fluids may be introduced through said ports 2006 to fluidic channels 2004. Control lines 2002 may control the flow of fluids through the activation of valves 2008. Pressurizing the control lines 2002, deforms a wall between the control lines 2002 and the fluidic channels 2004, pinching off the fluidic channel and closing the valve 2008.)” or wherein the deformable region is configured to provide the first fluid at a velocity that is at or faster than a characteristic propagation velocity for the flow region.” (this is not required as its “or”). Regarding claim 3, Esfandyarpour teaches all of claim 23 as above. The recitation “wherein an intrinsic gain of at least one of the fluidic transistors is greater than one.” is capability of the fluidic transistor. Esfandyarpour discloses the positively claimed structural elements of the at least one of the fluidic transistors as claimed, such at least one of the fluidic transistors are said to be fully capable of the recited adaption in as much as recited and required herein. Regarding claim 5, Esfandyarpour teaches all of claim 23 as above in addition to “wherein for at least one of the fluidic transistors, the flow region is disposed above or below the gate region, or wherein the flow region is disposed beside the gate region.” (channels within Fig. 20 and Fig. 21) Regarding claim 6, Esfandyarpour teaches all of claim 23 as above in addition to “wherein for at least one of the fluidic transistors, the flow region comprises a characteristic dimension from about 10 nm to about 1 mm and/or a cross-sectional area of about 100 nm2 to about 1 mm2.” (Para [0155], The microfluidic channels may be in the range of 1 to 100 μm in diameter, or in certain embodiments, in the range of 10 to 20 μm in diameter.). Regarding claim 7, Esfandyarpour teaches all of claim 23 as above in addition to “wherein for at least one of the fluidic transistors, the deformable region comprises a flexural rigidity of about 10-23 J to 10-3 J, a Young's modulus of about 100 kPa to about 500 GPa, and/or a Poisson ratio of about 0.2 to about 0.5.” (Para [0149], (Para [0149], sieve valve). It is known in the art that sieve valves have a Poisson ratio of about 0.2 to about 0.5 and therefore having a sieve valve discloses the claimed feature. Regarding claim 8, Esfandyarpour teaches all of claim 23 as above in addition to “wherein for at least one of the fluidic transistors, the deformable region comprises an elastomer, a silicon oxide, a thin metal layer, a thin polymer layer, a silicon layer, or a combination thereof.” (Para [0124], polydimethylsiloxane PDMS valves). Therefore, the deformable region comprises an elastomer. Regarding claim 10, Esfandyarpour teaches all of claim 23 as above in addition to “wherein at least one of the fluidic transistors further comprises: a flow channel comprising an inlet serving as a source” (Para [0154], control lines 2002, The microfluidic device can control the “injection” or flow of the beads, reagents and/or samples described herein by a series of control lines that intersect with and/or impede upon the microfluidic channels described herein.) and an outlet serving as a drain, (Para [0131], fig. 18a-b A first fluidic input 1811A allows the injection of mixed beads. A second inlet 1812A allows the injection of a buffer solution without beads. A first outlet 1811B may be downstream from the first inlet 1811A. A second outlet 1812B may be downstream from the second inlet 1812A. Fluids may be brought into or out of the module through ports 1809. The fluidic system may have a substrate 1802, and a channel 1810 formed in a layer of PDMS 1808 glass or other material.) wherein the flow region is disposed within the flow channel and (Para [0149],The control channels can, for example, be defined by a side wall that also defines a portion of the microfluidic channel); “wherein the flow channel is configured to transport the first fluid from the source to the drain; (Paras [0154], [0131], and [0149] above); and a gate channel comprising an inlet and an outlet, Para [0131], [0154], and Fig. 18a-b, control lines 2002, The microfluidic device can control the “injection” or flow of the beads, reagents and/or samples described herein by a series of control lines that intersect with and/or impede upon the microfluidic channels described herein. A first fluidic input 1811A allows the injection of mixed beads. A second inlet 1812A allows the injection of a buffer solution without beads. A first outlet 1811B may be downstream from the first inlet 1811A. A second outlet 1812B may be downstream from the second inlet 1812A. Fluids may be brought into or out of the module through ports 1809. The fluidic system may have a substrate 1802, and a channel 1810 formed in a layer of PDMS 1808 glass or other material.)) wherein the gate region is disposed within the gate channel (Para [0149],The control channels can, for example, be defined by a side wall that also defines a portion of the microfluidic channel); and wherein the gate channel is configured to confine the second fluid between the inlet and the outlet of the gate channel. (Para [0154], As shown in FIG. 24 and described above, the control lines can be expanded to retain the solution and/or beads within a predetermined portion of the device.) Regarding claim 13, Esfandyarpour teaches all of claim 10 as above in addition to “wherein for at least one of the fluidic transistors, a cross-section of the flow channel and/or a cross-section of the gate channel varies in the direction of flow to create a contracting taper, an expanding taper, or another geometrical volume.” (Para [0147], Moreover, the size and/or geometry of the microfluidic channel 1922 (e.g., cross-sectional shape, aspect ratio or the like) can be selected such that the movement of the DNA within the microfluidic channel 1922 and in contact with the fragmentation beads 1924 produces the desired shearing of the DNA. The microfluidic channel can have any suitable shape, such as semi-circular, oval, tapered or the like). Regarding claim 14, Esfandyarpour teaches all of claim 23 as above in addition to “wherein for at least one of the fluidic transistors, the flow and gate channels are disposed in a single substrate or in different substrates,” (Para[0015] In some embodiments, an apparatus includes a substrate, a plurality of particles and a flow mechanism. The substrate may define a microfluidic channel configured to receive a sample containing a plurality of DNA molecules.) and wherein the single substrate or the different substrates comprise glass, plastic, a semiconductor, a metal, an elastomer, or a combination thereof. (Para [0059}, In certain embodiments, the substrate material may include at least one of silicon, silicon-based material, glass, modified or functionalized glass, plastic, metal, ceramic plastics or a combination thereof. The substrate is generally a non-magnetic material.). Regarding claim 17, Esfandyarpour teaches all of claim 23 as above in addition to “wherein for at least one of the fluidic transistors, the deformable region is configured to minimize fluidic communication between the flow and gate channels, or wherein the deformable region is configured to deflect upon applying pressure between the gate region and the source.” (Para [0154], Control lines 2002 may control the flow of fluids through the activation of valves 2008. Pressurizing the control lines 2002, deforms a wall between the control lines 2002 and the fluidic channels 2004, pinching off the fluidic channel and closing the valve 2008. FIG. 21 shows a further embodiment of the fluidics system, with similar control lines 2102, fluidic channels 2104 and valves 2108, but with additional crossovers 2110, wherein the control line is narrowed too much to be able to fully deform to the point wherein the fluidic channel 2102 is sealed, preventing the crossover 2110 from acting as a valve 2108). Regarding claim 20, Esfandyarpour teaches all of claim 23 as above. The recitation “wherein at least one of the fluidic transistors comprisesis capability of the fluidic transistor. Esfandyarpour discloses the positively claimed structural elements of the at least one of the fluidic transistors as claimed, such at least one of the fluidic transistors are said to be fully capable of the recited adaption in as much as recited and required herein. Regarding claim 24, Esfandyarpour teaches all of claim 23 as above. The recitation “wherein the fluidic transistor is configured in a common-source topology, common-gate topology, or a common- drain topology, or a combination thereof.” is capability of the fluidic transistor. Esfandyarpour discloses the positively claimed structural elements of the at least one of the fluidic transistors as claimed, such at least one of the fluidic transistors are said to be fully capable of the recited adaption in as much as recited and required herein. Regarding claim 28, Esfandyarpour teaches all of claim 23 as above and further teaches “wherein the fluidic network is configured as a fluidic amplifier, a fluidic flow-buffer, a fluidic regulator, a fluidic pressure-buffer, a fluidic level-shifter, or a fluidic logic gate.” (Para [0015], he mechanism for producing the flow may be configured to produce a flow of the sample and the plurality of particles within the microfluidic channel such that the plurality of particles produces a shear force on the plurality of DNA molecules to produce a plurality of DNA fragments. In some embodiments, an on-chip peristaltic pump, made of multiple fluidic gates with orthogonal control and flow channels (Valve Technology), or an external pressure may generate the required flow in the channel.). Therefore the network is a fluidic logic gate. Regarding claim 63, Esfandyarpour teaches all of claim 28 as above and further teaches “wherein the fluidic network further comprises one or more of a subcircuit, a fluidic load, a fluidic resistor, a fluidic capacitor, a fluidic inductor, a fluidic trap, or a fluidic filter.” (Para [0149], Said another way, in some embodiments, the valves in the channel can be partially closed creating a leaky “sieve valve” to separate the DNA fragments from the fragmentation beads 1924.). Therefore the sieve valve within the network discloses the fluidic filter. Regarding claim 64, Esfandyarpour teaches all of claim 28. The recitation “wherein the fluidic network is configured as a fluidic amplifier in a common-source topology, and wherein the fluidic amplifier comprises: at least one of the fluidic transistors, wherein a gate region of the fluidic transistor is configured as an input terminal for an input pressure signal with respect to a source region, and wherein a drain region is configured as an output terminal to provide an amplified output signal with respect to the source region, as compared to the input pressure signal.” is capability of the fluidic network and the gate region . Esfandyarpour discloses the positively claimed structural elements of the fluidic network and the gate region as claimed, such fluidic network and gate region are said to be fully capable of the recited adaption in as much as recited and required herein. Regarding claim 65, Esfandyarpour teaches all of claim 28. The recitation “wherein the fluidic network is configured as a fluidic flow-buffer in a common-gate topology, and wherein the fluidic flow-buffer comprises: at least one of the fluidic transistors, wherein a source region of the fluidic transistor is configured as an input terminal for an input flow signal, and wherein a drain region is configured as an output terminal to provide an output fluidic signal comprising a flow rate that is substantially equal to that of the input flow signal and comprising a greater pressure, as compared to an input flow signal in direct fluidic communication with the output fluidic signal.” is capability of the fluidic network, source region, and the drain region. Esfandyarpour discloses the positively claimed structural elements of the fluidic network, source region, and the drain region as claimed, such features are said to be fully capable of the recited adaption in as much as recited and required herein. Regarding claim 66, Esfandyarpour teaches all of claim 28. The recitation “wherein the fluidic network is configured as a fluidic regulator,” and “wherein the second terminal is configured as an input terminal, and the drain region of the at least one of the fluidic transistors is configured as an output terminal such that a relative change in the pressure of an input pressure signal produces a smaller relative change in the flow of an output flow signal.” is capability of the fluidic network, the second terminal, and the drain region. Esfandyarpour discloses the positively claimed structural elements of the fluidic network, the second terminal, and the drain region as claimed, such features are said to be fully capable of the recited adaption in as much as recited and required herein. Further taught by Esfandyarpour “and wherein: a first terminal of a fluidic load is in fluidic communication with the source region of at least one of the fluidic transistors, a second terminal of the fluidic load is in fluidic communication with a gate region of the at least one of the fluidic transistors,” (Para [0131], [0154], and Fig. 18a-b, and Fig 21, control lines 2002, The microfluidic device can control the “injection” or flow of the beads, reagents and/or samples described herein by a series of control lines that intersect with and/or impede upon the microfluidic channels described herein.) Therefore the control lines disclose the fluidic load with a first and second terminal which communicates with the source region and the gate region. Regarding claim 67, Esfandyarpour teaches all of claim 28. The recitation “wherein the fluidic network is configured as a fluidic pressure-buffer in a common-drain topology, and wherein the fluidic pressure-buffer comprises: at least one of the fluidic transistors, wherein a gate region of the fluidic transistor is configured as an input terminal for an input pressure signal; and wherein a source region is configured as an output terminal to provide an output fluidic signal comprising pressure that is substantially equal to that of the input pressure signal and comprising a greater flow rate, as compared to an input pressure signal in direct fluidic communication with the output fluidic signal.” is capability of the fluidic network, the fluidic pressure- buffer (which is not positively claimed), gate region, and the source region,. Esfandyarpour discloses the positively claimed structural elements of the fluidic network, the fluidic pressure- buffer (which is not positively claimed), gate region, and the source region as claimed, such features are said to be fully capable of the recited adaption in as much as recited and required herein. Regarding claim 68, Esfandyarpour teaches all of claim 33 in addition to “wherein the fluidic network comprises a fluidic level-shifter, “ (Para [0015], on-chip peristaltic pump, made of multiple fluidic gates with orthogonal control and flow channels (Valve Technology); and wherein: a first terminal of a fluidic load is in fluidic communication with the source region of at least one of the fluidic transistors,” (Para [0131], [0154], and Fig. 18a-b, and Fig 21, control lines 2002, The microfluidic device can control the “injection” or flow of the beads, reagents and/or samples described herein by a series of control lines that intersect with and/or impede upon the microfluidic channels described herein.) Therefore the control lines disclose the fluidic load with a first and second terminal which communicates with the source region and the gate region. The recitation “and a second terminal of the fluidic load is configured as an output terminal such that an output pressure signal is level-shifted, as compared to the input pressure signal.” is capability of the second terminal. Esfandyarpour discloses the positively claimed structural elements of the second terminal as claimed, such features are said to be fully capable of the recited adaption in as much as recited and required herein. Regarding claim 69, Esfandyarpour teaches all of claim 28. The recitation “wherein the fluidic network is configured as a fluidic logic gate, and wherein the fluidic logic gate comprises: a plurality of fluidic transistors, wherein gate regions of the plurality of the fluidic transistors are configured as input terminals for a plurality of input fluidic signals; and wherein drain regions of the plurality of fluidic transistors are in fluidic connection and are configured as an output terminal to provide an output fluidic signal that varies in pressure depending on pressure of the plurality of input fluidic signals.” is capability of the fluidic network, the fluidic logic gate (which is not positively claimed), gate regions, and the drain regions. Esfandyarpour discloses the positively claimed structural elements of the fluidic network, the fluidic logic gate (which is not positively claimed), gate regions, and the drain regions as claimed, such features are said to be fully capable of the recited adaption in as much as recited and required herein. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Esfandyarpour et. al. (US20190226021) as applied to claim 33 above and in further view of Ogg et. al. (CN 105873681 A). Regarding claim 19, Esfandyarpour teaches all of claim 33 in addition to teaching layers within Para [0131]. However, Esfandyarpour does not teach “wherein at least one of the fluidic transistors further comprises: a deformable layer disposed between the flow channel and the gate channel, wherein the deformable region is disposed within the deformable layer.”. Ogg teaches cartridge and instruments for sample analysis in addition to “wherein at least one of the fluidic transistors further comprises: a deformable layer disposed between the flow channel and the gate channel, wherein the deformable region is disposed within the deformable layer.”(Pages 1 and 2, The invention further claims a card first side of the deformable layer comprises a first layer, a second layer and a gate electric layer clamped between them: (a) wherein the first layer comprises: (i) contacting a deformable layer, wherein the first side comprises a plurality of fluid loop. each fluid loop comprises at least one fluid channel and at least one valve seat, and (ii) a second side comprises at least one pneumatic distribution channel, the pneumatic distribution channel optionally covered by a cover layer, (iii) at least one through-hole in the first layer. which is configured to make the pneumatic distribution channel communicates with the deformable layer). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Esfandyarpour to incorporate the teachings of Ogg having a deformable layer as claimed. Doing so would have the deformable material is in direct contact with the surface of the cartridge interface as taught by Ogg on pages 1 and 2 which would decrease the amount of time for samples to travel to the deformable layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VELVET E HERON whose telephone number is (571)272-1557. The examiner can normally be reached M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Charles Capozzi can be reached on (571) 270-3638. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /V.E.H./Examiner, Art Unit 1798 /CHARLES CAPOZZI/Supervisory Patent Examiner, Art Unit 1798
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Prosecution Timeline

Oct 23, 2023
Application Filed
Aug 27, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
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Grant Probability
99%
With Interview (+52.6%)
3y 9m (~10m remaining)
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