DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to preliminary amendments and remarks filed on 10/30/2023. In the current amendments, the specification is amended, the abstract is amended, claim 9 is amended, and claims 10-15 are newly presented. Claims 1-15 are pending and have been examined.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/30/2023, 05/27/2025, and 08/22/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 and 9-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the next layer” in line 10. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, “the next layer” has been interpreted as “a next layer”.
Claim 1 recites the limitation “the next in-memory computing cycle” in line 10. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, “the next in-memory computing cycle” has been interpreted as “a next in-memory computing cycle”.
Claim 2 recites the limitation “the in-memory computing cycle” in line 9. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, “the in-memory computing cycle” has been interpreted as “an in-memory computing cycle”.
Claim 2 recites the limitation “the size” in line 10. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, “the size” has been interpreted as “a size”.
Claim 3 recites the limitation “the symbol of weights” in line 7. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, “the symbol of weights” has been interpreted as “a symbol of weights”.
Dependent claims 2-7 and 9-15 are rejected based on being directly or indirectly dependent on rejected claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2024/0111987 A1) in view of Park et al. ("T2FSNN: Deep Spiking Neural Networks with Time-to-first-spike Coding").
Regarding Claim 1,
Yang et al. teaches a method for operating an in-memory computing architecture applied to a neural network (Fig. 1; [0009]: "In a first aspect, there is provided a current integration-based in-memory SNN including pre-neurons, a synaptic array and post-neuron circuits" teaches a current integration-based in-memory SNN (in-memory computing architecture applied to a neural network) including pre-neurons, a synaptic array and post-neuron circuits. [0084]: "Those skilled in the art could clearly understand that, for the convenience and conciseness of description, for details in specific working processes of the foregoing apparatuses and devices, reference may be made to the above detailed description of corresponding processes in the method embodiments, and a repeated description of such details is omitted to avoid redundancy" teaches that the above described embodiment can be implemented as a method), comprising:
inputting the mono-pulse input signal into a memory array of the in-memory computing architecture to generate a bit line current signal corresponding to the memory array (Fig. 1; Fig. 3a; [0009]-[0012]: "In a first aspect, there is provided a current integration-based in-memory SNN including pre-neurons, a synaptic array and post-neuron circuits, … the synaptic array configured to receive input spikes from the pre-neurons, the synaptic array consisting of i*j synaptic circuits, where i is the number of rows, j is number of columns, and i and j are both positive integers greater than or equal to 1, … each of the synaptic circuits including a memory cell, … the memory cell made up of a conventional six-transistor static random-access memory (6T SRAM) cell for storing a 1-bit synaptic weight and two series transistors for reading the synaptic weight, one of the transistors including a gate connected to an output of an inverter in the 6T SRAM cell, a source connected to a high level and a drain connected to a source of the other transistor, the other transistor including a gate connected to a read word line, a drain connected to a read bit line for carrying a conducting current as an output current of the synaptic circuit" teaches a current integration-based in-memory neural network (in-memory computing architecture) comprising a synapse array comprising memory cells (memory array) receiving an input spike (mono-pulse input signal) and generating an output current bit line signal (bit line current signal)); and
controlling a neuron circuit of the in-memory computing architecture to output a mono-pulse output signal based on discrete time coding according to the bit line current signal, wherein the mono-pulse output signal is configured as a mono-pulse input signal of a memory array of the next layer of neural network in the next in-memory computing cycle (Fig. 1; [0009]-[0013]: "In a first aspect, there is provided a current integration-based in-memory SNN including pre-neurons, a synaptic array and post-neuron circuits … a drain connected to a read bit line for carrying a conducting current as an output current of the synaptic circuit, … the post-neuron circuits including an integration capacitor and a comparator, each of the post-neuron circuits configured to fire a spike to a next-layer neuron depending on a comparison of an accumulated voltage across the integration capacitor with a threshold voltage; the accumulated voltage resulted from an integration by the integration capacitor of the output currents in one column of synaptic circuits to which the integration capacitor is connected" teaches a post-neuron circuit (neuron circuit) of the current integration-based in-memory neural network (in-memory computing architecture) that outputs a spike (mono-pulse output signal) to a next-layer neuron (e.g. the output spike is a mono-pulse input signal to the memory array of the next layer of the neural network in the next computing cycle) based on the output current bit line signal (bit line current signal)).
Yang et al. does not appear to explicitly teach generating a mono-pulse input signal based on discrete time coding.
However, Park et al. teaches generating a mono-pulse input signal based on discrete time coding (Fig. 2; Section II. B, first-third paragraphs: "Neural coding is a method of representing information with spike trains, including encoding and decoding procedures. There have been four neural coding schemes in deep SNNs: rate, phase, burst, and TTFS ... As illustrated in Fig. 2, the neurons with TTFS coding generate only one spike during inference and transmit the information using the timing of the spike" teaches generating a single spike input signal (mono-pulse input signal) using time to first spike (TTFS) based neural coding (discrete time coding)).
Yang et al. is analogous to the claimed invention because it is directed towards in-memory computing for neural networks.
Park et al. is analogous to the claimed invention because it is directed towards to use of temporal coding for implementing neural networks.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate generating a mono-pulse input signal based on discrete time coding as taught by Park et al. to the disclosed invention of Yang et al.
One of ordinary skill in the art would have been motivated to make this modification to "improve the inference efficiency of deep SNNs in terms of both latency and number of spikes" (Park et al. Conclusion).
Regarding Claim 8,
Yang et al. teaches an apparatus for operating an in-memory computing architecture applied to a neural network (Fig. 1; [0009]: "In a first aspect, there is provided a current integration-based in-memory SNN including pre-neurons, a synaptic array and post-neuron circuits" teaches a current integration-based in-memory SNN (in-memory computing architecture applied to a neural network) including pre-neurons, a synaptic array and post-neuron circuits. [0084]: "Those skilled in the art could clearly understand that, for the convenience and conciseness of description, for details in specific working processes of the foregoing apparatuses and devices, reference may be made to the above detailed description of corresponding processes in the method embodiments, and a repeated description of such details is omitted to avoid redundancy" teaches that the above described embodiment can be implemented as an apparatus), comprising:
a bit line signal generation module configured to input the mono-pulse input signal into a memory array of the in-memory computing architecture to generate a bit line current signal corresponding to the memory array (Fig. 1; Fig. 3a; [0009]-[0012]: "In a first aspect, there is provided a current integration-based in-memory SNN including pre-neurons, a synaptic array and post-neuron circuits, … the synaptic array configured to receive input spikes from the pre-neurons, the synaptic array consisting of i*j synaptic circuits, where i is the number of rows, j is number of columns, and i and j are both positive integers greater than or equal to 1, … each of the synaptic circuits including a memory cell, … the memory cell made up of a conventional six-transistor static random-access memory (6T SRAM) cell for storing a 1-bit synaptic weight and two series transistors for reading the synaptic weight, one of the transistors including a gate connected to an output of an inverter in the 6T SRAM cell, a source connected to a high level and a drain connected to a source of the other transistor, the other transistor including a gate connected to a read word line, a drain connected to a read bit line for carrying a conducting current as an output current of the synaptic circuit" teaches a current integration-based in-memory neural network (in-memory computing architecture) comprising a synapse array comprising memory cells (memory array) receiving an input spike (mono-pulse input signal) and generating an output current bit line signal (bit line current signal)); and
a control output module configured to control a neuron circuit of the in-memory computing architecture to output a mono-pulse output signal based on discrete time coding according to the bit line current signal, wherein the mono-pulse output signal is configured as a mono-pulse input signal of a memory array of a next layer of neural network in a next in-memory computing cycle (Fig. 1; [0009]-[0013]: "In a first aspect, there is provided a current integration-based in-memory SNN including pre-neurons, a synaptic array and post-neuron circuits … a drain connected to a read bit line for carrying a conducting current as an output current of the synaptic circuit, … the post-neuron circuits including an integration capacitor and a comparator, each of the post-neuron circuits configured to fire a spike to a next-layer neuron depending on a comparison of an accumulated voltage across the integration capacitor with a threshold voltage; the accumulated voltage resulted from an integration by the integration capacitor of the output currents in one column of synaptic circuits to which the integration capacitor is connected" teaches a post-neuron circuit (neuron circuit) of the current integration-based in-memory neural network (in-memory computing architecture) that outputs a spike (mono-pulse output signal) to a next-layer neuron (e.g. the output spike is a mono-pulse input signal to the memory array of the next layer of the neural network in the next computing cycle) based on the output current bit line signal (bit line current signal)).
Yang et al. does not appear to explicitly teach an input signal generation module configured to generate a mono-pulse input signal based on discrete time coding.
However, Park et al. teaches an input signal generation module configured to generate a mono-pulse input signal based on discrete time coding (Fig. 2; Section II. B, first-third paragraphs: "Neural coding is a method of representing information with spike trains, including encoding and decoding procedures. There have been four neural coding schemes in deep SNNs: rate, phase, burst, and TTFS ... As illustrated in Fig. 2, the neurons with TTFS coding generate only one spike during inference and transmit the information using the timing of the spike" teaches generating a single spike input signal (mono-pulse input signal) using time to first spike (TTFS) based neural coding (discrete time coding)).
Yang et al. is analogous to the claimed invention because it is directed towards in-memory computing for neural networks.
Park et al. is analogous to the claimed invention because it is directed towards to use of temporal coding for implementing neural networks.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate an input signal generation module configured to generate a mono-pulse input signal based on discrete time coding as taught by Park et al. to the disclosed invention of Yang et al.
One of ordinary skill in the art would have been motivated to make this modification to "improve the inference efficiency of deep SNNs in terms of both latency and number of spikes" (Park et al. Conclusion).
Claims 5, 9, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2024/0111987 A1) in view of Park et al. ("T2FSNN: Deep Spiking Neural Networks with Time-to-first-spike Coding") and further in view of Chun et al. (US 2023/0186986 A1).
Regarding Claim 5,
Yang et al. in view of Park et al. teaches the method of claim 1.
Yang et al. in view of Park et al. does not appear to explicitly teach wherein the controlling a neuron circuit of the in- memory computing architecture to output a mono-pulse output signal based on discrete time coding according to the bit line current signal comprises: controlling an on-off state of a first switching transistor and a second switching transistor of the neuron circuit in response to the bit line current signal, so that the neuron circuit outputs the mono-pulse output signal in response to the on-off state.
However, Chun et al. teaches wherein the controlling a neuron circuit of the in- memory computing architecture to output a mono-pulse output signal based on discrete time coding according to the bit line current signal comprises: controlling an on-off state of a first switching transistor and a second switching transistor of the neuron circuit in response to the bit line current signal, so that the neuron circuit outputs the mono-pulse output signal in response to the on-off state (Fig. 3; [0080]-[0082]: "The leakage sub-circuit 361 may receive the column integrated signal (e.g., ICells) and the reference integrated signal (e.g., IAps) described above with reference to FIG. 2 … The leakage sub-circuit 361 may be deactivated while a reset signal RESET is applied, and may be activated while the reset signal RESET is not applied. For example, the leakage sub-circuit 361 may allow an output current according to the output signal 159 to leak for a threshold time after the reset signal RESET is not applied … The output current of the output signal 159 may be converted to an output voltage while flowing in the capacitor. A leakage operational amplifier OPinteg of the leakage sub-circuit 361 may be connected to a window switch at an output terminal, and the window switch may be connected to a capacitor connected to the ground. When a window signal WINDOW is being applied to the window switch, the window switch may be closed and the leakage operational amplifier OPinteg and a capacitor connected to the ground may be connected. Thus, the output current of the output signal 159 may flow into the capacitor connected to the ground located at the output terminal of the leakage operational amplifier OPinteg. The capacitor connected to the ground may convert the output current to an output voltage by leaking charges corresponding to the output current … the leakage sub-circuit 361 may transmit the leaked output voltage to the firing sub-circuit 362 for the above-described threshold time" teaches a reset switch (first switch transistor) and a window switch (second switching transistor) that are opened and closed (on-off state) based on the output current signal (bit line current signal) for outputting the output voltage signal (mono-pulse output)).
Yang et al. and Chun et al. are analogous to the claimed invention because they are directed towards in-memory computing for neural networks.
Park et al. is analogous to the claimed invention because it is directed towards to use of temporal coding for implementing neural networks.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the controlling a neuron circuit of the in- memory computing architecture to output a mono-pulse output signal based on discrete time coding according to the bit line current signal comprises: controlling an on-off state of a first switching transistor and a second switching transistor of the neuron circuit in response to the bit line current signal, so that the neuron circuit outputs the mono-pulse output signal in response to the on-off state as taught by Chun et al. to the disclosed invention of Yang et al. in view of Park et al.
One of ordinary skill in the art would have been motivated to make this modification to "minimize an error due to a size of the capacitor or a limitation of the leakage current in the output circuit" (Chun et al. [0086]).
Regarding Claim 9,
Yang et al. in view of Park et al. teaches the method of claim 1.
Yang et al. in view of Park et al. does not appear to explicitly teach an electronic device, comprising: one or more processors; and a storage apparatus for storing one or more programs, wherein one or more programs, when executed by one or more processors, cause one or more processors to implement the method.
However, Chun et al. teaches an electronic device, comprising: one or more processors; and a storage apparatus for storing one or more programs, wherein one or more programs, when executed by one or more processors, cause one or more processors to implement the method (Fig. 1; [0120]: "The neural network circuits, synaptic memory arrays … and other apparatuses, units, modules, devices, and components described herein with respect to FIGS. 1-10 are implemented by or representative of hardware components … one or more of the hardware components that perform the operations described in this application are implemented by computing hardware, for example, by one or more processors or computers. A processor or computer may be implemented by one or more processing elements, such as an array of logic gates, a controller and an arithmetic logic unit, a digital signal processor, a microcomputer, a programmable logic controller, a field-programmable gate array, a programmable logic array, a microprocessor, or any other device or combination of devices that is configured to respond to and execute instructions in a defined manner to achieve a desired result. In one example, a processor or computer includes, or is connected to, one or more memories storing instructions or software that are executed by the processor or computer" teaches that the neural network circuits for implementing the described embodiments may be implemented as hardware components of computing hardware (electronic device) comprising a processor for executing instructions (programs) stored in memory (storage device)).
Yang et al. and Chun et al. are analogous to the claimed invention because they are directed towards in-memory computing for neural networks.
Park et al. is analogous to the claimed invention because it is directed towards to use of temporal coding for implementing neural networks.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate an electronic device, comprising: one or more processors; and a storage apparatus for storing one or more programs, wherein one or more programs, when executed by one or more processors, cause one or more processors to implement the method as taught by Chun et al. to the disclosed invention of Yang et al. in view of Park et al.
One of ordinary skill in the art would have been motivated to make this modification because "limitations in a design for sensing and summing current output from the memory array may be reduced" (et al. [0067]).
Regarding Claim 13,
Yang et al. in view of Park et al. and further in view of Chun et al. teaches the method of claim 5.
In addition, Chun et al. further teaches an electronic device, comprising: one or more processors; and a storage apparatus for storing one or more programs, wherein one or more programs, when executed by one or more processors, cause one or more processors to implement the method (Fig. 1; [0120]: "The neural network circuits, synaptic memory arrays … and other apparatuses, units, modules, devices, and components described herein with respect to FIGS. 1-10 are implemented by or representative of hardware components … one or more of the hardware components that perform the operations described in this application are implemented by computing hardware, for example, by one or more processors or computers. A processor or computer may be implemented by one or more processing elements, such as an array of logic gates, a controller and an arithmetic logic unit, a digital signal processor, a microcomputer, a programmable logic controller, a field-programmable gate array, a programmable logic array, a microprocessor, or any other device or combination of devices that is configured to respond to and execute instructions in a defined manner to achieve a desired result. In one example, a processor or computer includes, or is connected to, one or more memories storing instructions or software that are executed by the processor or computer" teaches that the neural network circuits for implementing the described embodiments may be implemented as hardware components of computing hardware (electronic device) comprising a processor for executing instructions (programs) stored in memory (storage device)).
Yang et al. and Chun et al. are analogous to the claimed invention because they are directed towards in-memory computing for neural networks.
Park et al. is analogous to the claimed invention because it is directed towards to use of temporal coding for implementing neural networks.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate an electronic device, comprising: one or more processors; and a storage apparatus for storing one or more programs, wherein one or more programs, when executed by one or more processors, cause one or more processors to implement the method as taught by Chun et al. to the disclosed invention of Yang et al. in view of Park et al.
One of ordinary skill in the art would have been motivated to make this modification because "limitations in a design for sensing and summing current output from the memory array may be reduced" (et al. [0067]).
Allowable Subject Matter
Claims 2-4, 6-7, 10-12, and 14-15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN J HALES whose telephone number is (571)272-0878. The examiner can normally be reached M-F 9:00am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kamran Afshar can be reached at (571) 272-7796. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRIAN J HALES/Examiner, Art Unit 2125
/KAMRAN AFSHAR/Supervisory Patent Examiner, Art Unit 2125
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