DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The replacement drawings were received on 8/5/26. These drawings are acceptable.
Response to Arguments
Applicant's arguments filed 8/5/26 have been fully considered but they are not persuasive.
Applicant argues the Xiong mapping of the sub-holes is inconsistent. In response, Examiner has corrected the inadvertent error in mapping of the sub-holes in the rejection below.
Applicant argues that Xiong is non-analogous art. In response, a reference dealing with fabrication of communicating, different diameter vias can be reasonably pertinent to the problem of constructing a stepped via structure. Tehrani discloses that vias 25 are opened through the insulating gate structure and that polysilicon is deposited in vias 25 to form conduction channel 35 and a top semiconductor contact 36. Xiong teaches stepped dual-diameter via hole geometry. Thus, Tehrani supports deposition of semiconductor material in a via, while Xiong supports a via having two coaxial, communicating portion of unequal diameter. Because Tehrani deposits its semiconductor material into the via, the modified Tehrani structure below would have portions of that semiconductor material occupying the respective smaller and larger portions.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3-5 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 3 and 5 recite the limitation “an interface” in line 6. The term "interface" is not clearly defined in the specification (e.g., is it the edge, center, or midpoint). The question remains interface with what. A three-dimensional component normally has multiple surface/interfaces. Likewise, claim 5 measures a distance between “the interface of the extension part” and “the interface of the main body part” without expressly identifying the particular interfaces. Accordingly, the 0.5–5 µm measurement cannot be accurately determined, making the claim indefinite.
The other claims are rejected as being dependent on an indefinite base claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being obvious over U.S. Patent No. 5,943,574 (Tehrani, patent family member of JP 2001-044279, cited by Applicant) in view of U.S. Patent Application Publication No. 2019/0208631 (Xiong).
Tehrani discloses
1. (Currently Amended) A semiconductor device, comprising:
a substrate 10;
a first active layer 17, disposed on the substrate 10;
a first insulation layer 20, covering the first active layer 17; and
a second active layer 36, disposed on the first insulation layer 20, wherein the first insulation layer 20 is provided with a first via hole 25, and the third active layer 35 is disposed in the first via hole 25 and connects the first active layer 17 and the second active layer 36.
Tehran fails to disclose
the first via hole comprises a first sub-hole and a second sub-hole communicated with each other in a thickness direction
Xiong teaches (at least Figs. 1A, 1B)
A semiconductor device comprising:
wherein the first via hole 136 comprises a first sub-hole 136b and a second sub-hole 136a communicated with each other in a thickness direction, a size of the second sub-hole 136a is greater than a size of the first sub-hole 136b ([0033], the via 136 includes a wide cylindrical opening 136a and a narrow cylindrical opening 136b, where the two cylindrical openings 136a and 136b are electrically connected).
Xiong teaches the general concept of a via hole formed in two stages—such as a "dual-drill" process—where a wide top portion and a narrower bottom portion (second sub-hole) are aligned to form a single continuous hole. Given the "broadest reasonable interpretation" (BRI) of a sub-hole, a single, complex-shaped via hole is interpreted to encompass a hole created by two smaller sub-holes.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the geometry of a via to form sub-holes in Tehrani. The motivation would be sub-holes may provide improved signal integrity and reduce crosstalk as taught by Xiong ([0033]-[0040]).
Claim(s) 2 is/are, to the extent taught and understood, rejected under 35 U.S.C. 103 as being unpatentable over Tehrani in view of Xiong, as applied to claim 1 above, and further in view of U.S. Patent No. 5,772,904 (Kim).
Tehrani discloses
2. (Original) The semiconductor device according to claim 1, further comprising:
a first conductive layer 30, disposed in the first insulation layer 20 and comprising a gate (col. 4, lines 3-31) provided with a first opening 26,
The combination of references fails to teach
wherein in a top view, the first via hole is disposed in the first opening.
Kim teaches
A semiconductor device comprising:
a first insulation layer 13 is provided with a first via hole 13”;
a first conductive layer 14, disposed in the first insulation layer 13 and comprising a gate (column 3, lines 26-44) provided with a first opening 14”, wherein in a top view (not shown, but the hole and the opening are aligned), the first via hole 13” is disposed in the first opening 14”.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide the hole in an opening in the modified device of Tehrani. The motivation would be driven by the need for high-density, low-parasitic, and high-performance interconnects. Such a structure typically enables precise, self-aligned contacts to the source/drain regions while maintaining electrical isolation from the surrounding gate as taught by Kim (column 4, lines 42-46).
Claim(s) 3-5, 7, 8, 13 is/are, to the extent taught and understood, rejected under 35 U.S.C. 103 as being unpatentable over Tehrani in view of Xiong and Kim, as applied to claims 1, 2 above, and further in view of U.S. Patent Application Publication No. 2024/0258340 (Luo).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
Tehrani discloses
3. (Currently Amended) The semiconductor device according to claim 2, wherein the third active layer comprises:
the main body part (portion of 35/36), disposed in the first via hole 136b; and
the extension part (portion of 35/36), connected to the main body part and disposed between the second active layer 36 and the first insulation layer 20,
The combination of references fails to teach
wherein in the top view, an orthographic projection of an interface of the main body part on the extension part is located within an interface of the extension part.
Luo teaches
A semiconductor device comprising:
wherein the third active layer 7 comprises:
a main body part (middle portion), disposed in the first via hole 8; and
an extension part (top left and right portions), connected to the main body part (middle portion) and disposed between the second active layer 6 and the first insulation layer 4 / 28, wherein in the top view (not shown), an orthographic projection of a boundary of the main body part (middle portion) on the extension part (top left and right portions) is located within a boundary of the extension part (top left and right portions).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide the third active layer with a main body part and an extension part in the modified device of Tehrani. The motivation would be to ensure that the area of the TFT projected in the direction of the array substrate is reduced based on higher mobility as taught by Luo ([0026]).
Luo teaches
4. (Original) The semiconductor device according to claim 3, wherein in the top view, the extension part (top left and right portions) partially overlaps the gate 5.
It would have been obvious to select the distance range by routine optimization. See MPEP 2144.05.
5.(Currently Amended) The semiconductor device according to claim 4, wherein a distance between the interface of the extension part and the interface of the main body part is greater than or equal to 0.5 microns and is less than or equal to 5 microns.
The combination of references fails to teach
7. (Original) The semiconductor device according to claim 2, wherein the first insulation layer comprises:
a first insulation sub-layer, covering the first active layer; and
a second insulation sub-layer, covering the first conductive layer, wherein the second active layer is disposed on the second insulation sub-layer.
Luo teaches
A semiconductor device comprising:
wherein the first insulation layer 4 / 28 comprises:
a first insulation sub-layer 11, covering the first active layer 3; and
a second insulation sub-layer 12, covering the first conductive layer 5, wherein the second active layer 6 is disposed on the second insulation sub-layer 12.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide first and second insulating sub-layers in the modified device of Tehrani. The motivation would be to form a multi-layer insulator which is well-known in the art as shown in Lou. See MPEP 2144.03.
It would have been obvious to select the thickness range by routine optimization. See MPEP 2144.05.
8. (Original) The semiconductor device according to claim 7, wherein a film thickness of the first conductive layer 5 ranges between 0.05 microns and 1 micron (Lou, [0048]), a thickness of the first insulation sub-layer ranges between 0.05 microns and 0.5 microns, and a thickness of the second insulation sub-layer ranges between 0.05 microns and 0.5 microns.
The combination of references fails to teach
13. (Original) The semiconductor device according to claim 1, wherein the first via hole has a shape of a circular truncated cone.
Luo teaches (Fig. 5)
A semiconductor device comprising:
wherein the first via hole 8 has a shape of a circular truncated cone.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a hole having a certain shape in Tehrani. The motivation would be a determination of the optimum based on routine engineering design considerations ([0045]). See MPEP 2144.04.
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Claim 9, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tehran in view of Xiong as applied to claim 1 above, and further in view of U.S. Patent No. 6,107,660 (Yang).
The combination of references fails to teach
9. (Original) The semiconductor device according to claim 1, further comprising:
a second conductive layer, disposed between the substrate and the first active layer and comprising a first electrode; and
a second insulation layer, covering the second conductive layer and provided with a second via hole, wherein the first active layer is electrically connected to the first electrode through the second via hole.
Yang teaches
A semiconductor device comprising:
a second conductive layer 24, disposed between the substrate 20 and the first active layer 36 and comprising a first electrode (doped polysilicon); and
a second insulation layer 26, covering the second conductive layer 24 and provided with a second via hole 32, wherein the first active layer 36 is electrically connected to the first electrode 24 through the second via hole 32.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a second conductive layer and a second insulating layer in the modified device of Tehrani. The motivation would be to provide a contact to the first active layer which can act as a doped region (source or drain), which are all well-known elements of a vertical semiconductor device that reduces occupied area and increases packing density as taught by Yang (Background).
Yang teaches
10. (Original) The semiconductor device according to claim 9, further comprising:
a third insulation layer 42, covering the second active layer 40 and provided with a third via hole 44c; and
a third conductive layer (not shown), disposed on the third insulation layer 42, and comprising:
a second electrode (not shown); and
an electrode connecting part (not shown), spaced apart from the second electrode (not shown), wherein the second electrode (not shown) is electrically connected to the second active layer 40 through the third via hole 44c, and the electrode connecting part (not shown) is electrically connected to the first electrode 24 through a fourth via hole 44a that penetrates through the third insulation layer 42, the first insulation layer 30, and the second insulation layer 26.
Claim 11, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tehran in view of Xiong and Yang as applied to claim 10 above, and further in view of U.S. Patent Application Publication No. 2021/0367081 (Yan).
The combination of references fails to teach
11.(Original) The semiconductor device according to claim 10, wherein the first electrode comprises:
a first electrode part;
a second electrode part; and
a third electrode part, connected between the first electrode part and the second electrode part, wherein in a top view, the first electrode part partially overlaps the first active layer, and the second electrode part partially overlaps the electrode connecting part.
Yan teaches
A semiconductor device comprising:
wherein the first electrode 400 / 410 / 160 comprises:
a first electrode part 400;
a second electrode part 160; and
a third electrode part 410, connected between the first electrode part 400 and the second electrode part 160, wherein in a top view (Fig. 5), the first electrode part 400 partially overlaps the first active layer 100, and the second electrode part 410 partially overlaps the electrode connecting part 400.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide the first electrode having three parts in the modified device of Tehrani. The motivation would be to reduce leakage current as taught by Yan ([0033]-[0037]).
Yan teaches
12. (Original) The semiconductor device according to claim 11, wherein a width of the third electrode part 410 is less than a width of the second electrode part 160, and the width of the second electrode part 160 is less than a width of the first electrode part 400.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication Nos. 2014/0003148 (Sun), 2013/0109175 (Zhang), 2003/0189396 (Niyama) teach vertically stacked active layers connected through an active layer formed inside a via hole in an insulating layer.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893
