DETAILED ACTION
Response to Arguments
Applicant’s arguments filed 04/08/2026, with respect to claims 1 and 15 have been fully considered and are not persuasive. Applicant argues that Atsuo et al. (JP 2017046008 A; hereinafter “Atsuo”), and further in view of Yamazaki et al. (US 2011/0068336 A1, hereinafter “Yamazaki”) fails to teach the following:
“and wherein a film forming gas of the semiconductor modification layer comprises silicon tetrahydride, such that a large amount of hydrogen doped in the semiconductor layer is from hydrogen in the silicon tetrahydride introduced in forming the semiconductor modification layer; a first temperature in a reaction chamber where the thin-film transistor is manufactured in forming the semiconductor modification layer ranges from 130°C to 200°C; and a thickness of the semiconductor modification layer ranges from 20 nm to 200 nm”.
In regard to the limitations of claim 1 that state “wherein a film forming gas of the semiconductor modification layer comprises silicon tetrahydride, such that a large amount of hydrogen doped in the semiconductor layer is from hydrogen in the silicon tetrahydride introduced in forming the semiconductor modification layer; a first temperature in a reaction chamber where the thin-film transistor is manufactured in forming the semiconductor modification layer ranges from 130°C to 200°C “ the presence of process limitations on product claims, in which the product is not otherwise patentably distinguish over prior art, cannot impart patentability to the product. In re Stephens 145 USPQ 656 (CCPA 1965). The method of forming a device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given patentable weight.
Further the limitation states a thickness of the semiconductor modification layer ranges from 20 nm to 200 nm is taught by Atsuo in paragraph 101. The insulating layer 405 can have a film thickness range of 100 to 400 nm. As the claimed range and range from Atsuo overlap the layer of the insulating layer 405 with a thickness of 100 to 200 would have proper quality.
Applicant’s arguments filed 04/08/2026, with respect to claim 2 has been fully considered the previous 112(b) rejection has been withdrawn. However, a new 112(b) rejection has been made.
Applicant’s arguments regarding claim 9 have been considered and the previous 35 U.S.C 102(a)(1) restriction has been withdrawn.
Examiner acknowledges the title of the invention has been changed and is clearly indicative of the invention to which the claims are directed. Therefore the specification objection has been withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regard to claims 2 and 18, it is unclear what the applicant regards as the semiconductor modification layer. This is due to the claim reciting “a distance between a portion most proximal to the base substrate and a portion most distal from the base substrate in a direction perpendicular to a bearing face of the base substrate is greater than or equal to 0 nm and less than or equal to 15 nm”. A distance between a portion most proximal to the base substrate and a portion most distal from the base substrate in a direction perpendicular to a bearing face of the base substrate is greater than or equal to 0 nm would mean there is an embodiment of the device where the semiconductor modification layer is completely flat.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8, 15-17 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Atsuo et al. (JP 2017046008 A; hereinafter “Atsuo”), and further in view of Yamazaki et al. (US 2011/0068336 A1, hereinafter “Yamazaki”).
In regard to claim 1, Atsuo teaches a thin-film transistor (a circuit constituted by a thin film transistor (hereinafter referred to as TFT) (Fig. 4A and paragraph 1), comprising:
a gate (a gate electrode 402), a first insulative layer(gate insulating films 403a) (Fig. 4A and paragraph 96), a semiconductor layer (amorphous semiconductor film 404 in between impurity regions 407) (Fig. 4A and paragraph 98 and 103), a source and drain layer (impurity region 406 is a high-concentration impurity region and becomes a later source / drain region) (Fig. 4C and paragraph 102), a semiconductor modification layer (an insulating layer 405) (Fig. 4B and paragraph 101), and a second insulative layer (an interlayer insulating film 408) that are disposed on a base substrate (a plastic substrate 400) and sequentially laminated in a direction away from the base substrate (the aforementioned layers are shown laminated sequentially in a direction away from the plastic substrate 400 in Fig. 4F) (Fig. 4F and paragraph 95);
wherein the source and drain layer comprises a source and a drain (the processed impurity regions 407 functions as the source and drain layer) that are spaced apart and both connected to the semiconductor layer (the processed impurity regions 407 are shown spaced apart and connected to the amorphous semiconductor film 404 in Fig. 4F) (Fig. 4F and paragraphs 102-103), a portion of the semiconductor layer is exposed from a gap between the source and the drain (the amorphous semiconductor film 404 is shown exposed and in between the processed impurity regions 407 in Fig. 4F), and the semiconductor modification layer at least covers the portion of the semiconductor layer exposed from the gap (the insulating layer 405 is shown covering the exposed amorphous semiconductor film 404 in Fig. 4F)
However, Atsuo doesn’t explicitly teach a number of hydrogen atoms in per cubic centimeter of the semiconductor layer is greater than 16 x 10^20 and less than 26 x 10^20; and wherein a film forming gas of the semiconductor modification layer comprises silicon tetrahydride, such that a large amount of hydrogen doped in the semiconductor layer is from hydrogen in the silicon tetrahydride introduced in forming the semiconductor modification layer; a first temperature in a reaction chamber where the thin-film transistor is manufactured in forming the semiconductor modification layer ranges from 130°C to 200°C; and a thickness of the semiconductor modification layer ranges from 20 nm to 200 nm.
However, the claim language stating “wherein a film forming gas of the semiconductor modification layer comprises silicon tetrahydride, such that a large amount of hydrogen doped in the semiconductor layer is from hydrogen in the silicon tetrahydride introduced in forming the semiconductor modification layer; a first temperature in a reaction chamber where the thin-film transistor is manufactured in forming the semiconductor modification layer ranges from 130°C to 200°C “ regards the process of forming the semiconductor modification layer. The presence of process limitations on product claims, in which the product is not otherwise patentably distinguish over prior art, cannot impart patentability to the product. In re Stephens 145 USPQ 656 (CCPA 1965). The method of forming a device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given patentable weight.
Further, Atsuo in paragraph 101, teaches the insulating layer 405 can have a film thickness range of 100 to 400 nm. As the claimed range and range from Atsuo overlap, the Examiner takes official notice that it would have been obvious to one skilled in the art at the time, to have a thickness of the insulating layer 405 be 100nm to 200nm, while ensuring layer quality.
Yamazaki teaches a thin film transistor (151), wherein a number of hydrogen atoms in per cubic centimeter of a semiconductor layer (oxide semiconductor layer 113) is greater than 16 x 10^20 and less than 26 x 10^20 (when hydrogen moves to the interface between the oxide semiconductor layer 113 and the oxide insulating layer 107 the hydrogen concentration at the interface is .5 X 1020 atoms/cm3 to 100 X 1020 atoms/cm3 therefore there exist a state where the concertation of the hydrogen atoms per cubic centimeter of a semiconductor layer is greater than 16 x 1020 and less than 26 x 1020) (paragraph 88).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to combine the teachings of Atsuo with the teachings of Yamazaki, since having a preferred concentration of hydrogen within the semiconductor layer increases the reliability of the device as taught by Yamazaki (paragraphs 9 and 88). Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In regard to claim 8, Atsuo teaches a material of the semiconductor modification layer comprises a silicon oxide (the insulating layer 405 is a silicon oxide film) (paragraph 101); and a material of the second insulative layer comprises a silicon oxide (the interlayer insulating film 408 is a silicon oxide) (paragraph 104), or a silicon oxide and a silicon nitride.
However, Atsuo doesn’t explicitly teach wherein a material of the semiconductor layer comprises an oxide.
Yamazaki teaches wherein a material of the semiconductor layer comprises an oxide (the semiconductor layer is an oxide semiconductor layer 123) (paragraph 42).
It would have been obvious to one of ordinary skill in the art to combine the teachings of Atsuo with the teachings of Yamazaki to have a material of the semiconductor layer comprises an oxide since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
In regard to claim 15, Atsuo teaches a display panel (liquid crystal display panel) (paragraph 1), comprising: a base substrate (a plastic substrate 400) and a plurality of thin-film transistors on the base substrate (a plurality of pixels, and TFT elements are provided in each of the plurality of pixels) (paragraph 119); wherein each of the plurality of thin-film transistors comprises:
a gate (a gate electrode 402), a first insulative layer(gate insulating films 403a) (Fig. 4A and paragraph 96), a semiconductor layer (amorphous semiconductor film 404 in between impurity regions 407) (Fig. 4A and paragraph 98 and 103), a source and drain layer (impurity region 406 is a high-concentration impurity region and becomes a later source / drain region) (Fig. 4C and paragraph 102), a semiconductor modification layer (an insulating layer 405) (Fig. 4B and paragraph 101), and a second insulative layer (an interlayer insulating film 408) that are disposed on the base substrate and sequentially laminated in a direction away from the base substrate (the aforementioned layers are shown laminated sequentially in a direction away from the plastic substrate 400 in Fig. 4F) (Fig. 4F and paragraph 95); wherein the source and drain layer comprises a source and a drain (the processed impurity regions 407 functions as the source and drain layer) that are spaced apart and both connected to the semiconductor layer (the processed impurity regions 407 are shown spaced apart and connected to the amorphous semiconductor film 404 in Fig. 4F) (Fig. 4F and paragraphs 102-103), a portion of the semiconductor layer is exposed from a gap between the source and the drain (the amorphous semiconductor film 404 is shown exposed and in between the processed impurity regions 407 in Fig. 4F), and the semiconductor modification layer at least covers the portion of the semiconductor layer exposed from the gap (the insulating layer 405 is shown covering the exposed amorphous semiconductor film 404 in Fig. 4F).
Atsuo doesn’t explicitly teach a number of hydrogen atoms in per cubic centimeter of the semiconductor layer is greater than 16 x 10^20 and less than 26 x 10^20; and wherein a film forming gas of the semiconductor modification layer comprises silicon tetrahydride, such that a large amount of hydrogen doped in the semiconductor layer is from hydrogen in the silicon tetrahydride introduced in forming the semiconductor modification layer; a first temperature in a reaction chamber where the thin-film transistor is manufactured in forming the semiconductor modification layer ranges from 130°C to 200°C; and a thickness of the semiconductor modification layer ranges from 20 nm to 200 nm.
However, the claim language stating “wherein a film forming gas of the semiconductor modification layer comprises silicon tetrahydride, such that a large amount of hydrogen doped in the semiconductor layer is from hydrogen in the silicon tetrahydride introduced in forming the semiconductor modification layer; a first temperature in a reaction chamber where the thin-film transistor is manufactured in forming the semiconductor modification layer ranges from 130°C to 200°C “ regards the process of forming the semiconductor modification layer. The presence of process limitations on product claims, in which the product is not otherwise patentably distinguish over prior art, cannot impart patentability to the product. In re Stephens 145 USPQ 656 (CCPA 1965). The method of forming a device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given patentable weight.
Further, Atsuo in paragraph 101, teaches the insulating layer 405 can have a film thickness range of 100 to 400 nm. As the claimed range and range from Atsuo overlap, the Examiner takes official notice that it would have been obvious to one skilled in the art at the time, to have a thickness of the insulating layer 405 be 100 nm to 200 nm, while ensuring layer quality.
Yamazaki teaches a display panel (a thin film transistor 151 which is typically used in a liquid crystal display device) (Fig. 1 and paragraph 42), wherein a number of hydrogen atoms in per cubic centimeter of a semiconductor layer (oxide semiconductor layer 113) is greater than 16 x 1020 and less than 26 x 1020 (When hydrogen moves to the interface between the oxide semiconductor layer 113 and the oxide insulating layer 107 the hydrogen concentration at the interface is .5 X 1020 atoms/cm3 to 100 X 1020 atoms/cm3 therefore there exist a state where the concertation of the hydrogen atoms per cubic centimeter of a semiconductor layer is greater than 16 x 1020 and less than 26 x 1020) (paragraph 88).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to combine the teachings of Atsuo with the teachings of Yamazaki, since having a preferred concentration of hydrogen within the semiconductor layer increases the reliability of the device as taught by Yamazaki (paragraphs 9 and 88). Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In regard to claim 16, Atsuo teaches wherein the base substrate comprises a display region (a pixel portion 87) and a periphery region (gate side driving circuit 84) surrounding the display region (the gate side driving circuit 84 is shown surrounding the pixel portion 88 in Fig. 5) (Fig. 5 and paragraph 111), the plurality of thin-film transistors are at least disposed in the display region (a plurality of pixels, and TFT elements are provided in each of the plurality of pixels) (paragraph 119), and the display panel further comprises: a signal wiring in the periphery region (it would be known to one skilled in the art that wiring would be present in a gate side driving circuit).
However, Atsuo doesn’t explicitly teach wherein the signal wiring comprises a first wiring segment and a second wiring segment that are disposed in different layers, the display panel further comprises a target insulative layer between the first wiring segment and the second wiring segment, and the first wiring segment is electrically connected to the second wiring segment by a via in the target insulative layer.
Yamazaki teaches wherein a signal wiring comprises a first wiring segment (a gate wiring layer 111b) and a second wiring segment (a second wiring layer 115c) that are disposed in different layers (the gate wiring layer 111b and a second wiring layer 115c are shown in different layers in Fig. 1) (Fig. 1 and paragraph 43), the display panel further comprises a target insulative layer (a second gate insulating layer 102b) between the first wiring segment and the second wiring segment (Fig. 1 and paragraph 42), and the first wiring segment is electrically connected to the second wiring segment by a via (a contact hole 128) in the target insulative layer (a contact hole 128 is formed in the gate insulating layer 102 to reach the gate wiring layer 111b) (paragraph. 43).
It would have been obvious to one skilled in the art to combine the teachings of Atsuo with the teachings of Yamazaki to have the signal wiring comprises a first wiring segment and a second wiring segment that are disposed in different layers, the display panel further comprises a target insulative layer between the first wiring segment and the second wiring segment, and the first wiring segment is electrically connected to the second wiring segment by a via in the target insulative layer since this is a well-known layout that allows for proper separation of components while maintain proper resistances to accommodate device operation.
In regard to claim 17, Atsuo in view of Yamazaki teaches wherein the first wiring segment and the gate are made of the same material by one patterning process (the gate electrode 111a and the gate wiring layer 111b is formed through a first photolithography step) (Yamazaki Fig. 2A and paragraphs 47-48), the second wiring segment and the source and drain layer are made of the same material by one patterning process (a conductive film is selectively etched, so that the second wiring layer (denoted by 115a, 115b and 115c) including the source electrode layer and the drain electrode layer is formed) (Yamazaki paragraph 79), and the target insulative layer is a first insulative layer (the gate insulating layer 102 serves as the target insulative layer and a first insulative layer as shown in Yamazaki Fig. 1).
In regard to claim 21, Atsuo teaches a material of the semiconductor modification layer comprises a silicon oxide (the insulating layer 405 is a silicon oxide film) (paragraph 101); and a material of the second insulative layer comprises a silicon oxide (the interlayer insulating film 408 is a silicon oxide) (paragraph 104), or a silicon oxide and a silicon nitride.
However, Atsuo doesn’t explicitly teach wherein a material of the semiconductor layer comprises an oxide.
Yamazaki teaches wherein a material of the semiconductor layer comprises an oxide (the semiconductor layer is an oxide semiconductor layer 123) (paragraph 42).
It would be obvious to one skilled in the art to combine the teachings of Atsuo with the teachings of Yamazaki to have a material of the semiconductor layer comprises an oxide since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claims 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Atsuo in view of Yamazaki as applied to claim 1, and further in view of Zhou et al. (US 2021/0210529 A1; hereinafter “Zhou”).
In regard to claim 6, Atsuo in view of Yamazaki doesn’t explicitly teach the thickness of the second insulative layer ranges from 100 nm to 350 nm.
Zhou teaches a thin film transistor (a thin film transistor as shown in Fig. 1) (Fig. 1 and paragraph 25), wherein a thickness of a second insulative layer (passivation layer 7) ranges from 100 nm to 350 nm (the passivation layer has a thickness of 150nm or smaller) (Fig. 1 and paragraph 68).
It would have been obvious to one skilled in the art to combine the teachings of Atsuo in view of Yamazaki with the teachings of Zhou to have the thickness of the second insulative layer ranges from 100 nm to 350 nm since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In regard to claim 20, Atsuo in view of Yamazaki doesn’t explicitly teach the thickness of the second insulative layer ranges from 100 nm to 350 nm.
Zhou teaches a thin film transistor (a display device, which comprises a thin film transistor as shown in Fig. 1) (Fig. 1 and paragraph 25 and 52), wherein a thickness of a second insulative layer (passivation layer 7) ranges from 100 nm to 350 nm (the passivation layer has a thickness of 150nm or smaller) (Fig. 1 and paragraph 68).
It would have been obvious to one skilled in the art to combine the teachings of Atsuo in view of Yamazaki with the teachings of Zhou to have the thickness of the second insulative layer ranges from 100 nm to 350 nm since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Allowable Subject Matter
Claims 9-12 and 14 are allowed.
The following is the Office's statement of reasons for allowance:
Regarding claim 9, the prior art of record, taken alone or in combination, fails to teach or suggest:
“the first temperature in the reaction chamber in forming the semiconductor modification layer ranges from 130°C to 200°C… a number of hydrogen atoms in per cubic centimeter of the semiconductor layer is greater than 16 x 1020 and less than 26 x 1020”
Zhang et al. (US 2020/0220020 A1, hereinafter “Zhang”) is considered a close prior art of reference (see for example non-final rejection mailed 01/23/2026). However, Zhang fails to teach forming the semiconductor modification layer ranges from 130°C to 200°C. Zhang teaches higher temperatures used to form an element mapped as the semiconductor modification layer.
Yamazaki et al. (US 20180053857 A1; hereinafter “Yamazaki857”) is considered a close prior art of reference. However, Yamazaki fails to teach a number of hydrogen atoms in per cubic centimeter of the semiconductor layer is greater than 16 x 1020 and less than 26 x 1020. Yamazaki teaches the hydrogen concentration of the element mapped as the semiconductor layer is less than 5×1019/cm3 (paragraph 149).
Claims 10-12 are allowable due to depending on claim 9.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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