DETAILED ACTION
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 6, 14, 18 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regard to claims 2 and 18, it is unclear what the applicant regards as the semiconductor modification layer. This is due to the claim reciting “a distance between a portion most proximal to the base substrate and a portion most distal from the base substrate in a direction perpendicular to a bearing face of the base substrate is greater than or equal to 0 nm and less than or equal to 15 nm”. This would mean the thickness of the semiconductor modification layer would be 0 nm ≤ X ≤ 15 nm. This directly contradicts claim 1 because if the thickness is 0nm the semiconductor modification layer would not be present, and further contradicts the specification where it is stated that the thickness of the semiconductor modification layer ranges from 20 nm to 200 nm (see paragraph 10 for example).
In regard to claim 6, it is unclear what the applicant regards as the thickness of the semiconductor modification layer and the thickness of the second insulative layer. This is because the ratio of the ranges of the thickness recited in the claim range from 2/35 to 2 not range from 1/25 to 1/3 as stated in claim 5 which claim 6 is a dependent claim of.
In regard to claim 14, it is unclear how the working ranges of the second temperature ranges of 220°C to 340°C can be greater than the threshold 250°C. This contradicts the limitation of independent claim 9 which recites in lines 17-19 the second temperature is less than the temperature threshold.
In regard to claim 20, it is unclear what the applicant regards as the thickness of the semiconductor modification layer and the thickness of the second insulative layer. This is because the ratio of the ranges of the thickness recited in the claim range from 2/35 to 2, not range from 1/25 to 1/3 as stated in claim 19, which claim 20 is a dependent claim of.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 9 is rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Zhang et al. (US 2020/0220020 A1, hereinafter “Zhang”).
In regard to claim 9, Zhang teaches a method for manufacturing a thin-film transistor (an embodiment of the present disclosure provides a method for preparing a thin-film transistor) (Figs. 2-4 and paragraph 60), comprising:
sequentially forming a gate (a gate electrode 1) (Fig. 2 and paragraph 62), a first insulative layer (a gate insulating layer 103) (Fig. 3 and paragraph 63), a semiconductor layer (a first thin film 101 forms tan active layer 2) (Figs. 3-4 and paragraph 65), and a source and drain layer on a base substrate (the substrate 100) in a reaction chamber (a second thin film 102 forms a source electrode 3, and a drain electrode 4 on the substrate 100 in a film forming chamber) (Figs. 3-4 and paragraphs 65-66) , wherein the source and drain layer comprises a source (the source electrode 3) and a drain (the drain electrode 4) that are spaced apart and both connected to the semiconductor layer (the source electrode 3, and the drain electrode 4 are shown spaced apart and contacting the active layer 2 in Fig. 4), and a portion of the semiconductor layer is exposed from a gap between the source and the drain (the active layer 2 is shown exposed by a gap in Fig. 4);
controlling a temperature of the reaction chamber to be a first temperature (the first thin film 101 may be formed at a temperature of 300° C) (paragraph 46), and forming a semiconductor modification layer (a passivation layer 104) on a side, distal from the base substrate, of the source and drain layer (the passivation layer 104 is formed on a topside of the source electrode 3, and the drain electrode 4) (Fig. 5 and paragraph 82), wherein the semiconductor modification layer at least covers the portion of the semiconductor layer exposed from the gap (the passivation layer 104 is shown covering the gap of the active layer 2); and
controlling the temperature of the reaction chamber to be a second temperature (the passivation layer 104 can be formed by a plasma enhanced chemical vapor deposition method, and an annealing process can be performed at a temperature of 350° C) (Fig. 5 and paragraph 84), wherein the second temperature is greater than the first temperature (the temperature for forming the first thin film 101 is 300° C while the temperature for forming the passivation layer 104 350° C),
and forming a second insulative layer (a planarization layer 105) on a side, distal from the base substrate, of the semiconductor modification layer (the planarization layer 105 is formed on the sop surface of the passivation layer 104 as shown in Fig. 6) (Fig. 6 and paragraph 82), a concentration of hydrogen in the semiconductor layer is greater than a concentration threshold (the H-atoms contained in the metal oxide would pass the concentration threshold that allows the proper device operation) (paragraphs 54-55), and the first temperature, the second temperature, and a temperature of the reaction chamber in forming the gate, the first insulative layer, the semiconductor layer, and the source and drain layer are all less than a temperature threshold (as the device is formed undamaged, the temperatures used in forming the device are below the damaging thresholds).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 8, 15-17 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Atsuo et al. (JP 2017046008 A; hereinafter “Atsuo”), and further in view of Yamazaki et al. (US 2011/0068336 A1, hereinafter “Yamazaki”).
In regard to claim 1, Atsuo teaches a thin-film transistor (a circuit constituted by a thin film transistor (hereinafter referred to as TFT) (Fig. 4A and paragraph 1), comprising:
a gate (a gate electrode 402), a first insulative layer(gate insulating films 403a) (Fig. 4A and paragraph 96), a semiconductor layer (amorphous semiconductor film 404 in between impurity regions 407) (Fig. 4A and paragraph 98 and 103), a source and drain layer (impurity region 406 is a high-concentration impurity region and becomes a later source / drain region) (Fig. 4C and paragraph 102), a semiconductor modification layer (an insulating layer 405) (Fig. 4B and paragraph 101), and a second insulative layer (an interlayer insulating film 408) that are disposed on a base substrate (a plastic substrate 400) and sequentially laminated in a direction away from the base substrate (the aforementioned layers are shown laminated sequentially in a direction away from the plastic substrate 400 in Fig. 4F) (Fig. 4F and paragraph 95);
wherein the source and drain layer comprises a source and a drain (the processed impurity regions 407 functions as the source and drain layer) that are spaced apart and both connected to the semiconductor layer (the processed impurity regions 407 are shown spaced apart and connected to the amorphous semiconductor film 404 in Fig. 4F) (Fig. 4F and paragraphs 102-103), a portion of the semiconductor layer is exposed from a gap between the source and the drain (the amorphous semiconductor film 404 is shown exposed and in between the processed impurity regions 407 in Fig. 4F), and the semiconductor modification layer at least covers the portion of the semiconductor layer exposed from the gap (the insulating layer 405 is shown covering the exposed amorphous semiconductor film 404 in Fig. 4F).
However, Atsuo doesn’t explicitly teach a number of hydrogen atoms in per cubic centimeter of the semiconductor layer is greater than 16 x 10^20 and less than 26 x 10^20.
Yamazaki teaches a thin film transistor (151), wherein a number of hydrogen atoms in per cubic centimeter of a semiconductor layer (oxide semiconductor layer 113) is greater than 16 x 10^20 and less than 26 x 10^20 (When hydrogen moves to the interface between the oxide semiconductor layer 113 and the oxide insulating layer 107 the hydrogen concentration at the interface is .5 X 1020 atoms/cm3 to 100 X 1020 atoms/cm3 therefore there exist a state where the concertation of the hydrogen atoms per cubic centimeter of a semiconductor layer is greater than 16 x 1020 and less than 26 x 1020) (paragraph 88).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to combine the teachings of Atsuo with the teachings of Yamazaki, since having a preferred concentration of hydrogen within the semiconductor layer increases the reliability of the device as taught by Yamazaki (paragraphs 9 and 88). Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In regard to claim 8, Atsuo teaches a material of the semiconductor modification layer comprises a silicon oxide (the insulating layer 405 is a silicon oxide film) (paragraph 101); and a material of the second insulative layer comprises a silicon oxide (the interlayer insulating film 408 is a silicon oxide) (paragraph 104), or a silicon oxide and a silicon nitride.
However, Atsuo doesn’t explicitly teach wherein a material of the semiconductor layer comprises an oxide.
Yamazaki teaches wherein a material of the semiconductor layer comprises an oxide (the semiconductor layer is an oxide semiconductor layer 123) (paragraph 42).
It would be obvious to one of ordinary skill in the art to combine the teachings of Atsuo with the teachings of Yamazaki to have a material of the semiconductor layer comprises an oxide since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
In regard to claim 15, Atsuo display pane (liquid crystal display panel) (paragraph 1), comprising: a base substrate (a plastic substrate 400) and a plurality of thin-film transistors on the base substrate (a plurality of pixels, and TFT elements are provided in each of the plurality of pixels) (paragraph 119); wherein each of the plurality of thin-film transistors comprises:
a gate (a gate electrode 402), a first insulative layer(gate insulating films 403a) (Fig. 4A and paragraph 96), a semiconductor layer (amorphous semiconductor film 404 in between impurity regions 407) (Fig. 4A and paragraph 98 and 103), a source and drain layer (impurity region 406 is a high-concentration impurity region and becomes a later source / drain region) (Fig. 4C and paragraph 102), a semiconductor modification layer (an insulating layer 405) (Fig. 4B and paragraph 101), and a second insulative layer (an interlayer insulating film 408) that are disposed on the base substrate and sequentially laminated in a direction away from the base substrate (the aforementioned layers are shown laminated sequentially in a direction away from the plastic substrate 400 in Fig. 4F) (Fig. 4F and paragraph 95); wherein the source and drain layer comprises a source and a drain (the processed impurity regions 407 functions as the source and drain layer) that are spaced apart and both connected to the semiconductor layer (the processed impurity regions 407 are shown spaced apart and connected to the amorphous semiconductor film 404 in Fig. 4F) (Fig. 4F and paragraphs 102-103), a portion of the semiconductor layer is exposed from a gap between the source and the drain (the amorphous semiconductor film 404 is shown exposed and in between the processed impurity regions 407 in Fig. 4F), and the semiconductor modification layer at least covers the portion of the semiconductor layer exposed from the gap (the insulating layer 405 is shown covering the exposed amorphous semiconductor film 404 in Fig. 4F).
However, Atsuo doesn’t explicitly teach a number of hydrogen atoms in per cubic centimeter of the semiconductor layer is greater than 16 x 10^20 and less than 26 x 10^20.
Yamazaki teaches a thin film transistor (151), wherein a number of hydrogen atoms in per cubic centimeter of a semiconductor layer (oxide semiconductor layer 113) is greater than 16 x 10^20 and less than 26 x 10^20 (When hydrogen moves to the interface between the oxide semiconductor layer 113 and the oxide insulating layer 107 the hydrogen concentration at the interface is .5 X 1020 atoms/cm3 to 100 X 1020 atoms/cm3 therefore there exist a state where the concertation of the hydrogen atoms per cubic centimeter of a semiconductor layer is greater than 16 x 1020 and less than 26 x 1020) (paragraph 88).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to combine the teachings of Atsuo with the teachings of Yamazaki, since having a preferred concentration of hydrogen within the semiconductor layer increases the reliability of the device as taught by Yamazaki (paragraphs 9 and 88). Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In regard to claim 16, Atsuo teaches wherein the base substrate comprises a display region (a pixel portion 87) and a periphery region (gate side driving circuit 84) surrounding the display region (the gate side driving circuit 84 is shown surrounding the pixel portion 88 in Fig. 5) (Fig. 5 and paragraph 111), the plurality of thin-film transistors are at least disposed in the display region (a plurality of pixels, and TFT elements are provided in each of the plurality of pixels) (paragraph 119), and the display panel further comprises: a signal wiring in the periphery region (it would be known to one skilled in the art that wiring would be present in a gate side driving circuit).
However, Atsuo doesn’t explicitly teach wherein the signal wiring comprises a first wiring segment and a second wiring segment that are disposed in different layers, the display panel further comprises a target insulative layer between the first wiring segment and the second wiring segment, and the first wiring segment is electrically connected to the second wiring segment by a via in the target insulative layer.
Yamazaki teaches wherein a signal wiring comprises a first wiring segment (a gate wiring layer 111b) and a second wiring segment (a second wiring layer 115c) that are disposed in different layers (the gate wiring layer 111b and a second wiring layer 115c are shown in different layers in Fig. 1) (Fig. 1 and paragraph 43), the display panel further comprises a target insulative layer (a second gate insulating layer 102b) between the first wiring segment and the second wiring segment (Fig. 1 and paragraph 42), and the first wiring segment is electrically connected to the second wiring segment by a via (a contact hole 128) in the target insulative layer (a contact hole 128 is formed in the gate insulating layer 102 to reach the gate wiring layer 111b) (paragraph. 43).
It would have been obvious to one skilled in the art to combine the teachings of Atsuo with the teachings of Yamazaki to have the signal wiring comprises a first wiring segment and a second wiring segment that are disposed in different layers, the display panel further comprises a target insulative layer between the first wiring segment and the second wiring segment, and the first wiring segment is electrically connected to the second wiring segment by a via in the target insulative layer since this is a well-known layout that allows for proper separation of components while maintain proper resistances to accommodate device operation.
In regard to claim 17, Atsuo in view of Yamazaki teaches wherein the first wiring segment and the gate are made of the same material by one patterning process (the gate electrode 111a and the gate wiring layer 111b is formed through a first photolithography step) (Yamazaki Fig. 2A and paragraphs 47-48), the second wiring segment and the source and drain layer are made of the same material by one patterning process (a resist a conductive film is selectively etched, so that the second wiring layer (denoted by 115a, 115b and 115c) including the source electrode layer and the drain electrode layer is formed) (Yamazaki paragraph 79), and the target insulative layer is a first insulative layer (the gate insulating layer 102 serves as the target insulative layer and a first insulative layer as shown in Yamazaki Fig. 1).
In regard to claim 21, Atsuo teaches a material of the semiconductor modification layer comprises a silicon oxide (the insulating layer 405 is a silicon oxide film) (paragraph 101); and a material of the second insulative layer comprises a silicon oxide (the interlayer insulating film 408 is a silicon oxide) (paragraph 104), or a silicon oxide and a silicon nitride.
However, Atsuo doesn’t explicitly teach wherein a material of the semiconductor layer comprises an oxide.
Yamazaki teaches wherein a material of the semiconductor layer comprises an oxide (the semiconductor layer is an oxide semiconductor layer 123) (paragraph 42).
It would be obvious to one skilled in the art to combine the teachings of Atsuo with the teachings of Yamazaki to have a material of the semiconductor layer comprises an oxide since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim 5 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Atsuo in view of Yamazaki as applied to claim 1 above, and further in view of Nakano (WO 2015114870 A1).
In regard to claim 5, Atsuo in view of Yamazaki don’t explicitly teach wherein a ratio of a thickness of a semiconductor modification layer to a thickness of a second insulative layer ranges from 1/25 to 1/3.
Nakano teaches wherein a ratio of a thickness of a semiconductor modification layer (a thickness of an etch stop layer 24) to a thickness of a second insulative layer (a thickness of a protective insulating layer 22) ranges from 1/25 to 1/3 (the thickness of the etch stop layer 24 to the protective insulating layer 22 is 1/10) (Fig. 8 and paragraphs 48 and 95).
It would be obvious to one skilled in the art to combine the teachings of Atsuo in view of Yamazaki with the teachings of Nakano to have a ratio of a thickness of a semiconductor modification layer to a thickness of a second insulative layer ranges from 1/25 to 1/3 since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, the specification contains no disclosure of either the critical nature of the claimed [or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen or upon another variable recited in a claim, the Applicant must show that the chosen are critical. In re Woodruf, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
In regard to claim 19, Atsuo in view of Yamazaki don’t explicitly teach wherein a ratio of a thickness of a semiconductor modification layer to a thickness of a second insulative layer ranges from 1/25 to 1/3.
Nakano teaches wherein a ratio of a thickness of a semiconductor modification layer (a thickness of an etch stop layer 24) to a thickness of a second insulative layer (a thickness of a protective insulating layer 22) ranges from 1/25 to 1/3 (The thickness of the etch stop layer 24 to the protective insulating layer 22 is 1/10) (Fig. 8 and paragraphs 48 and 95).
It would be obvious to one skilled in the art to combine the teachings of Atsuo in view of Yamazaki with the teachings of Nakano to have a ratio of a thickness of a semiconductor modification layer to a thickness of a second insulative layer ranges from 1/25 to 1/3 since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Furthermore, the specification contains no disclosure of either the critical nature of the claimed or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen or upon another variable recited in a claim, the Applicant must show that the chosen are critical. In re Woodruf, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang as applied to claim 9 above, and further in view of Koyama et al. (US 2014/0146033 A1; hereinafter “Koyama”).
In regard to claim 10, Zhang doesn’t explicitly teach wherein forming the semiconductor modification layer on the side, distal from the base substrate, of the source and drain layer comprises: introducing silicon tetrahydride to the reaction chamber, and forming the semiconductor modification layer on the side, distal from the base substrate, of the source and drain layer by a chemical vapor deposition process; forming the second insulative layer on the side, distal from the base substrate, of the semiconductor modification layer comprises: introducing silicon tetrahydride and ammonia to the reaction chamber, and forming the second insulative layer on the side, distal from the base substrate, of the semiconductor modification layer by the chemical vapor deposition process; wherein the hydrogen in the semiconductor layer is from hydrogen in the silicon tetrahydride introduced to the reaction chamber in forming the semiconductor modification layer and hydrogen in the silicon tetrahydride and the ammonia introduced to the reaction chamber in forming the second insulative layer.
Koyama teaches a method for manufacturing a thin-film transistor (a method for manufacturing a thin-film transistor) (Fig. 16A and paragraph 288), wherein forming a semiconductor modification layer (an insulating layer 306) on the side, distal from a base substrate (the insulating layer 306 is shown on the top side of a substrate 301 in Fig. 17D) (Fig. 17D and paragraph 271), of a source and drain layer (a layer containing a pair of electrodes 305a and 305b) (Fig. 17A and paragraph 271), comprises: introducing silicon tetrahydride to a reaction chamber, and forming the semiconductor modification layer on the side, distal from the base substrate, of the source and drain layer by a chemical vapor deposition process (a silicon oxynitride film is formed as the insulating layer 306 is formed using CVD and silane gas) (Fig. 17D and paragraphs 304-305); forming a second insulative layer (a silicon nitride oxide film is formed as the insulating layer 307) on the side, distal from the base substrate, of the semiconductor modification layer comprises: introducing silicon tetrahydride and ammonia to the reaction chamber, and forming the second insulative layer on the side, distal from the base substrate, of the semiconductor modification layer by the chemical vapor deposition process (the deposition gasses containing silane as well as ammonia are used in a CVD deposition of insulating layer 307) (Fig. 17D and paragraphs 310-311); wherein the hydrogen in a semiconductor layer (an oxide semiconductor layer 304) is from hydrogen in the silicon tetrahydride introduced to the reaction chamber in forming the semiconductor modification layer and hydrogen in the silicon tetrahydride and the ammonia introduced to the reaction chamber in forming the second insulative layer (it would be known to those skilled in the art that the hydrogen used in the deposition of subsequent layers above an oxide semiconductor layer 304 would be absorbed into the oxide semiconductor layer 304).
It would be obvious to one skilled in the art to combine the teachings of Zhang with Koyama to introduce silicon tetrahydride to the reaction chamber, and forming the semiconductor modification layer on the side, distal from the base substrate, of the source and drain layer by a chemical vapor deposition process; forming the second insulative layer on the side, distal from the base substrate, of the semiconductor modification layer comprises: introducing silicon tetrahydride and ammonia to the reaction chamber, and forming the second insulative layer on the side, distal from the base substrate, of the semiconductor modification layer by the chemical vapor deposition process; wherein the hydrogen in the semiconductor layer is from hydrogen in the silicon tetrahydride introduced to the reaction chamber in forming the semiconductor modification layer and hydrogen in the silicon tetrahydride and the ammonia introduced to the reaction chamber in forming the second insulative layer since this allows forming a transistor with a proper threshold voltage while preventing damage to lower layers within the transistor as taught by Koyama (paragraphs 287, 295 and 357-358).
In regard to claim 11, Zhang in view of Koyama teaches wherein in the hydrogen in the semiconductor layer, a content of hydrogen in silicon tetrahydride introduced to the reaction chamber in forming the semiconductor modification layer is greater than a content of hydrogen in silicon tetrahydride and ammonia introduced to the reaction chamber in forming the second insulative layer (it would be known to one skilled in the art that the hydrogen deposited on a layer closer to the oxide semiconductor layer 304 would be absorbed than the hydrogen deposited on a layer further away. Therefore the examiner takes official notice that the content of hydrogen used in the oxide semiconductor layer 304 would be greater from the content of hydrogen in silicon tetrahydride introduced to the reaction chamber in forming the insulating layer 306 is greater than a content of hydrogen in silicon tetrahydride and ammonia introduced to the reaction chamber in forming the insulating layer 307 of Koyama.)
In regard to claim 12, Zhang doesn’t explicitly teach wherein upon formation of the source and drain layer and prior to formation of the semiconductor modification layer, the method further comprises: controlling the temperature of the reaction chamber to be a third temperature, and performing plasma treatment on the semiconductor layer, wherein the third temperature is less than the temperature threshold.
Koyama teaches upon formation of the source and drain layer and prior to formation of the semiconductor modification layer, the method further comprises:
controlling the temperature of the reaction chamber to be a third temperature (when forming an oxide insulating film between the oxide semiconductor layer 304 and the insulating layer 306 the substrate placed in a treatment chamber of the plasma CVD apparatus and is held at a temperature ranging from 180°C to 400°C) (paragraph 308), and performing plasma treatment on the semiconductor layer (a plasma treatment is provided to the substrate as described) (paragraph 308), wherein the third temperature is less than the temperature threshold (as the layers are not damaged the temperature is less than a threshold).
It would be obvious to one skilled in the art to combine the teachings of Zhang with the teachings of Koyama to have the method further comprise controlling the temperature of the reaction chamber to be a third temperature, and performing plasma treatment on the semiconductor layer, wherein the third temperature is less than the temperature threshold since this allows the formation of layers while preventing damage to underlying layers as taught in Koyama (paragraph 308).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over , Zhang in view of Koyama applied to claim 9 above, and further in view of Yamazaki et al. (US 2011/0068336 A1, hereinafter “Yamazaki”).
In regard to claim 13, Zhang in view of Koyama fail to teach a number of hydrogen atoms in per cubic centimeter of the semiconductor layer is greater than 16 x 1020 and less than 26 x 1020.
Yamazaki teaches a thin film transistor (151), wherein a number of hydrogen atoms in per cubic centimeter of a semiconductor layer (oxide semiconductor layer 113) is greater than 16 x 10^20 and less than 26 x 10^20 (When hydrogen moves to the interface between the oxide semiconductor layer 113 and the oxide insulating layer 107 the hydrogen concentration at the interface is .5 X 1020 atoms/cm3 to 100 X 1020 atoms/cm3 therefore there exist a state where the concertation of the hydrogen atoms per cubic centimeter of a semiconductor layer is greater than 16 x 1020 and less than 26 x 1020) (paragraph 88).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to combine the teachings of Zhang in view of Koyama with the teachings of Yamazaki, since having a preferred concentration of hydrogen within the semiconductor layer increases the reliability of the device as taught by Yamazaki (paragraphs 9 and 88). Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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/SEYON ALI-SIMAH PUNCHBEDDELL/Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893