CTNF 18/289,292 CTNF 101317 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections 07-29-01 AIA Claim 1 objected to because of the following informalities: the claim states the following grammatical error "an ML cost model" it should be "a ML cost model" . Appropriate correction is required. 07-29-01 AIA Claim 1 objected to because of the following informalities: the claim states the following grammatical error "an ML accelerator" it should be "a ML accelerator" . Appropriate correction is required. Claim 2 objected to because "each of layer of the plurality of layers" contains a grammatical error. Correction to "each layer of the plurality of layers " or "each of the plurality of layers" is required. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 6 recites the limitation "the hardware ML accelerator" in line 3 of the claim. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the term will be treated as if it’s referring to “application-specific hardware ML accelerator.” Claims 7-8 depend from claim 6; therefore, they inherit the deficiencies of claim 6 and are also rejected under 112(b). Claim 9 recites the limitation "the hardware ML accelerator" in line 1 of the claim. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the term will be treated as if it’s referring to “application-specific hardware ML accelerator.” Claim 10 recites the term "ML cost model" is ambiguous because the applicant specification uses "ML cost model" broadly, but also distinguishes an "analytical cost model" from a "ML cost model" see applicant specification [0037] " system 100 includes respective cost models 114 that are based on one of two types of cost models, an analytical cost model or ML based cost model ... There are various differences between the analytical cost model and ML based cost model.", and see [0038] "The analytical cost model does not require training data. With a given input, the analytical cost model uses “internal logic” to derive the bottlenecks and output the cost.", and see [0039] "The ML based cost model requires labeled data to train a machine-learning model that can predict at least a latency and throughput." Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claim 1-20 rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. MPEP 2106 (Ill) sets out steps for evaluating whether a claim is drawn to patent-eligible subject matter. The analysis of claims 1-20, in accordance with these steps, follows. Step 1 Analysis: Claims 1-10 are directed to method (processes). Claim 11-19 are directed to a device (machine). Claim 20 is directed to a computer program product (article of manufacture). Therefore, claims 1-20 fall into one of four statutory categories (i.e., process, machine, article of manufacture). As to claim 1, Step 2A Prong 1: this claim recites the following abstract ideas: selecting an architecture that represents a baseline processor configuration; (the limitation describes selecting a baseline processor architecture, which is a mental process implemented in the human mind.) performance data about the architecture in response to modelling the architecture executing computations of the first neural network; (the limitation describe producing performance information from an evaluation of the architecture, which is a mental process implemented in the human mind.) based on the performance data, dynamically tuning the architecture to satisfy a performance objective that represents an expected performance of the architecture (the limitation describes adjusting a design based on evaluated performance to meet an objective which is a mental process implemented in the human mind.) determining customized hardware configurations for implementing each of the plurality of layers of the first neural network; and (the limitation describes determining layer-specific hardware configuration which is a mental evaluation process implemented in the human mind.) generating a configuration of an ML accelerator based on the dynamically tuned architecture and the customized hardware configurations. (the limitation describes formulating an accelerator configuration from selected design parameter, which is a mental process implemented in the human mind.) Step 2A Prong 2 and 2B: the claim recited the following additional elements: A computer-implemented method for generating an application-specific machine-learning (ML) accelerator, the method comprising: (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) modelling, using an ML cost model, how the architecture executes computations of a first neural network that includes a plurality of layers; (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) generating, by the ML cost model, (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) when the architecture implements the first neural network and executes machine-learning computations for a target application; (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) The additional element does not integrate the judicial exception into practical application and does not amount to significantly more than the Judicial exception. As to claim 11, Step 2A Prong 1: this claim recites the following abstract ideas: selecting an architecture that represents a baseline processor configuration; (the limitation describes selecting a baseline processor architecture, which is a mental process implemented in the human mind.) performance data about the architecture in response to modelling the architecture executing computations of the first neural network; (the limitation describe producing performance information from an evaluation of the architecture, which is a mental process implemented in the human mind.) based on the performance data, dynamically tuning the architecture to satisfy a performance objective that represents an expected performance of the architecture (the limitation describes adjusting a design based on evaluated performance to meet an objective which is a mental process implemented in the human mind.) determining customized hardware configurations for implementing each of the plurality of layers of the first neural network; and (the limitation describes determining layer-specific hardware configuration which is a mental evaluation process implemented in the human mind.) generating a configuration of an ML accelerator based on the dynamically tuned architecture and the customized hardware configurations. (the limitation describes formulating an accelerator configuration from selected design parameter, which is a mental process implemented in the human mind.) Step 2A Prong 2 and 2B: the claim recited the following additional elements: A system comprising a processing device and a non-transitory machine-readable storage device storing instructions for generating an application-specific machine-learning (ML) accelerator, the instructions being executable by the processing device to cause performance of operations comprising: (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) modelling, using an ML cost model, how the architecture executes computations of a first neural network that includes a plurality of layers; (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) generating, by the ML cost model, (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) when the architecture implements the first neural network and executes machine-learning computations for a target application; (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) The additional element does not integrate the judicial exception into practical application and does not amount to significantly more than the Judicial exception. As to claim 20, Step 2A Prong 1: this claim recites the following abstract ideas: selecting an architecture that represents a baseline processor configuration; (the limitation describes selecting a baseline processor architecture, which is a mental process implemented in the human mind.) performance data about the architecture in response to modelling the architecture executing computations of the first neural network; (the limitation describe producing performance information from an evaluation of the architecture, which is a mental process implemented in the human mind.) based on the performance data, dynamically tuning the architecture to satisfy a performance objective that represents an expected performance of the architecture (the limitation describes adjusting a design based on evaluated performance to meet an objective which is a mental process implemented in the human mind.) determining customized hardware configurations for implementing each of the plurality of layers of the first neural network; and (the limitation describes determining layer-specific hardware configuration which is a mental evaluation process implemented in the human mind.) generating a configuration of an ML accelerator based on the dynamically tuned architecture and the customized hardware configurations. (The limitation describes formulating an accelerator configuration from selected design parameter, which is a mental process implemented in the human mind.) Step 2A Prong 2 and 2B: the claim recited the following additional elements: A non-transitory machine-readable storage device storing instructions for generating an application-specific machine-learning (ML) accelerator, the instructions being executable by the processing device to cause performance of operations comprising: (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) modelling, using an ML cost model, how the architecture executes computations of a first neural network that includes a plurality of layers; (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) generating, by the ML cost model, (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) when the architecture implements the first neural network and executes machine-learning computations for a target application; (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) The additional element does not integrate the judicial exception into practical application and does not amount to significantly more than the Judicial exception. As to claim 2 and 12, Step 2A Prong 1: This claim does not recite an additional abstract idea, but the claim depends on claim 1 Step 2A Prong 2 and 2B: the claim recited the following additional elements: generating an application-specific hardware ML accelerator based on the customized hardware configurations, (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) wherein the application-specific hardware ML accelerator is optimized to implement each of layer of the plurality of layers of the first neural network when the first neural network is used to execute computations for the target application. (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) The additional element does not integrate the judicial exception into practical application and does not amount to significantly more than the Judicial exception. As to claim 3 and 13, Step 2A Prong 1: this claim recites the following abstract ideas: wherein the performance objective comprises a plurality of discrete objectives (The limitation describes breaking an optimization goal into multiple discrete objectives, which is a mental process implemented in the human mind.) Step 2A Prong 2 and 2B: the claim recited the following additional elements: and generating the application-specific ML accelerator comprises: generating an application-specific hardware ML accelerator configured to satisfy each discrete objective of the plurality of discrete objectives when the application-specific hardware ML accelerator executes computations for the target application. (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) The additional element does not integrate the judicial exception into practical application and does not amount to significantly more than the Judicial exception. As to claim 4 and 14, Step 2A Prong 1: This claim does not recite an additional abstract idea, but the claim depends on claim 3. Step 2A Prong 2 and 2B: the claim recited the following additional elements: modeling, by the ML cost model, use of the architecture to execute each layer of the plurality of layers of the first neural network; and (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) in response to modelling use of the architecture to execute each layer, generating, by the ML cost model, performance parameters of the architecture for each of the plurality of layers. (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) The additional element does not integrate the judicial exception into practical application and does not amount to significantly more than the Judicial exception. As to claim 5 and 15, Step 2A Prong 1: this claim recites the following abstract ideas: the performance parameters correspond to each discrete objective of the plurality of discrete objectives; (the limitation describes associating performance parameters with a design objective, which is a mental process implemented in the human mind.) the plurality of discrete objectives comprises at least one of: a threshold processing latency, a threshold power consumption, a threshold data throughput, and a threshold processor utilization. (this limitation describes evaluating latency, power, throughput, or utilization threshold, which is a mental process implemented in the human mind.) Step 2A Prong Two and Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception under step 2B. Thus, the judicial exception is not integrated into a practical application (see MPEP 2106.04(d) I.), failing step 2A prong 2. The claim is ineligible. As to claim 6 and 16, Step 2A Prong 1: This claim does not recite an additional abstract idea, but the claim depends on claim 2.Step 2A Prong 2 and 2B: the claim recited the following additional elements: wherein dynamically tuning the architecture comprises: determining, for an input tensor, a mapping of computations that causes the application-specific hardware ML accelerator to utilize a threshold percentage of hardware computing units of the hardware ML accelerator when the application-specific hardware ML accelerator processes the input tensor; and dynamically tuning the architecture based on the determined mapping. (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) The additional element does not integrate the judicial exception into practical application and does not amount to significantly more than the Judicial exception. As to claim 7 and 17, Step 2A Prong 1: This claim does not recite an additional abstract idea, but the claim depends on claim 6. Step 2A Prong 2 and 2B: the claim recited the following additional elements: dynamically tuning the architecture based on operations performed by each of a plurality of ML cost models of a global tuner; and (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) dynamically tuning the architecture based on operations performed by at least one of a random tuner or a simulated annealing tuner of the global tuner. (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) The additional element does not integrate the judicial exception into practical application and does not amount to significantly more than the Judicial exception. As to claim 8 and 18, Step 2A Prong 1: This claim does not recite an additional abstract idea, but the claim depends on claim 6. Step 2A Prong 2 and 2B: the claim recited the following additional elements: wherein the architecture is for an integrated circuit, comprises one or more hardware blocks of the integrated circuit, and dynamically tuning the architecture comprises: (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) for each of the one or more hardware blocks: dynamically tuning the architecture to satisfy a respective performance objective for the hardware block when the architecture implements the first neural network and executes computations for the target application using the first neural network. (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) The additional element does not integrate the judicial exception into practical application and does not amount to significantly more than the Judicial exception. As to claim 9, Step 2A Prong 1: This claim does not recite an additional abstract idea, but the claim depends on claim 6. Step 2A Prong 2 and 2B: the claim recited the following additional elements: the configuration of the hardware ML accelerator specifies customized software configurations for the first neural network; and (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) generating the application-specific hardware ML accelerator comprises, generating the application-specific hardware ML accelerator based on the customized hardware configurations and the customized software configurations. (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) The additional element does not integrate the judicial exception into practical application and does not amount to significantly more than the Judicial exception. As to claim 10 and 19, Step 2A Prong 1: This claim does not recite an additional abstract idea, but the claim depends on claim 6. Step 2A Prong 2 and 2B: the claim recited the following additional elements: the ML cost model is an architecture-aware cost model that includes one or more individual analytical models; and (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) the architecture-aware cost model is configured to estimate performance of the architecture based on a deterministic dataflow of data that is processed using the architecture. (The limitation describes mere instruction to apply abstract idea using a generic computer, which is a well-understood, routine, conventional activity, see MPEP 2106.05(d)(II)(i)) The additional element does not integrate the judicial exception into practical application and does not amount to significantly more than the Judicial exception. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1, 11, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al. (US 20200410389 A1) in view of Lin et al. (US 20180114117 A1) . As to claim 1, Jain teaches selecting an architecture that represents a baseline processor configuration; (see Jain paragraph [0019] “The SOC 200 includes a machine learning (ML) module 202, a reset controller 204, which includes a reset timer 206 and a ML boot module 208, a debug module 210, a memory 212, an interconnect framework 214, multiple cores (CPU.sub.1 . . . CPU.sub.n) 216 and multiple hardware IP blocks (HW IP.sub.1 . . . HW IP.sub.m) 218 (e.g., accelerators).”) modelling, using an ML cost model, how the architecture executes computations of a first neural network that includes a plurality of layers; (see Jain paragraph [0018] “The ML module 104 observes the performance of the hardware blocks 102 and maps an observation of the current performance to a state. Then the ML module 104 uses a neural network to identify an action to be taken based on the state and maps the action to be taken to a new set of parameter values for the hardware blocks 102.”) generating, by the ML cost model, performance data about the architecture in response to modelling the architecture executing computations of the first neural network; (see Jain paragraph [0021] “The debug module 210 also uses known techniques, such as performance counters, to measure system performance. The collected performance metrics are transferred from the debug module 210 to the ML module 202 via a ML_SOC_PERF interface 224.”) based on the performance data, dynamically tuning the architecture to satisfy a performance objective that represents an expected performance of the architecture when the architecture implements the first neural network and executes machine-learning computations for a target application; (see Jain paragraph [0022] “The ML module 202 configures the SOC 200 to meet desired performance/power targets, which may be programmed or set by a user. The ML module 202 configures the SOC 200 by setting configuration parameters of the cores 216, IP blocks 218, interconnect framework 214 and memory 212.”, and see Jain paragraph [0052] “At step 502, the ML module 202 uses the ML_SOC_PERF interface to measure the current SOC performance metrics and maps the observation to a ML network state information. Then the ML module uses the ML network and its current state to compute the next action to be taken to achieve the performance target.”) Jain doesn’t explicitly teaches "plurality of layers", "A computer-implemented method for generating an application-specific machine-learning (ML) accelerator, the method comprising:", "in response to dynamically tuning the architecture, determining customized hardware configurations for implementing each of the plurality of layers of the first neural network; and", and "generating a configuration of an ML accelerator based on the dynamically tuned architecture and the customized hardware configurations." However. Lin teaches A computer-implemented method for generating an application-specific machine-learning (ML) accelerator, the method comprising: (see Lin Paragraph [0038] “FIG. 4 is a flow chart illustrating a method for accelerating a trained DNN model (including a DNN net file and weights) in an FPGA, according to an embodiment of the present invention.”) plurality of layers; (see Lin paragraph [0033] “Such net file, referring now to FIG. 3, may include information of a plurality of layers 310_1 to 310_N, each of which corresponds to at least one of neural layers 321 to 326.”) in response to dynamically tuning the architecture, determining customized hardware configurations for implementing each of the plurality of layers of the first neural network; and (see Lin paragraph [0031] “Verilog source files 230a (shown in the right side of FIG. 2B) comprising source code files 231 to 234 (corresponding to respective neural layers 211 to 214) of the net definition file 210a are generated.”) generating a configuration of an ML accelerator based on the dynamically tuned architecture and the customized hardware configurations. (see Lin paragraph [0044] “In step S460, an executable FPGA bit file 23 is generated using the one or more source files 22.”) It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the invention of Jain To include Lin's DNN conversion platform that receives a DNN net file, analyzes the DNN net file to identify a plurality of neural layers because Lin expressly recognizes that DNNs require intense computation, that existing FPGA RTL flows require considerable programming effort, and that "a need exists for improvements in converting of a DNN model to an FPGA RTL-level implementation." Lin [0005] As to claim 11, this is directed to a system that corresponds to the method of claim 1, See the rejection for claim 1 above, which also applies to claim 11. In addition, Lin teaches a system comprising a processing device and a non-transitory machine-readable storage device storing instructions for generating an application-specific machine-learning (ML) accelerator, the instructions being executable by the processing device to cause performance of operations comprising: (see paragraph [0008] " processor and memory communicatively coupled to the at least one processor. The memory stores processor readable program instructions that, when executed by the at least one processor, cause the at least one processor to receive a DNN….") As to claim 20, this is directed to a system that corresponds to the method of claim 1, See the rejection for claim 1 above, which also applies to claim 20. In addition, Lin teaches A non-transitory machine-readable storage device storing instructions for generating an application-specific machine-learning (ML) accelerator, the instructions being executable by the processing device to cause performance of operations comprising (see paragraph [0008] "processor and memory communicatively coupled to the at least one processor. The memory stores processor readable program instructions that, when executed by the at least one processor, cause the at least one processor to receive a DNN….") 07-21-aia AIA Claim (s) 2-10, and 12-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al. (US 20200410389 A1) in view of Lin et al. (US 20180114117 A1) and further in view of Ebcioglu et al. (US 20150317190 A1) . As to claim 2, Jain as modified by Lin teaches the method of claim 1, wherein the application-specific hardware ML accelerator is optimized to implement each of layer of the plurality of layers of the first neural network (see Lin paragraph [0031] “Verilog source files 230a (shown in the right side of FIG. 2B) comprising source code files 231 to 234 (corresponding to respective neural layers 211 to 214) of the net definition file 210a are generated.”) when the first neural network is used to execute computations for the target application. (see Lin paragraph [0038] “FIG. 4 is a flow chart illustrating a method for accelerating a trained DNN model (including a DNN net file and weights) in an FPGA, according to an embodiment of the present invention.”) Jain-Lin does not explicitly teach "generating an application-specific hardware ML accelerator based on the customized hardware configurations" However, Ebcioglu teaches generating an application-specific hardware ML accelerator based on the customized hardware configurations, (see Ebcioglu paragraph [0056] “The process of application-specific hardware generation from a high level program specification is known as high-level synthesis. As a result of this process, the high level representation of the program, which is expressed using a high level programming language such as C or C++, is converted into hardware which is typically expressed in a hardware description language (HDL).” It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the invention of Jain-Lin To include Application specific hardware generated processor, because Ebcioglu teaches that application-specific hardware generation through high-level synthesis converts a high-level program representation into HDL hardware and that the specialized register-transfer level hardware provides greater flexibility and can overcome limitations of software-only or general purpose parallelization. Ebcioglu paragraph [0056] As to claim 3, Jain-Lin as modified by Ebcioglu teaches the method of claim 2, wherein the performance objective comprises a plurality of discrete objectives and generating the application-specific ML accelerator comprises: (see Jain paragraph [0022] “The ML module 202 configures the SOC 200 to meet desired performance/power targets, which may be programmed or set by a user.”) generating an application-specific hardware ML accelerator configured to satisfy each discrete objective of the plurality of discrete objectives (see Jain paragraph [0052] “Then the ML module uses the ML network and its current state to compute the next action to be taken to achieve the performance target. This computed action is mapped by the ML network to output the next set of SOC configuration parameters.”) when the application-specific hardware ML accelerator executes computations for the target application. (See Jain paragraph [0058] “FIG. 6 shows an example dataflow 600, where the dataflow comprises of a chain of computation operations that are identified by a sequence of hardware or software performing specific operations on a given data buffer.”) As to claim 4, Jain-Lin as modified by Ebcioglu teaches the method of claim 3, wherein generating the performance data comprises: modeling, by the ML cost model, use of the architecture to execute each layer of the plurality of layers of the first neural network; and (see Lin paragraph [0032] “According to some embodiments of the present invention (as will be discussed in more detail with reference to FIG. 3), the DNN recognition platform 30 may be implemented based on a convolutional neural network (CNN). The CNN may include multiple layers such as a convolution layer, a pooling layer, a ReLU layer, a fully connected layer, a loss layer, and so on.”) in response to modelling use of the architecture to execute each layer, generating, by the ML cost model, performance parameters of the architecture for each of the plurality of layers. (See Lin paragraph [0041] “In step S430, a parallelism level with respect to kernel or channel is optimized based on FPGA resources. In another example, a parallelism level is optimized by determining the KPF or CPF, based on FPGA resources. In another example, optimizing the parallelism level may include determining the KPF and/or CPF of each neural layer.”) As to claim 5, Jain-Lin as modified by Ebcioglu teaches the method of claim 4, the performance parameters correspond to each discrete objective of the plurality of discrete objectives; and (see Jain paragraph [0021] “The collected performance metrics are transferred from the debug module 210 to the ML module 202 via a ML_SOC_PERF interface 224.”) the plurality of discrete objectives comprises at least one of: a threshold processing latency, a threshold power consumption, a threshold data throughput, and a threshold processor utilization. (see Jain [0041] “At step 306, the performance of the system is measured, and metrics are determined, such as core execution speed, memory read and write times, and power consumed.”) As to claim 6. Jain-Lin as modified by Ebcioglu teaches the method of claim 2, dynamically tuning the architecture based on the determined mapping. (See Jain paragraph [0052] “Then the ML module uses the ML network and its current state to compute the next action to be taken to achieve the performance target. This computed action is mapped by the ML network to output the next set of SOC configuration parameters.”) Jain doesn’t teach " wherein dynamically tuning the architecture comprises: determining, for an input tensor, a mapping of computations", "that causes the application-specific hardware ML accelerator to utilize a threshold percentage of hardware computing units of the hardware ML accelerator", and "when the application-specific hardware ML accelerator processes the input tensor; and" However, Lin teaches wherein dynamically tuning the architecture comprises: determining, for an input tensor, a mapping of computations (see Lin paragraph [0050] “In some embodiments, a data model (e.g., Blob depicted in FIG. 5A), is used in each neural layer of the DNN recognition platform 30, has a structure that models the data as multi-dimensional.”) that causes the application-specific hardware ML accelerator to utilize a threshold percentage of hardware computing units of the hardware ML accelerator (see Lin [0032] “In some embodiments however, resource constraints of the FPGA 30a (FIG. 1) may limit parallelisms to the kernel and channel.”) when the application-specific hardware ML accelerator processes the input tensor; and (see Lin paragraph [0048] “the DNN recognition platform 30 may also use a uniform operation model which can be applied to various neural layers 321 to 326 (FIG. 3).”) As to claim 7, Jain-Lin as modified by Ebcioglu teaches the method of claim 6, wherein dynamically tuning the architecture comprises: dynamically tuning the architecture based on operations performed by each of a plurality of ML cost models of a global tuner; and (see Jain paragraph [0036] “There can be multiple approaches to build the ML network ranging from using a simple lookup table to select hyper-parameters of the ML network, to complex techniques including transfer learning or using complex automatic approaches like using neural networks to design neural networks.”) dynamically tuning the architecture based on operations performed by at least one of a random tuner or a simulated annealing tuner of the global tuner. (See Jain paragraph [0051] “the ML module sequences through various different ML network topologies and hyper-parameters to identify the best performing ML network for the use case.”) As to claim 8, Jain-Lin as modified by Ebcioglu teaches the method of claim 6, wherein the architecture is for an integrated circuit, comprises one or more hardware blocks of the integrated circuit, and dynamically tuning the architecture comprises: (see Jain paragraph [0017] “Contemporary SOCs are quite complex and heterogeneous and are typically designed to include multiple cores, multiple hardware accelerators, an interconnection framework, and multiple memories.”, and see Jain paragraph [0018] “Referring now to FIG. 1, a simplified schematic block diagram of a SOC 100 including a plurality of hardware blocks 102 and a machine learning (ML) module or agent 104, in accordance with an embodiment of the present invention, is shown.”) for each of the one or more hardware blocks: dynamically tuning the architecture to satisfy a respective performance objective for the hardware block (see Jain paragraph [0022] “The ML module 202 configures the SOC 200 by setting configuration parameters of the cores 216, IP blocks 218, interconnect framework 214 and memory 212.”) when the architecture implements the first neural network and executes computations for the target application using the first neural network. (See Jain paragraph [0021] “The debug module 210 is connected to the interconnect framework 214 and is configured to automatically learn the data flow pertaining to a particular use case executing on the SOC 200 using known tracing techniques.”) As to claim 9, Jain-Lin as modified by Ebcioglu teaches the method of claim 6, wherein: the configuration of the hardware ML accelerator specifies customized software configurations for the first neural network; and (see Lin paragraph [0046] “In step S480, user application program interfaces (APIs) to access the FPGA 30a are generated.”) Lin doesn’t teach "generating the application-specific hardware ML accelerator comprises, generating the application-specific hardware ML accelerator based on the customized hardware configurations and the customized software configurations." However, Ebcioglu teaches generating the application-specific hardware ML accelerator comprises, generating the application-specific hardware ML accelerator based on the customized hardware configurations and the customized software configurations. (See Ebcioglu paragraph [1268] “The method in the present document can be used to execute only some parts of the input sequential application in hardware. This requires a partitioning of the application into two parts, one that will be compiled into hardware and the other that will be compiled into a software executable that will be executed on a general purpose processor (i.e., the host machine).”, and see Ebcioglu paragraph [1270] “The resulting parallel program contains the two source files where the accelerated regions are deleted and a call to a special startAccelerator subroutine is inserted at the entry point of the accelerated region.”) As to claim 10, Jain-Lin as modified by Ebcioglu teaches the method of claim 6, wherein: the ML cost model is an architecture-aware cost model that includes one or more individual analytical models; and (see Jain “The ML module 202 configures the SOC 200 to meet desired performance/power targets, which may be programmed or set by a user.”) the architecture-aware cost model is configured to estimate performance of the architecture based on a deterministic dataflow of data that is processed using the architecture. (See Jain paragraph [0021] “The debug module 210 also uses known techniques, such as performance counters, to measure system performance. The collected performance metrics are transferred from the debug module 210 to the ML module 202 via a ML_SOC_PERF interface 224.”, and see Jain paragraph [0043] “At step 312, the ML module 202 uses the debug module 210 to detect the data flow. As discussed above, the data flow is a unique chain of computation operations that are identified by a unique sequence of the cores 216 or IP blocks 218 performing specific operations on a given data buffer as it undergoes transformation in the system 200.”) As to claim 12, this is directed to a system that corresponds to the method of claim 2, See the rejection for claim 2 above, which also applies to claim 12. As to claim 13, this is directed to a system that corresponds to the method of claim 3, See the rejection for claim 3 above, which also applies to claim 13. As to claim 14, this is directed to a system that corresponds to the method of claim 4, See the rejection for claim 4 above, which also applies to claim 14. As to claim 15, this is directed to a system that corresponds to the method of claim 5, See the rejection for claim 5 above, which also applies to claim 15. As to claim 16, this is directed to a system that corresponds to the method of claim 6, See the rejection for claim 6 above, which also applies to claim 16. As to claim 17, this is directed to a system that corresponds to the method of claim 7, See the rejection for claim 7 above, which also applies to claim 17. As to claim 18, this is directed to a system that corresponds to the method of claim 8, See the rejection for claim 8 above, which also applies to claim 18. As to claim 19, this is directed to a system that corresponds to the method of claim 9, See the rejection for claim 9 above, which also applies to claim 19. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDULLAH K ABOUD whose telephone number is (571)272-0025. The examiner can normally be reached Mon-Fri 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Li B Zhen, can be reached at (571) 272-3768. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ABDULLAH KHALED ABOUD/Examiner, Art Unit 2121 /Li B. Zhen/Supervisory Patent Examiner, Art Unit 2121 Application/Control Number: 18/289,292 Page 2 Art Unit: 2121 Application/Control Number: 18/289,292 Page 3 Art Unit: 2121 Application/Control Number: 18/289,292 Page 4 Art Unit: 2121 Application/Control Number: 18/289,292 Page 5 Art Unit: 2121 Application/Control Number: 18/289,292 Page 6 Art Unit: 2121 Application/Control Number: 18/289,292 Page 7 Art Unit: 2121 Application/Control Number: 18/289,292 Page 8 Art Unit: 2121 Application/Control Number: 18/289,292 Page 9 Art Unit: 2121 Application/Control Number: 18/289,292 Page 10 Art Unit: 2121 Application/Control Number: 18/289,292 Page 11 Art Unit: 2121 Application/Control Number: 18/289,292 Page 12 Art Unit: 2121 Application/Control Number: 18/289,292 Page 13 Art Unit: 2121 Application/Control Number: 18/289,292 Page 14 Art Unit: 2121 Application/Control Number: 18/289,292 Page 15 Art Unit: 2121 Application/Control Number: 18/289,292 Page 16 Art Unit: 2121 Application/Control Number: 18/289,292 Page 17 Art Unit: 2121 Application/Control Number: 18/289,292 Page 18 Art Unit: 2121 Application/Control Number: 18/289,292 Page 19 Art Unit: 2121 Application/Control Number: 18/289,292 Page 20 Art Unit: 2121 Application/Control Number: 18/289,292 Page 21 Art Unit: 2121 Application/Control Number: 18/289,292 Page 22 Art Unit: 2121 Application/Control Number: 18/289,292 Page 23 Art Unit: 2121 Application/Control Number: 18/289,292 Page 24 Art Unit: 2121 Application/Control Number: 18/289,292 Page 25 Art Unit: 2121
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