DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/07/2023 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4, 6,-7, 9, 16, 17 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Rancour et al (US Published Patent Application No. 20200042869, "Rancour"), in view of Kello (US Published Patent Application No. 20100312736).
In regard to claim 1, Rancour teaches two or more analog signal processing circuits each configured for generating a component signal for a feedback signal of a respective artificial neuron circuit, comprising: an input stage configured to receive and adapt an output signal of said artificial neuron circuit; (Rancour, paragraph 0024, “As an example, described below is a Self-trained Multi-layer Analog Real-Time ("SMART") ANN circuit architecture that solves a pattern recognition problem for numbers 0-9 in about 20 μs, using an assemblage of electronic components. The disclosed architecture enables real-time processing for both ANN function and training;” and paragraph 0027, “In this context, a perceptron is an artificial neuron with an output value O or 1 based on whether the weighted sum of its inputs (e.g., inputs input1 , input2 , input3 , ... , input33 , input34 and input35 of perceptron 100) is respectively less than or greater than a known threshold value.”)
a first multiplier circuit configured to generate a first product signal indictive of multiplication of the adapted output signal by a previously generated feedback signal of said artificial neuron circuit; (Rancour, paragraph 0035, “Reference source not found. as abstract multiplier and adder symbols. For the perceptron 100, there are ten such training circuits 600 in total, one for each output-layer neuron, for example, one for each of the numerals 0-9. Signals "Weightl", "Weight2", ... "Weightl0" are common to all ten output-layer neurons, whereas each output-layer neuron receives a unique set of"Activation" signals from the hidden (inner) layer, namely the signals generated by that neuron's corresponding input numeral.”)
a weight update circuit configured to generate a new weight signal based on a multiplication of a previously generated weight signal of said analog signal processing circuit by a summation of said previously generated weight signal with said first product signal; and (Rancour, paragraph 0009, “The training circuitry may be configured to train the artificial neural network by adjusting the weight of the at least one artificial neuron. The training circuitry may include a track and hold circuit that provides a value based on a weight to the artificial neural network circuitry, wherein the weight may be generated based on an output-layer of the artificial neural network circuitry.” and paragraph 0025, “Artificial neurons and inputs may have a weight that adjusts as learning proceeds (for example, each input to an artificial neuron may be separately weighted). The weight increases or decreases the strength of the signal at a connection. Artificial neurons may have a threshold such that the signal is only sent if the aggregate signal crosses that threshold.”)
a second multiplier circuit configured to generate said signal component as a second product signal based on a multiplication of said output signal by said new weight signal; (Rancour, paragraph 0040, “Each training circuit 600 has feedback control of one specific weight value. All ten output neurons receive the same ten weights. Each output neuron receives its own unique set of "Activation" signals corresponding to the specific input numeral that the neuron is to "recognize" or "ignore."”)
a summation circuit configured to generate a summation signal indicative of a summation of the second product signals from said two or more analog signal processing circuits; and (Rancour, paragraph 0050, “As another example, for an XOR gate, the amplitude of the bias element is zero and the first and second phase shifts, for 920 and 922, are O degrees and 180 degrees respectively. Therefore, the summation of the input signals by summer 928 amounts to a subtraction. As a result, no explicit phase-shifting circuitry is required.”)
a factor generator circuit configured to subtract from the summation signal from the summation circuit a reference signal and to thereby generate the feedback signal of said two or more artificial neuron circuits. (Rancour, paragraph 0050, “As another example, for an XOR gate, the amplitude of the bias element is zero and the first and second phase shifts, for 920 and 922, are O degrees and 180 degrees respectively. Therefore, the summation of the input signals by summer 928 amounts to a subtraction. As a result, no explicit phase-shifting circuitry is required.”)
However, Rancour does not explicitly teach said respective two or more artificial neurons circuits, each of said two or more artificial neuron circuits is configured to generate an output signal driving a respective one of said two or more analog signal processing circuits;
Kello teaches said respective two or more artificial neurons circuits, each of said two or more artificial neuron circuits is configured to generate an output signal driving a respective one of said two or more analog signal processing circuits; (Kello, paragraph 0065, “each artificial neuron is configured to receive an input signal from and send an output signal to one or more of the other artificial neurons through one of the connections;” and paragraph 0076, “In another aspect, the systems of this disclosure further comprise an external receiving device an external receiving device connected to the network of artificial neurons, wherein one or more artificial neurons sends an output signal to the external receiving device.”)
Rancour and Kello are related to the same field of endeavor (i.e. neural networks). In view of the teachings of Kello, it would have been obvious for a person with ordinary skill in the art to apply the teachings of Kello to Rancour before the effective filing date of the claimed invention in order to optimize the performance of an artificial neural network. (Kello, paragraph 0005, “To optimize the performance of an artificial neural network, a balance has to be struck between unresponsive and overly responsive spiking by relating their dynamics to a critical branching process.”)
In regard to claim 4, Rancour and Kello teach the system of claim 1.
Rancour further teaches wherein at least one of the first and second multiplier circuits comprises squaring and subtraction circuits configured for the generation of said first product signal. (Rancour, paragraph 0031, “In this example, the aggregation function for each hidden-layer neuron consists of 35 interconnected ANALOG DEVICES AD633AN four-quadrant analog multiplier chips. FIG. 3 is a functional block diagram 300 for the AD633AN four-quadrant analog multiplier chip. The chip's transfer function is (X l - X2)·(Yl -Y2)/ W = 10 V +Z.”)
Rancour and Kello are combinable for the same rationale as set forth above with respect to claim 1.
In regard to claim 6, Rancour and Kello teach the system of claim 1.
Kello further teaches wherein at least one of the first and second multiplier circuits comprises a scaling circuit configured to factor out of the product signal thereby generated a scaling constant. (Kello, paragraph 0164, “The tuning algorithms were designed to scale (renormalize) post-synaptic and pre-synaptic connection weights, respectively. The post-synaptic algorithm scales weights so that a given spike on neuron i produced at time tis expected to be followed at t+ I by exactly one corresponding spike over its post-synaptic neurons.”)
Rancour and Kello are combinable for the same rationale as set forth above with respect to claim 1.
In regard to claim 7, Rancour and Kello teach the system of claim 1.
Kello further teaches wherein the output signal is a temporally integrated signal generated by the artificial neuron circuit, and wherein said artificial neuron circuit is configured to control at least one of a rise time, width, fall time, and refractory period, of output signals thereby generated. (Kello, paragraph 0112, “Alternatively, at each time step t, the membrane potential of every neuron can be determined from the weighted sum of spikes from presynaptic neurons, as well as from external inputs,” and paragraph 0117, “an analogue of the refractory period, which in some embodiments is 1.0;”)
Rancour and Kello are combinable for the same rationale as set forth above with respect to claim 1.
In regard to claim 9, Rancour and Kello teach the system of claim 7.
Kello further teaches wherein the artificial neuron circuit comprises at least one of the following: a scaling input stage configured to receive one or more input signals and respective one or more scaling signals, at least one of said one or more scaling signals associated with a weight signal generated by the weight update circuit, adapt each of said input signals in accordance with its respective scaling signal, and generate an input current of said artificial neuron circuit based on the scaled input signals; (Kello, paragraph 0164, “The tuning algorithms were designed to scale (renormalize) post-synaptic and pre-synaptic connection weights, respectively. The post-synaptic algorithm scales weights so that a given spike on neuron i produced at time tis expected to be followed at t+ I by exactly one corresponding spike over its post-synaptic neurons.”)
a leaky integrate and fire (LIF) neuron circuit configured to generate spike signals based on the input current from the scaling input stage, said LIF neuron circuit comprising a soma module configured to regulate a leakage current used for charging a soma capacitive element thereof; (Kello, paragraph 0182, “In this example, a self-tuning algorithm is developed for use with leaky integrate-and-fire (LIF) neurons that adjusts postsynaptic weights to a critical branching point between subcritical and supercritical spiking dynamics. The tuning algorithm stabilizes spiking activity in the sense that spikes propagate through the network without multiplying to the point of wildfire activity, and without dying out so quickly that information cannot be transmitted and processed. The critical branching point is also found to maximize memory and representational capacity of the network when used as liquid state machine.”)
a spike generator configured to generate first and second driving currents whenever a voltage over the soma capacitive element is greater than a defined voltage level, said first driving current used for charging the soma capacitive element, and said second driving current used for generating the spike signals, and wherein said analog signal processing circuit comprises a spike shaping module configured to: (Kello, paragraph 0182, “In this example, a self-tuning algorithm is developed for use with leaky integrate-and-fire (LIF) neurons that adjusts postsynaptic weights to a critical branching point between subcritical and supercritical spiking dynamics. The tuning algorithm stabilizes spiking activity in the sense that spikes propagate through the network without multiplying to the point of wildfire activity, and without dying out so quickly that information cannot be transmitted and processed. The critical branching point is also found to maximize memory and representational capacity of the network when used as liquid state machine.”)
regulate a discharge current of said soma capacitive element, charge a spike shaping capacitive element thereof with the second driving current from the spike generator, and regulate the discharge current of the soma capacitive element according to a voltage level of said spike shaping capacitive element. (Kello, paragraph 0182, “In this example, a self-tuning algorithm is developed for use with leaky integrate-and-fire (LIF) neurons that adjusts postsynaptic weights to a critical branching point between subcritical and supercritical spiking dynamics. The tuning algorithm stabilizes spiking activity in the sense that spikes propagate through the network without multiplying to the point of wildfire activity, and without dying out so quickly that information cannot be transmitted and processed. The critical branching point is also found to maximize memory and representational capacity of the network when used as liquid state machine.”)
Rancour and Kello are combinable for the same rationale as set forth above with respect to claim 1.
In regard to claim 16, Rancour and Kello teach the system of claim 9.
Kello further teaches wherein the spike generator comprises first and second invertors, said second invertor configured to generate the second driving current, and to discharge the spike shaping capacitive element whenever the voltage over the soma capacitive element is smaller than the defined voltage level. (Kello, paragraph 0192, “The tuning algorithm adjusts the postsynaptic weights of a given model neuron so that, when it spikes, one and only one spike is expected to follow over the postsynaptic array of neurons. The algorithm weights each descendent spike relative to its number of ancestor spikes n over its presynaptic array on the preceding time step, i.e., 1/n. The algorithm increases weights projecting out from a given postsynaptic neuron by a factor~ when the sum of weighted spikes over its postsynaptic array is greater than one. The algorithm decreases weights by ~ when the sum is less than one (no change is made when equal to one).”)
Rancour and Kello are combinable for the same rationale as set forth above with respect to claim 1.
In regard to claim 17, Rancour and Kello teach the system of claim 9.
Kello further teaches comprising an integration module configured to regulate a charging current of an integration capacitive element thereof according to a voltage level over the spike shaping capacitive element, and output the temporally integrated signal based on a voltage level of said integration capacitive element. (Kello, paragraph 0182, “In this example, a self-tuning algorithm is developed for use with leaky integrate-and-fire (LIF) neurons that adjusts postsynaptic weights to a critical branching point between subcritical and supercritical spiking dynamics. The tuning algorithm stabilizes spiking activity in the sense that spikes propagate through the network without multiplying to the point of wildfire activity, and without dying out so quickly that information cannot be transmitted and processed. The critical branching point is also found to maximize memory and representational capacity of the network when used as liquid state machine.”)
Rancour and Kello are combinable for the same rationale as set forth above with respect to claim 1.
In regard to claim 26, Rancour teaches A method of generating a signal component for a feedback signal of an artificial neuron, the method comprising generating a first product signal based on an output signal of said artificial neuron and a previously generated feedback signal of said artificial neuron, generating a new weight signal from a previously generated weight signal and a summation of said previously generated weight signal with said first product signal, and (Rancour, paragraoh 0050, “For example, to implement an AND gate, one would set the first and second phase shifts, for 920 and 922 respectively, to 180 degrees. The bias phase shift 926 would be zero degrees, and the amplitude of the bias signal 924 would be unity. As another example, for an XOR gate, the amplitude of the bias element is zero and the first and second phase shifts, for 920 and 922, are O degrees and 180 degrees respectively. Therefore, the summation of the input signals by summer 928 amounts to a subtraction. As a result, no explicit phase-shifting circuitry is required.”)
However, Rancour does not explicitly teach generating said signal component from a second product signal generated based on said output signal and said new weight signal.
Kello teaches generating said signal component from a second product signal generated based on said output signal and said new weight signal. (Kello, paragraph 0164, “The tuning algorithms were designed to scale (renormalize) post-synaptic and pre-synaptic connection weights, respectively. The post-synaptic algorithm scales weights so that a given spike on neuron i produced at time tis expected to be followed at t+ I by exactly one corresponding spike over its post-synaptic neurons.”)
Rancour and Kello are combinable for the same rationale as set forth above with respect to claim 1.
Claims 2, 19, 25 and 27-31 are rejected under 35 U.S.C. 103 as being unpatentable over Rancour, in view of Kello and in further view of Danial et al (US Published Patent Application No. 20200272893, "Danial").
In regard to claim 2, Rancour and Kello teach the system of claim 1.
However, Rancour and Kello do not explicitly teach wherein the input stage comprising a resistor ladder circuit configured to adapt the output signal of the artificial neuron circuit according to a predefined adaptation signal indicative of a learning rate of said artificial neuron circuit by adjusting at least one resistive element thereof in accordance with the predefined adaptation signal.
Danial teaches wherein the input stage comprising a resistor ladder circuit configured to adapt the output signal of the artificial neuron circuit according to a predefined adaptation signal indicative of a learning rate of said artificial neuron circuit by adjusting at least one resistive element thereof in accordance with the predefined adaptation signal. (Danial, paragraph 0104, “The learning rate is crucial to the adaptation performance: it depends on the circuit parameters, the write voltage, the pulse-time width, the feedback resistor, the present state, and the physical properties of the memristive device.”)
Rancour, Kello and Danial are related to the same field of endeavor (i.e. neural networks). In view of the teachings of Danial, it would have been obvious for a person with ordinary skill in the art to apply the teachings of Danial to Rancour and Kello before the effective filing date of the claimed invention in order to achieve high speed and accuracy. (Danial, paragraph 0052, “The quality of a system is considered ideal when it achieves high speed and accuracy with”)
In regard to claim 19, Rancour teaches a first multiplier circuit configured to generate a first signal based on a multiplication of the adapted temporally integrated signal by a feedback signal of said artificial neuron circuit; (Rancour, paragraph 0035, “Reference source not found. as abstract multiplier and adder symbols. For the perceptron 100, there are ten such training circuits 600 in total, one for each output-layer neuron, for example, one for each of the numerals 0-9. Signals "Weightl", "Weight2", ... "Weightl0" are common to all ten output-layer neurons, whereas each output-layer neuron receives a unique set of"Activation" signals from the hidden (inner) layer, namely the signals generated by that neuron's corresponding input numeral.”)
a weight update circuit configured to generate a new weight signal based on a multiplication of a previous weight signal by a summation of said previous weight signal with said first product signal; and (Rancour, paragraph 0009, “The training circuitry may be configured to train the artificial neural network by adjusting the weight of the at least one artificial neuron. The training circuitry may include a track and hold circuit that provides a value based on a weight to the artificial neural network circuitry, wherein the weight may be generated based on an output-layer of the artificial neural network circuitry.” and paragraph 0025, “Artificial neurons and inputs may have a weight that adjusts as learning proceeds (for example, each input to an artificial neuron may be separately weighted). The weight increases or decreases the strength of the signal at a connection. Artificial neurons may have a threshold such that the signal is only sent if the aggregate signal crosses that threshold.”)
a second multiplier circuit configured to generate a second product signal based on a multiplication of said temporally integrated signal by the new weight signal. (Rancour, paragraph 0040, “Each training circuit 600 has feedback control of one specific weight value. All ten output neurons receive the same ten weights. Each output neuron receives its own unique set of "Activation" signals corresponding to the specific input numeral that the neuron is to "recognize" or "ignore."”)
However, Rancour does not explicitly teach a scaling input circuit configured to receive one or more input signals, adapt at least one of said one or more input signals in accordance with a weight signal, and generate an input current of said artificial neuron circuit based at least on the adapted input signal;
a leaky integrate and fire (LIF) neuron circuit configured to generate spike signals based on the input current from said scaling input circuit; and
an integration circuit configured to generate a temporally integrated signal indicative of temporal integration of at least some of said spike signals; and an analog signal processing circuit comprising:
an input configured to adapt said temporally integrated signal in accordance with a predefined adaptation signal indicative of a learning rate of said artificial neuron circuit;
Kello teaches a scaling input circuit configured to receive one or more input signals, adapt at least one of said one or more input signals in accordance with a weight signal, and generate an input current of said artificial neuron circuit based at least on the adapted input signal; (Kello, paragraph 0164, “The tuning algorithms were designed to scale (renormalize) post-synaptic and pre-synaptic connection weights, respectively. The post-synaptic algorithm scales weights so that a given spike on neuron i produced at time tis expected to be followed at t+ I by exactly one corresponding spike over its post-synaptic neurons.”)
a leaky integrate and fire (LIF) neuron circuit configured to generate spike signals based on the input current from said scaling input circuit; and (Kello, paragraph 0182, “In this example, a self-tuning algorithm is developed for use with leaky integrate-and-fire (LIF) neurons that adjusts postsynaptic weights to a critical branching point between subcritical and supercritical spiking dynamics. The tuning algorithm stabilizes spiking activity in the sense that spikes propagate through the network without multiplying to the point of wildfire activity, and without dying out so quickly that information cannot be transmitted and processed. The critical branching point is also found to maximize memory and representational capacity of the network when used as liquid state machine.”)
an integration circuit configured to generate a temporally integrated signal indicative of temporal integration of at least some of said spike signals; and an analog signal processing circuit comprising: (Kello, paragraph 0182, “In this example, a self-tuning algorithm is developed for use with leaky integrate-and-fire (LIF) neurons that adjusts postsynaptic weights to a critical branching point between subcritical and supercritical spiking dynamics. The tuning algorithm stabilizes spiking activity in the sense that spikes propagate through the network without multiplying to the point of wildfire activity, and without dying out so quickly that information cannot be transmitted and processed. The critical branching point is also found to maximize memory and representational capacity of the network when used as liquid state machine.”)
However, Rancour and Kello do not explicitly teach an input configured to adapt said temporally integrated signal in accordance with a predefined adaptation signal indicative of a learning rate of said artificial neuron circuit;
Danial teaches an input configured to adapt said temporally integrated signal in accordance with a predefined adaptation signal indicative of a learning rate of said artificial neuron circuit; (Danial, paragraph 0104, “The learning rate is crucial to the adaptation performance: it depends on the circuit parameters, the write voltage, the pulse-time width, the feedback resistor, the present state, and the physical properties of the memristive device.”)
Rancour, Kello and Danial are combinable for the same rationale as set forth above with respect to claim 2.
In regard to claim 20, Rancour, Kello and Danial teach the learning core of claim 19.
Kello further teaches wherein the LIF neuron circuit comprises a soma module configured to regulate a leakage current from said scaling input circuit for adjusting a charging current of a soma capacitive element thereof. (Kello, paragraph 0192, “The tuning algorithm adjusts the postsynaptic weights of a given model neuron so that, when it spikes, one and only one spike is expected to follow over the postsynaptic array of neurons. The algorithm weights each descendent spike relative to its number of ancestor spikes n over its presynaptic array on the preceding time step, i.e., 1/n. The algorithm increases weights projecting out from a given postsynaptic neuron by a factor~ when the sum of weighted spikes over its postsynaptic array is greater than one. The algorithm decreases weights by ~ when the sum is less than one (no change is made when equal to one).”)
Rancour, Kello and Danial are combinable for the same rationale as set forth above with respect to claim 2.
In regard to claim 21, Rancour, Kello and Danial teach the learning core of claim 20.
Kello further teaches wherein the LIF neuron circuit comprises a spike generator configured to generate first and second driving currents whenever a voltage over the soma capacitive element is greater than a defined voltage level, said first driving current being used for charging the soma capacitive element, and said second driving current being used for generating the spike signals. (Kello, paragraph 0192, “The tuning algorithm adjusts the postsynaptic weights of a given model neuron so that, when it spikes, one and only one spike is expected to follow over the postsynaptic array of neurons. The algorithm weights each descendent spike relative to its number of ancestor spikes n over its presynaptic array on the preceding time step, i.e., 1/n. The algorithm increases weights projecting out from a given postsynaptic neuron by a factor~ when the sum of weighted spikes over its postsynaptic array is greater than one. The algorithm decreases weights by ~ when the sum is less than one (no change is made when equal to one).”)
Rancour, Kello and Danial are combinable for the same rationale as set forth above with respect to claim 2.
In regard to claim 22, Rancour, Kello and Danial teach the learning core of claim 21.
Kello further teaches comprising a spike shaping module configured to charge a spike shaping capacitive element thereof with the second driving current from the spike generator and regulate according to voltage level of said spike shaping capacitive element a discharge current of the soma capacitive element. (Kello, paragraph 0192, “The tuning algorithm adjusts the postsynaptic weights of a given model neuron so that, when it spikes, one and only one spike is expected to follow over the postsynaptic array of neurons. The algorithm weights each descendent spike relative to its number of ancestor spikes n over its presynaptic array on the preceding time step, i.e., 1/n. The algorithm increases weights projecting out from a given postsynaptic neuron by a factor~ when the sum of weighted spikes over its postsynaptic array is greater than one. The algorithm decreases weights by ~ when the sum is less than one (no change is made when equal to one).”)
Rancour, Kello and Danial are combinable for the same rationale as set forth above with respect to claim 2.
In regard to claim 23, Rancour, Kello and Danial teach the learning core of claim 22.
Kello further teaches wherein the spike generator comprises first and second invertors, said second invertor configured to generate the second driving current, and to discharge the spike shaping capacitive element whenever the voltage over the soma capacitive element is smaller than the defined voltage level, and wherein said learning core comprising an integration module configured to regulate a charging current of an integration capacitive element thereof according to a voltage level over the spike shaping capacitive element, wherein the temporally integrated signal is indicative of the voltage of said spike shaping capacitive element. (Kello, paragraph 0182, “In this example, a self-tuning algorithm is developed for use with leaky integrate-and-fire (LIF) neurons that adjusts postsynaptic weights to a critical branching point between subcritical and supercritical spiking dynamics. The tuning algorithm stabilizes spiking activity in the sense that spikes propagate through the network without multiplying to the point of wildfire activity, and without dying out so quickly that information cannot be transmitted and processed. The critical branching point is also found to maximize memory and representational capacity of the network when used as liquid state machine.”) and paragraph 0192, “The tuning algorithm adjusts the postsynaptic weights of a given model neuron so that, when it spikes, one and only one spike is expected to follow over the postsynaptic array of neurons. The algorithm weights each descendent spike relative to its number of ancestor spikes n over its presynaptic array on the preceding time step, i.e., 1/n. The algorithm increases weights projecting out from a given postsynaptic neuron by a factor~ when the sum of weighted spikes over its postsynaptic array is greater than one. The algorithm decreases weights by ~ when the sum is less than one (no change is made when equal to one).”)
Rancour, Kello and Danial are combinable for the same rationale as set forth above with respect to claim 2.
In regard to claim 25, Rancour, Kello and Danial teach the learning core of claim 19.
Rancour further teaches a summation circuit configured to generated a summation signal based on a summation of the second product signal from the analog signal processing circuits of said two or more of the learning cores, and a subtraction circuit configured generate the feedback signal for said learning core based on a subtraction of a reference signal from said summation signal. (Rancour, paragraph 0050, “As another example, for an XOR gate, the amplitude of the bias element is zero and the first and second phase shifts, for 920 and 922, are O degrees and 180 degrees respectively. Therefore, the summation of the input signals by summer 928 amounts to a subtraction. As a result, no explicit phase-shifting circuitry is required.”)
Rancour, Kello and Danial are combinable for the same rationale as set forth above with respect to claim 2.
In regard to claim 27, Rancour and Kello teach the method of claim 26.
However, Rancour and Kello do not explicitly teach comprising scaling the output signal according to a predefined learning rate of the artificial neuron.
Danial teaches comprising scaling the output signal according to a predefined learning rate of the artificial neuron. (Danial, paragraph 0104, “The learning rate is crucial to the adaptation performance: it depends on the circuit parameters, the write voltage, the pulse-time width, the feedback resistor, the present state, and the physical properties of the memristive device.”)
Rancour, Kello and Danial are combinable for the same rationale as set forth above with respect to claim 2.
In regard to claim 28, Rancour and Kello teach the method of claim 26.
However, Rancour and Kello do not explicitly teach comprising generating the output signal by adapting one or more input signals in accordance with at least one scaling signal, and generating an input current of the artificial neuron based on the adapted one or more input signals.
Danial teaches comprising generating the output signal by adapting one or more input signals in accordance with at least one scaling signal, and generating an input current of the artificial neuron based on the adapted one or more input signals. (Danial, paragraph 0104, “The learning rate is crucial to the adaptation performance: it depends on the circuit parameters, the write voltage, the pulse-time width, the feedback resistor, the present state, and the physical properties of the memristive device.”)
Rancour, Kello and Danial are combinable for the same rationale as set forth above with respect to claim 2.
In regard to claim 29, Rancour, Kello and Danial teach the method of claim 28.
Kello further teaches comprising generating spike signals by the artificial neuron based on the input current. (Kello, paragraph 0203, “However, in the current simulations, the output layer served a different purpose. Output neurons had no post-synaptic connections, which meant that spikes occurring in the output layer "exited" the network. That is, the critical branching algorithm did not count these spikes as ancestors with descendant spikes. Spiking models that are critical branching need a way for spikes to exit the network.”)
Rancour, Kello and Danial are combinable for the same rationale as set forth above with respect to claim 2.
In regard to claim 30, Rancour, Kello and Danial teach the method of claim 29.
Kello further teaches comprising regulating a leakage current for adjusting the input current and charging a soma capacitive element. (Kello, paragraph 0182, “In this example, a self-tuning algorithm is developed for use with leaky integrate-and-fire (LIF) neurons that adjusts postsynaptic weights to a critical branching point between subcritical and supercritical spiking dynamics. The
tuning algorithm stabilizes spiking activity in the sense that spikes propagate through the network without multiplying to the point of wildfire activity, and without dying out so quickly that information cannot be transmitted and processed.”)
Rancour, Kello and Danial are combinable for the same rationale as set forth above with respect to claim 2.
In regard to claim 31, Rancour, Kello and Danial teach the method of claim 30.
Kello further teaches generating first and second driving currents whenever a voltage over the soma capacitive element is greater than a defined voltage level, and charging said soma capacitive element by said first driving current, and generating the spike signals by said second driving current;
charging a spike shaping capacitive element by the second driving current and regulating according to a voltage level of said spike shaping capacitive element a discharge current of the soma capacitive element; (Kello, paragraph 0182, “In this example, a self-tuning algorithm is developed for use with leaky integrate-and-fire (LIF) neurons that adjusts postsynaptic weights to a critical branching point between subcritical and supercritical spiking dynamics. The tuning algorithm stabilizes spiking activity in the sense that spikes propagate through the network without multiplying to the point of wildfire activity, and without dying out so quickly that information cannot be transmitted and processed. The critical branching point is also found to maximize memory and representational capacity of the network when used as liquid state machine.”)
discharging the spike shaping capacitive element whenever the voltage over the soma capacitive element is smaller than the defined voltage level value; (Kello, paragraph 0182, “In this example, a self-tuning algorithm is developed for use with leaky integrate-and-fire (LIF) neurons that adjusts postsynaptic weights to a critical branching point between subcritical and supercritical spiking dynamics. The tuning algorithm stabilizes spiking activity in the sense that spikes propagate through the network without multiplying to the point of wildfire activity, and without dying out so quickly that information cannot be transmitted and processed. The critical branching point is also found to maximize memory and representational capacity of the network when used as liquid state machine.”)
regulating a charging current of an integration capacitive element according to a voltage level over the spike shaping capacitive element and outputting the temporally integrated signal based on a voltage level of said integration capacitive element. (Kello, paragraph 0182, “In this example, a self-tuning algorithm is developed for use with leaky integrate-and-fire (LIF) neurons that adjusts postsynaptic weights to a critical branching point between subcritical and supercritical spiking dynamics. The tuning algorithm stabilizes spiking activity in the sense that spikes propagate through the network without multiplying to the point of wildfire activity, and without dying out so quickly that information cannot be transmitted and processed. The critical branching point is also found to maximize memory and representational capacity of the network when used as liquid state machine.”)
Rancour, Kello and Danial are combinable for the same rationale as set forth above with respect to claim 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SKYLAR K VANWORMER whose telephone number is (703)756-1571. The examiner can normally be reached M-F 6:00am to 3:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Usmaan Saeed can be reached at (571) 272-4046. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/S.K.V./Examiner, Art Unit 2146
/USMAAN SAEED/Supervisory Patent Examiner, Art Unit 2146
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