Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on 08 November 2023. U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 6, 7, and 26 are rejected under 35 U.S.C. 103 as being unpatentable over US20210232486A1 (Barve) in view of US20230305814A1 (Sumeet), US20160070835A1 (Foisy), US20040088691A1 (Hammes), and US20200242291A1 (Yamamoto).
In regards to claim 1 (Barve) shows:
A high-level synthesis device comprising; Barve [0027] discloses: "High-Level Synthesis (HLS) is a design process where algorithmic description of hardware is converted low level RTL code."
a specification description provider to provide specification descriptions including a behavioral description indicating functional logic; Barve [0033] discloses: "the memory 102 may store (or stores) machine programming language (MPL) code written in any of languages (e.g., C, C++, System C, simulator such as MATLAB, Vivado High Level Synthesis (Vivado HLS), and the like)."
a high-level synthesis processor to perform high-level synthesis processing of generating hardware descriptions based on the specification descriptions, the hardware descriptions including a behavioral processing hardware description for an information processing device obtained by hardware implementation of the functional logic indicated by the behavioral description; Barve [0035] discloses: "a synthesizable logic 110 converts the MPL code comprising at least one of the one or more printf statements and the one or more scanf statements to register transfer language (RTL) instructions."
the specification descriptions further include an execution trace specification description for trace processing described to correspond to the behavioral description; Barve [0034] discloses: "the one or more printf and/or scanf statements are specified before or after at least one of (i) one or more functions and (ii) one or more sections having instructions comprised in the MPL code."
in the high-level synthesis processing, an execution trace hardware description describing an execution trace function to perform the trace processing is further generated based on the behavioral description and the execution trace specification description; Barve [0028] discloses: "the printf and/or scanf statement(s) is/are synthesized as a block during run-time which communicate with a host system (or system as described herein) and debug messages are generated which are displayed on a console."
the hardware descriptions include the execution trace hardware description; Barve [0037] discloses: "The printed one or more debug messages are indicative of (i) an execution flow of the RTL instructions at run-time, and (ii) one or more values associated with one or more parameters comprised in the (RTL) instructions."
Barve differs from the claimed invention in that it does not explicitly disclose the specification descriptions further include a high-level synthesis specification description defining high-level synthesis constraints; a control data flow graph (CDFG) creation processor to create a CDFG based on the behavioral description; a CDFG execution trace extension processor to provide an execution trace extension function to the CDFG based on the execution trace specification description to acquire a CDFG with execution trace extension; a scheduling processor to perform scheduling processing based on the high-level synthesis specification description on the CDFG with execution trace extension to acquire a scheduled CDFG; a binding processor to allocate a hardware resource to the scheduled CDFG to acquire a bound CDFG; an execution trace maximum window time calculator to calculate maximum window time based on the bound CDFG; the maximum window time is maximum time to perform the trace processing without affecting behavioral processing performed by the information processing device; the scheduled CDFG is divided into a plurality of control states; a state control machine generator to generate a state control machine indicating transition between the plurality of control states based on the scheduled CDFG; an execution trace mechanism generator to perform execution trace related information generation processing of generating execution trace mechanism circuitry, execution trace mechanism common circuitry, and an execution trace extension state control machine; the execution trace mechanism common circuitry includes a clock counter and recording memory transfer circuitry for an execution trace recording memory; the execution trace mechanism circuitry is a trace basic portion to perform the trace processing; and the execution trace extension state control machine is information obtained by providing an execution trace extension function to the state control machine.
Sumeet teaches a scheduling processor to perform scheduling processing based on the high-level synthesis specification description on the CDFG with execution trace extension to acquire a scheduled CDFG; Sumeet [0027] discloses: "The logic operations are distributed through the clock cycles in scheduling and the number of such operations depends on the clock frequency, optimization directives and FPGA technology library."
Sumeet teaches a binding processor to allocate a hardware resource to the scheduled CDFG to acquire a bound CDFG; Sumeet [0027] discloses: "Binding assigns hardware resources for carrying out the logic operation which are scheduled using a state machine by the control extraction step."
Sumeet teaches the scheduled CDFG is divided into a plurality of control states; Sumeet [0027] discloses: "Binding assigns hardware resources for carrying out the logic operation which are scheduled using a state machine by the control extraction step."
Sumeet teaches a state control machine generator to generate a state control machine indicating transition between the plurality of control states based on the scheduled CDFG; Sumeet [0075] discloses: "Extract the state variable to determine the state of execution at a particular clock cycle. The 'AP_CS_FSM' HDL signal value is used for this."
Sumeet teaches the execution trace extension state control machine is information obtained by providing an execution trace extension function to the state control machine; Sumeet [0060] discloses: "The operation record contains the target signal (in the form of initial name of HDL signal), the operator type, operands, predicate, and line numbers."
Sumeet differs from the claimed invention in that it does not explicitly disclose the specification descriptions further include a high-level synthesis specification description defining high-level synthesis constraints; a control data flow graph (CDFG) creation processor to create a CDFG based on the behavioral description; a CDFG execution trace extension processor to provide an execution trace extension function to the CDFG based on the execution trace specification description to acquire a CDFG with execution trace extension; an execution trace maximum window time calculator to calculate maximum window time based on the bound CDFG; the maximum window time is maximum time to perform the trace processing without affecting behavioral processing performed by the information processing device; an execution trace mechanism generator to perform execution trace related information generation processing of generating execution trace mechanism circuitry, execution trace mechanism common circuitry, and an execution trace extension state control machine; the execution trace mechanism common circuitry includes a clock counter and recording memory transfer circuitry for an execution trace recording memory; and the execution trace mechanism circuitry is a trace basic portion to perform the trace processing.
Foisy teaches the maximum window time is maximum time to perform the trace processing without affecting behavioral processing performed by the information processing device; Foisy [0095] discloses: "measurements showing that inventive tool does not affect synthesizable clock frequency, therefore providing completely non-intrusive instrumentation."
Foisy teaches an execution trace mechanism generator to perform execution trace related information generation processing of generating execution trace mechanism circuitry, execution trace mechanism common circuitry, and an execution trace extension state control machine based on the execution trace specification description, the bound CDFG, the maximum window time, and the state control machine; Foisy [0028] discloses: "The on-chip component includes a recorder, a backing store, and a reader as described below."
Foisy teaches the execution trace mechanism common circuitry includes a clock counter and recording memory transfer circuitry for an execution trace recording memory; Foisy [0029] discloses: "Debug data on each channel is timestamped and queued in an asynchronous FIFO."
Foisy teaches the execution trace mechanism circuitry is a trace basic portion to perform the trace processing; Foisy [0028] discloses: "the instrumentation embedded into the user design in FPGA comprises three components which handle logging of debug data on multiple channels, storage, and readback."
Foisy differs from the claimed invention in that it does not explicitly disclose the specification descriptions further include a high-level synthesis specification description defining high-level synthesis constraints; a control data flow graph (CDFG) creation processor to create a CDFG based on the behavioral description; a CDFG execution trace extension processor to provide an execution trace extension function to the CDFG based on the execution trace specification description to acquire a CDFG with execution trace extension; and an execution trace maximum window time calculator to calculate maximum window time based on the bound CDFG.
Hammes teaches a control data flow graph (CDFG) creation processor to create a CDFG based on the behavioral description; Hammes [0057] discloses: "the CFG to CFG-DFG converter 108 may be a software module including logic instructions for receiving the CFG representation created by HLL converter 106 and converting a CFG representation to a control-data-flow graph representation."
Hammes teaches a CDFG execution trace extension processor to provide an execution trace extension function to the CDFG based on the execution trace specification description to acquire a CDFG with execution trace extension; Hammes [0205] discloses: "For non-loop blocks, LOAD nodes may be created for the various scalar values that are referenced. Then the dataflow graph of the block's computation may be created. Finally, a STORE node may be created for each scalar variable to store its final value."
Hammes teaches an execution trace maximum window time calculator to calculate maximum window time based on the bound CDFG; Hammes [0131] discloses: "The <num> is an integer value specifying the number of clock cycles between the presentation of data to the hardware logic module's inputs and the availability of corresponding results on the outputs."
Hammes differs from the claimed invention in that it does not explicitly disclose the specification descriptions further include a high-level synthesis specification description defining high-level synthesis constraints.
Yamamoto teaches the specification descriptions further include a high-level synthesis specification description defining high-level synthesis constraints; Yamamoto [0056] discloses: "The non-functional requirement 152 is a file that defines a non-functional requirement such as the required circuit latency and memory usage."
It would have been obvious to one of ordinary skill in the art to combine Barve and Sumeet to schedule and bind the graph into a plurality of control states and a state control machine, with a reasonable expectation of success as both references address high-level synthesis of hardware.
It would have been obvious to one of ordinary skill in the art to further combine Barve and Sumeet with Foisy to record the trace data non-intrusively using a clock counter and recording memory without affecting behavioral processing, with a reasonable expectation of success as the references address instrumentation of synthesized hardware.
It would have been obvious to one of ordinary skill in the art to further combine Barve, Sumeet, and Foisy with Hammes to represent the behavioral description as a control data flow graph for systematic insertion of the trace function, with a reasonable expectation of success as the references address high-level synthesis of hardware from source code.
It would have been obvious to one of ordinary skill in the art to further combine Barve, Sumeet, Foisy, and Hammes with Yamamoto to define high-level synthesis constraints that guide generation of an efficient hardware circuit, with a reasonable expectation of success as the references address high-level synthesis of hardware from a behavioral description.
In regards to claim 5 (Barve modified by Sumeet and Foisy) does not show: a hardware description generator to generate the hardware descriptions based on the bound CDFG, the execution trace mechanism circuitry, the execution trace mechanism common circuitry, and the execution trace extension state control machine.
Hammes teaches a hardware description generator to generate the hardware descriptions based on the bound CDFG, the execution trace mechanism circuitry, the execution trace mechanism common circuitry, and the execution trace extension state control machine; Hammes [0063] discloses: "CFG-DFG to HDL converter 112 may be a software module that includes logic instructions for converting the CFG-DFG into a hardware definition of the physical logic that will be instantiated in the reconfigurable processor(s)".
It would have been obvious to one of ordinary skill in the art to combine Barve and Sumeet to schedule and bind the graph into a plurality of control states and a state control machine, with a reasonable expectation of success as both references address high-level synthesis of hardware.
It would have been obvious to one of ordinary skill in the art to further combine Barve and Sumeet with Foisy to record the trace data non-intrusively using a clock counter and recording memory without affecting behavioral processing, with a reasonable expectation of success as the references address instrumentation of synthesized hardware.
It would have been obvious to one of ordinary skill in the art to further combine Barve, Sumeet, and Foisy with Hammes to represent the behavioral description as a control data flow graph for systematic insertion of the trace function, with a reasonable expectation of success as the references address high-level synthesis of hardware from source code.
In regards to claim 6 (Barve) shows the high-level synthesis device according to claim 5 further comprising:
a hardware description storage to store the hardware descriptions; Barve [0032] discloses: "a database 108 is comprised in the memory 102, wherein the database 108 comprises information, for example, debug messages, error(s) identified during execution of machine programming language (MPL) code in run-time, execution flow of register transfer language/register transfer level (RTL) instructions and the like."
Barve differs from the claimed invention in that it does not explicitly disclose the execution trace hardware description includes an execution trace mechanism circuitry description and an execution trace mechanism common circuitry description corresponding respectively to the execution trace mechanism circuitry and the execution trace mechanism common circuitry;
Foisy teaches the execution trace hardware description includes an execution trace mechanism circuitry description and an execution trace mechanism common circuitry description corresponding respectively to the execution trace mechanism circuitry and the execution trace mechanism common circuitry; Foisy [0028] discloses: "The on-chip component includes a recorder, a backing store, and a reader as described below."
It would have been obvious to one of ordinary skill in the art to combine Barve and Sumeet to schedule and bind the graph into a plurality of control states and a state control machine, with a reasonable expectation of success as both references address high-level synthesis of hardware.
It would have been obvious to one of ordinary skill in the art to further combine Barve and Sumeet with Foisy to record the trace data non-intrusively using a clock counter and recording memory without affecting behavioral processing, with a reasonable expectation of success as the references address instrumentation of synthesized hardware.
In regards to claim 7 (Barve) shows the high-level synthesis device according to claim 6, wherein the behavioral processing hardware description includes:
an execution trace extension hardware description obtained by associating the functional logic based on the behavioral description with a trace function; Barve [0037] discloses: "The printed one or more debug messages are indicative of (i) an execution flow of the RTL instructions at run-time, and (ii) one or more values associated with one or more parameters comprised in the (RTL) instructions."
Barve differs from the claimed invention in that it does not explicitly disclose an execution trace extension state control machine description corresponding to the execution trace extension state control machine;
Sumeet teaches an execution trace extension state control machine description corresponding to the execution trace extension state control machine; Sumeet [0075] discloses: "Extract the state variable to determine the state of execution at a particular clock cycle. The 'AP_CS_FSM' HDL signal value is used for this."
It would have been obvious to one of ordinary skill in the art to combine Barve and Sumeet to associate the functional logic with the trace function and represent it in the state control machine description, with a reasonable expectation of success as the references address high-level synthesis and instrumentation of hardware.
In regards to claim 26 (Barve) shows:
A high-level synthesis method comprising; Barve [0027] discloses: "High-Level Synthesis (HLS) is a design process where algorithmic description of hardware is converted low level RTL code."
providing specification descriptions including a behavioral description indicating functional logic; Barve [0033] discloses: "the memory 102 may store (or stores) machine programming language (MPL) code written in any of languages (e.g., C, C++, System C, simulator such as MATLAB, Vivado High Level Synthesis (Vivado HLS), and the like)."
performing high-level synthesis processing to acquire hardware descriptions based on the specification descriptions, the hardware descriptions including a behavioral processing hardware description for an information processing device obtained by hardware implementation of the functional logic described by the behavioral description; Barve [0035] discloses: "a synthesizable logic 110 converts the MPL code comprising at least one of the one or more printf statements and the one or more scanf statements to register transfer language (RTL) instructions."
the specification descriptions further include an execution trace specification description for trace processing described to correspond to the behavioral description; Barve [0034] discloses: "the one or more printf and/or scanf statements are specified before or after at least one of (i) one or more functions and (ii) one or more sections having instructions comprised in the MPL code."
in the high-level synthesis processing, an execution trace hardware description describing an execution trace function to perform the trace processing is further generated based on the behavioral description and the execution trace specification description; Barve [0028] discloses: "the printf and/or scanf statement(s) is/are synthesized as a block during run-time which communicate with a host system (or system as described herein) and debug messages are generated which are displayed on a console."
the hardware descriptions include the execution trace hardware description; Barve [0037] discloses: "The printed one or more debug messages are indicative of (i) an execution flow of the RTL instructions at run-time, and (ii) one or more values associated with one or more parameters comprised in the (RTL) instructions."
Barve differs from the claimed invention in that it does not explicitly disclose the specification descriptions further include a high-level synthesis specification description defining high-level synthesis constraints; creating a control data flow graph (CDFG) based on the behavioral description; providing an execution trace extension function to the CDFG based on the execution trace specification description to acquire a CDFG with execution trace extension; performing scheduling processing based on the high-level synthesis specification description on the CDFG with execution trace extension to acquire a scheduled CDFG; allocating a hardware resource to the scheduled CDFG to acquire a bound CDFG; calculating maximum window time based on the bound CDFG; the maximum window time is maximum time to perform the trace processing without affecting behavioral processing performed by the information processing device; the scheduled CDFG is divided into a plurality of control states; generating a state control machine indicating transition between the plurality of control states based on the scheduled CDFG; performing execution trace related information generation processing of generating execution trace mechanism circuitry, execution trace mechanism common circuitry, and an execution trace extension state control machine; the execution trace mechanism common circuitry includes a clock counter and recording memory transfer circuitry for an execution trace recording memory; the execution trace mechanism circuitry is a trace basic portion to perform the trace processing; and the execution trace extension state control machine is information obtained by providing an execution trace extension function to the state control machine.
Sumeet teaches performing scheduling processing based on the high-level synthesis specification description on the CDFG with execution trace extension to acquire a scheduled CDFG; Sumeet [0027] discloses: "The logic operations are distributed through the clock cycles in scheduling and the number of such operations depends on the clock frequency, optimization directives and FPGA technology library."
Sumeet teaches allocating a hardware resource to the scheduled CDFG to acquire a bound CDFG; Sumeet [0027] discloses: "Binding assigns hardware resources for carrying out the logic operation which are scheduled using a state machine by the control extraction step."
Sumeet teaches the scheduled CDFG is divided into a plurality of control states; Sumeet [0027] discloses: "Binding assigns hardware resources for carrying out the logic operation which are scheduled using a state machine by the control extraction step."
Sumeet teaches generating a state control machine indicating transition between the plurality of control states based on the scheduled CDFG; Sumeet [0075] discloses: "Extract the state variable to determine the state of execution at a particular clock cycle. The 'AP_CS_FSM' HDL signal value is used for this."
Sumeet teaches the execution trace extension state control machine is information obtained by providing an execution trace extension function to the state control machine; Sumeet [0060] discloses: "The operation record contains the target signal (in the form of initial name of HDL signal), the operator type, operands, predicate, and line numbers."
Sumeet differs from the claimed invention in that it does not explicitly disclose the specification descriptions further include a high-level synthesis specification description defining high-level synthesis constraints; creating a control data flow graph (CDFG) based on the behavioral description; providing an execution trace extension function to the CDFG based on the execution trace specification description to acquire a CDFG with execution trace extension; calculating maximum window time based on the bound CDFG; the maximum window time is maximum time to perform the trace processing without affecting behavioral processing performed by the information processing device; performing execution trace related information generation processing of generating execution trace mechanism circuitry, execution trace mechanism common circuitry, and an execution trace extension state control machine; the execution trace mechanism common circuitry includes a clock counter and recording memory transfer circuitry for an execution trace recording memory; and the execution trace mechanism circuitry is a trace basic portion to perform the trace processing.
Foisy teaches the maximum window time is maximum time to perform the trace processing without affecting behavioral processing performed by the information processing device; Foisy [0095] discloses: "measurements showing that inventive tool does not affect synthesizable clock frequency, therefore providing completely non-intrusive instrumentation."
Foisy teaches performing execution trace related information generation processing of generating execution trace mechanism circuitry, execution trace mechanism common circuitry, and an execution trace extension state control machine based on the execution trace specification description, the bound CDFG, the maximum window time, and the state control machine; Foisy [0028] discloses: "The on-chip component includes a recorder, a backing store, and a reader as described below."
Foisy teaches the execution trace mechanism common circuitry includes a clock counter and recording memory transfer circuitry for an execution trace recording memory; Foisy [0029] discloses: "Debug data on each channel is timestamped and queued in an asynchronous FIFO."
Foisy teaches the execution trace mechanism circuitry is a trace basic portion to perform the trace processing; Foisy [0028] discloses: "the instrumentation embedded into the user design in FPGA comprises three components which handle logging of debug data on multiple channels, storage, and readback."
Foisy differs from the claimed invention in that it does not explicitly disclose the specification descriptions further include a high-level synthesis specification description defining high-level synthesis constraints; creating a control data flow graph (CDFG) based on the behavioral description; providing an execution trace extension function to the CDFG based on the execution trace specification description to acquire a CDFG with execution trace extension; and calculating maximum window time based on the bound CDFG.
Hammes teaches creating a control data flow graph (CDFG) based on the behavioral description; Hammes [0057] discloses: "the CFG to CFG-DFG converter 108 may be a software module including logic instructions for receiving the CFG representation created by HLL converter 106 and converting a CFG representation to a control-data-flow graph representation."
Hammes teaches providing an execution trace extension function to the CDFG based on the execution trace specification description to acquire a CDFG with execution trace extension; Hammes [0205] discloses: "For non-loop blocks, LOAD nodes may be created for the various scalar values that are referenced. Then the dataflow graph of the block's computation may be created. Finally, a STORE node may be created for each scalar variable to store its final value."
Hammes teaches calculating maximum window time based on the bound CDFG; Hammes [0131] discloses: "The <num> is an integer value specifying the number of clock cycles between the presentation of data to the hardware logic module's inputs and the availability of corresponding results on the outputs."
Hammes differs from the claimed invention in that it does not explicitly disclose the specification descriptions further include a high-level synthesis specification description defining high-level synthesis constraints.
Yamamoto teaches the specification descriptions further include a high-level synthesis specification description defining high-level synthesis constraints; Yamamoto [0056] discloses: "The non-functional requirement 152 is a file that defines a non-functional requirement such as the required circuit latency and memory usage."
It would have been obvious to one of ordinary skill in the art to combine Barve and Sumeet to schedule and bind the graph into a plurality of control states and a state control machine, with a reasonable expectation of success as both references address high-level synthesis of hardware.
It would have been obvious to one of ordinary skill in the art to further combine Barve and Sumeet with Foisy to record the trace data non-intrusively using a clock counter and recording memory without affecting behavioral processing, with a reasonable expectation of success as the references address instrumentation of synthesized hardware.
It would have been obvious to one of ordinary skill in the art to further combine Barve, Sumeet, and Foisy with Hammes to represent the behavioral description as a control data flow graph for systematic insertion of the trace function, with a reasonable expectation of success as the references address high-level synthesis of hardware from source code.
It would have been obvious to one of ordinary skill in the art to further combine Barve, Sumeet, Foisy, and Hammes with Yamamoto to define high-level synthesis constraints that guide generation of an efficient hardware circuit, with a reasonable expectation of success as the references address high-level synthesis of hardware from a behavioral description.
Claims 8, 9, and 10 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over US20210232486A1 (Barve) in view of US20230305814A1 (Sumeet), US20160070835A1 (Foisy), US20040088691A1 (Hammes), US20200242291A1 (Yamamoto), and US20140237454A1 (Delporte).
In regards to claim 8 (Barve modified by Sumeet) does not show: the behavioral description is described to correspond to a line number, and the execution trace specification description includes trace position identification information identifying a trace position by the line number defined as a trace target line number, trace processing information, recording scheme information, and execution trace-time processing control information indicating whether to stop processing when the trace processing is performed, provided to correspond to the trace target line number.
Foisy teaches recording scheme information indicating a method of controlling the processing of recording the trace information; Foisy [0033] discloses: "the inventive tool can be configured to use different types of backing stores, based on on-chip and/or off-chip memories."
Foisy differs from the claimed invention in that it does not explicitly disclose the behavioral description is described to correspond to a line number; trace position identification information identifying a trace position in the behavioral description by the line number, the line number identified by the trace position identification information being defined as a trace target line number; trace processing information indicating content of processing of recording trace information acquired when the trace processing is performed; and execution trace-time processing control information indicating whether to stop processing performed by the information processing device when the trace processing is performed, the trace processing information, the recording scheme information, and the execution trace-time processing control information being provided to correspond to the trace target line number.
Hammes teaches the behavioral description is described to correspond to a line number; Hammes [0110] discloses: "This entry provides the relative block number, the source line number that this basic block represents, the label defined by this block (if one exists) as it is represented in the associated symbol table."
Hammes differs from the claimed invention in that it does not explicitly disclose trace position identification information identifying a trace position in the behavioral description by the line number, the line number identified by the trace position identification information being defined as a trace target line number; trace processing information indicating content of processing of recording trace information acquired when the trace processing is performed; and execution trace-time processing control information indicating whether to stop processing performed by the information processing device when the trace processing is performed, the trace processing information, the recording scheme information, and the execution trace-time processing control information being provided to correspond to the trace target line number.
Delporte teaches trace position identification information identifying a trace position in the behavioral description by the line number, the line number identified by the trace position identification information being defined as a trace target line number; Delporte [0061] discloses: "When a failure occurs, a stack trace is produced that indicates the type of error and a list of the method invocations that led to the error. In some embodiments, this list of methods is used as a trace specification in accordance with the following principles".
Delporte teaches trace processing information indicating content of processing of recording trace information acquired when the trace processing is performed; Delporte [0064] discloses: "The state information that can be captured for a given method and that would typically be relevant usually consists of: (i) the arguments to the methods; and/or (ii) its arguments and object instance members (for non-static methods)."
Delporte teaches execution trace-time processing control information indicating whether to stop processing performed by the information processing device when the trace processing is performed, the trace processing information, the recording scheme information, and the execution trace-time processing control information being provided to correspond to the trace target line number; Delporte [0068] discloses: "The top method of the stack trace, or the top method of the most nested cause when such causes exist, are to be instrumented to: (i) catch the exception that was initially found in the log; (ii) dump the state information collected up to this point of the invocation; and (iii) to re-throw the same exception so that the system continues to behave identically, albeit with more precise traces in the log."
It would have been obvious to one of ordinary skill in the art to combine Barve and Sumeet to schedule and bind the graph into a plurality of control states and a state control machine, with a reasonable expectation of success as both references address high-level synthesis of hardware.
It would have been obvious to one of ordinary skill in the art to further combine Barve and Sumeet with Foisy to record the trace data non-intrusively using a clock counter and recording memory without affecting behavioral processing, with a reasonable expectation of success as the references address instrumentation of synthesized hardware.
It would have been obvious to one of ordinary skill in the art to further combine Barve, Sumeet, and Foisy with Hammes to represent the behavioral description as a control data flow graph for systematic insertion of the trace function, with a reasonable expectation of success as the references address high-level synthesis of hardware from source code.
It would have been obvious to one of ordinary skill in the art to combine Barve, Sumeet, Foisy, Hammes, and Delporte to specify, by line number, the positions and content of the trace and whether to stop processing, with a reasonable expectation of success as the references address trace and debug instrumentation of synthesized hardware.
In regards to claim 9 (Barve modified by Sumeet) does not show: the execution trace specification description further includes recorded variable information, clock counter specifying information indicating whether to record a clock count value, and high-level synthesis control information indicating content of processing in a case where trace time exceeds the maximum window time, provided to correspond to the trace target line number.
Foisy teaches clock counter specifying information indicating whether to record a clock count value as the trace information; Foisy [0029] discloses: "Debug data on each channel is timestamped and queued in an asynchronous FIFO."
Foisy teaches high-level synthesis control information indicating content of processing performed in a case where trace time to perform the trace processing exceeds the maximum window time, and the recorded variable information, the clock counter specifying information, and the high-level synthesis control information are provided to correspond to the trace target line number; Foisy [0032] discloses: "The recorder generates an Error signal whenever one of the following conditions occurs: 1) data on one of the channels is dropped; 2) the backing store becomes full."
Foisy differs from the claimed invention in that it does not explicitly disclose recorded variable information indicating a variable recorded as the trace information.
Delporte teaches recorded variable information indicating a variable recorded as the trace information; Delporte [0064] discloses: "The state information that can be captured for a given method and that would typically be relevant usually consists of: (i) the arguments to the methods; and/or (ii) its arguments and object instance members (for non-static methods)."
It would have been obvious to one of ordinary skill in the art to further combine Barve and Sumeet with Foisy to record the trace data non-intrusively using a clock counter and recording memory without affecting behavioral processing, with a reasonable expectation of success as the references address instrumentation of synthesized hardware.
It would have been obvious to one of ordinary skill in the art to combine Barve, Sumeet, Foisy, Hammes, and Delporte to specify the recorded variable, the clock count, and the control taken when the trace time exceeds the maximum window time, with a reasonable expectation of success as the references address trace instrumentation of synthesized hardware.
In regards to claim 10 (Barve modified by Sumeet) does not show: the recording scheme information includes a memory entry, a size entry, a recording frequency entry, a full-time notification entry, a full-time operation entry, and a data storage entry.
Foisy teaches the recording scheme information in the execution trace specification description includes a memory entry indicating types and the number of execution trace recording memories, a size entry indicating a size of the execution trace recording memory, a recording frequency entry, a full-time notification entry indicating whether to provide notification when the memory is full, a full-time operation entry indicating trace control content when the memory is full, and a data storage entry indicating a data storage destination; Foisy [0032] discloses: "The recorder generates an Error signal whenever one of the following conditions occurs: 1) data on one of the channels is dropped; 2) the backing store becomes full."
It would have been obvious to one of ordinary skill in the art to combine Barve and Sumeet to schedule and bind the graph into a plurality of control states and a state control machine, with a reasonable expectation of success as both references address high-level synthesis of hardware.
It would have been obvious to one of ordinary skill in the art to further combine Barve and Sumeet with Foisy to record the trace data non-intrusively using a clock counter and recording memory without affecting behavioral processing, with a reasonable expectation of success as the references address instrumentation of synthesized hardware.
In regards to claim 11 (Barve modified by Sumeet and Foisy) does not show: the execution trace specification description further includes pragma description information including a pragma description indicating content of the trace processing, provided to correspond to the trace target line number.
Hammes teaches pragma description information including a pragma description indicating content of the trace processing, the pragma description information being provided to correspond to the trace target line number; Hammes [0075] discloses: "the partitioner program may receive instructions from a user inserted partitioning syntax, for example a C pragma or a compiler directive, that guides how the CFG-DFG code is partitioned into reconfigurable hardware and instruction processor portions."
It would have been obvious to one of ordinary skill in the art to further combine Barve, Sumeet, and Foisy with Hammes to represent the behavioral description as a control data flow graph for systematic insertion of the trace function, with a reasonable expectation of success as the references address high-level synthesis of hardware from source code.
In regards to claim 12 (Barve modified by Sumeet and Foisy) does not show: the behavioral description has pragma description information in a line corresponding to the trace target line number, the pragma description information including a pragma description indicating content of the trace processing.
Hammes teaches the behavioral description has pragma description information in a line corresponding to the trace target line number, and the pragma description information includes a pragma description indicating content of the trace processing; Hammes [0092] discloses: "in the Fortran language the syntax '!dir$' may be used, and in C the syntax '#pragma' may be used."
It would have been obvious to one of ordinary skill in the art to further combine Barve, Sumeet, and Foisy with Hammes to represent the behavioral description as a control data flow graph for systematic insertion of the trace function, with a reasonable expectation of success as the references address high-level synthesis of hardware from source code.
In regards to claim 13 (Barve modified by Sumeet and Foisy) does not show: CDFG execution trace extension processing performed to correspond to the trace target line number and including the steps of (a) extracting a line number-corresponding CDFG portion, (b) identifying the recorded variable, and (c) identifying an edge where execution processing to the trace target line number is confirmed.
Hammes teaches extracting, from the CDFG, a portion corresponding to the trace target line number as a line number-corresponding CDFG portion; identifying, from the line number-corresponding CDFG portion, the recorded variable indicated by the recorded variable information; and identifying an edge where execution processing to the trace target line number is confirmed in the behavioral description; Hammes [0254] discloses: "An INITIATE node may be created as the head of the DFG, and a layer of LD_SCALAR nodes may be created to bring in the initial values of the scalars."
It would have been obvious to one of ordinary skill in the art to further combine Barve, Sumeet, and Foisy with Hammes to represent the behavioral description as a control data flow graph for systematic insertion of the trace function, with a reasonable expectation of success as the references address high-level synthesis of hardware from source code.
In regards to claim 14 (Barve modified by Sumeet and Foisy) does not show: maximum window time calculation processing including the steps of (a) identifying a recorded variable storage from the bound CDFG and (b) calculating an update cycle of an update of stored content in the recorded variable storage as the maximum window time.
Hammes teaches identifying, from the bound CDFG, a recorded variable storage corresponding to the recorded variable, and calculating an update cycle of an update of stored content in the recorded variable storage as the maximum window time; Hammes [0298] discloses: "The CIRCULATE node (in 32- or 64-bit form) exists to hold the current value of a scalar variable, and may be connected to the LOOP_DRIVER node's output."
It would have been obvious to one of ordinary skill in the art to further combine Barve, Sumeet, and Foisy with Hammes to represent the behavioral description as a control data flow graph for systematic insertion of the trace function, with a reasonable expectation of success as the references address high-level synthesis of hardware from source code.
In regards to claim 15 (Barve modified by Sumeet) does not show: the execution trace related information generation processing including generation basic processing and generation exception processing performed when the processing cycle exceeds the maximum window time, the generation exception processing including displaying a log and performing one of error stop processing and rescheduling processing.
Foisy teaches generation basic processing that generates the execution trace mechanism common circuitry and the execution trace mechanism circuitry and calculates a processing cycle of the generated execution trace mechanism circuitry; Foisy [0031] discloses: "The recorder 101 is instrumented with a number of statistic counters per debug channel which keep track of events such as total number of transactions, number of dropped transactions, time of first drop, etc."
Foisy teaches generation exception processing performed in a case where the processing cycle exceeds the maximum window time, including displaying a log including the trace target line number, the maximum window time, and the processing cycle; Foisy [0032] discloses: "The recorder generates an Error signal whenever one of the following conditions occurs: 1) data on one of the channels is dropped; 2) the backing store becomes full."
Foisy differs from the claimed invention in that it does not explicitly disclose performing one of error stop processing and rescheduling processing, the rescheduling processing including causing the scheduling processing to generate the scheduled CDFG again.
Hammes teaches performing one of error stop processing and rescheduling processing, the rescheduling processing including causing the scheduling processing to generate the scheduled CDFG again; Hammes [0313] discloses: "Many partitioning algorithms can be devised, and alternative algorithms may be invoked and evaluated in the decision process."
It would have been obvious to one of ordinary skill in the art to further combine Barve and Sumeet with Foisy to record the trace data non-intrusively using a clock counter and recording memory without affecting behavioral processing, with a reasonable expectation of success as the references address instrumentation of synthesized hardware.
It would have been obvious to one of ordinary skill in the art to further combine Barve, Sumeet, and Foisy with Hammes to represent the behavioral description as a control data flow graph for systematic insertion of the trace function, with a reasonable expectation of success as the references address high-level synthesis of hardware from source code.
In regards to claim 16 (Barve modified by Sumeet) does not show: the execution trace mechanism circuitry includes a validity determination circuitry, a target recorded variable acquisition circuitry, a clock counter acquisition circuitry, a recorded entry creation circuitry, the execution trace recording memory, a recording frequency determination circuitry, a recording memory full state register, a recording determination circuitry, and a notification mechanism circuitry.
Foisy teaches an execution trace validity determination circuitry, a target recorded variable acquisition circuitry, a clock counter acquisition circuitry, a recorded entry creation circuitry, the execution trace recording memory, a recording frequency determination circuitry, a recording memory full state register, a recording determination circuitry, and a notification mechanism circuitry to output a memory full signal and a recording completion signal; Foisy [0031] discloses: "The recorder 101 is instrumented with a number of statistic counters per debug channel which keep track of events such as total number of transactions, number of dropped transactions, time of first drop, etc."
It would have been obvious to one of ordinary skill in the art to further combine Barve and Sumeet with Foisy to record the trace data non-intrusively using a clock counter and recording memory without affecting behavioral processing, with a reasonable expectation of success as the references address instrumentation of synthesized hardware.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over US20210232486A1 (Barve) in view of US20160070835A1 (Foisy) and US20140237454A1 (Delporte).
In regards to claim 25 (Barve) shows:
A high-level synthesis device comprising; Barve [0027] discloses: "High-Level Synthesis (HLS) is a design process where algorithmic description of hardware is converted low level RTL code."
a specification description provider to provide specification descriptions including a behavioral description indicating functional logic; Barve [0033] discloses: "the memory 102 may store (or stores) machine programming language (MPL) code written in any of languages (e.g., C, C++, System C, simulator such as MATLAB, Vivado High Level Synthesis (Vivado HLS), and the like)."
a high-level synthesis processor to perform high-level synthesis processing of generating hardware descriptions based on the specification descriptions, the hardware descriptions including a behavioral processing hardware description for an information processing device obtained by hardware implementation of the functional logic indicated by the behavioral description; Barve [0035] discloses: "a synthesizable logic 110 converts the MPL code comprising at least one of the one or more printf statements and the one or more scanf statements to register transfer language (RTL) instructions."
the specification descriptions further include an execution trace specification description for trace processing described to correspond to the behavioral description; Barve [0034] discloses: "the one or more printf and/or scanf statements are specified before or after at least one of (i) one or more functions and (ii) one or more sections having instructions comprised in the MPL code."
in the high-level synthesis processing, an execution trace hardware description describing an execution trace function to perform the trace processing is further generated based on the behavioral description and the execution trace specification description; Barve [0028] discloses: "the printf and/or scanf statement(s) is/are synthesized as a block during run-time which communicate with a host system (or system as described herein) and debug messages are generated which are displayed on a console."
the hardware descriptions include the execution trace hardware description; Barve [0037] discloses: "The printed one or more debug messages are indicative of (i) an execution flow of the RTL instructions at run-time, and (ii) one or more values associated with one or more parameters comprised in the (RTL) instructions."
Barve differs from the claimed invention in that it does not explicitly disclose trace position identification information identifying a trace position in the behavioral description; trace processing information indicating content of processing of recording trace information acquired when the trace processing is performed; recording scheme information indicating a method of controlling the processing of recording the trace information; and execution trace-time processing control information indicating whether to stop processing performed by the information processing device when the trace processing is performed, provided to correspond to the trace position identification information.
Foisy teaches recording scheme information indicating a method of controlling the processing of recording the trace information; Foisy [0033] discloses: "the inventive tool can be configured to use different types of backing stores, based on on-chip and/or off-chip memories."
Foisy differs from the claimed invention in that it does not explicitly disclose trace position identification information identifying a trace position in the behavioral description; trace processing information indicating content of processing of recording trace information acquired when the trace processing is performed; and execution trace-time processing control information indicating whether to stop processing performed by the information processing device when the trace processing is performed, provided to correspond to the trace position identification information.
Delporte teaches trace position identification information identifying a trace position in the behavioral description; Delporte [0061] discloses: "When a failure occurs, a stack trace is produced that indicates the type of error and a list of the method invocations that led to the error. In some embodiments, this list of methods is used as a trace specification in accordance with the following principles".
Delporte teaches trace processing information indicating content of processing of recording trace information acquired when the trace processing is performed; Delporte [0064] discloses: "The state information that can be captured for a given method and that would typically be relevant usually consists of: (i) the arguments to the methods; and/or (ii) its arguments and object instance members (for non-static methods)."
Delporte teaches execution trace-time processing control information indicating whether to stop processing performed by the information processing device when the trace processing is performed, provided to correspond to the trace position identification information; Delporte [0068] discloses: "the top method of the most nested cause when such causes exist, are to be instrumented to: (i) catch the exception that was initially found in the log; (ii) dump the state information collected up to this point of the invocation; and (iii) to re-throw the same exception so that the system continues to behave identically".
It would have been obvious to one of ordinary skill in the art to combine Barve and Foisy to control the recording of the trace information, with a reasonable expectation of success as both references address trace instrumentation of synthesized hardware.
It would have been obvious to one of ordinary skill in the art to further combine Barve and Foisy with Delporte to specify the positions and content of the trace, with a reasonable expectation of success as the references address trace and debug instrumentation of synthesized hardware.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over US20210232486A1 (Barve) in view of US20230305814A1 (Sumeet) and US20160070835A1 (Foisy).
In regards to claim 27 (Barve) shows an information processing device implemented by the hardware descriptions generated by the high-level synthesis device according to claim 16, the information processing device comprising:
a behavioral processor hardware (HW) circuit corresponding to the behavioral processing hardware description; Barve [0043] discloses: "The device may also include means which could be e.g. hardware means like e.g. an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a combination of hardware and software means".
Barve differs from the claimed invention in that it does not explicitly disclose an execution trace extension state control machine HW circuit corresponding to the behavioral processing hardware description; and an execution trace mechanism circuitry HW circuit corresponding to the execution trace mechanism circuitry description and an execution trace mechanism common circuitry HW circuit corresponding to the execution trace mechanism common circuitry description;
Sumeet teaches an execution trace extension state control machine HW circuit corresponding to the behavioral processing hardware description; Sumeet [0075] discloses: "Extract the state variable to determine the state of execution at a particular clock cycle. The 'AP_CS_FSM' HDL signal value is used for this."
Sumeet differs from the claimed invention in that it does not explicitly disclose an execution trace mechanism circuitry HW circuit corresponding to the execution trace mechanism circuitry description and an execution trace mechanism common circuitry HW circuit corresponding to the execution trace mechanism common circuitry description;
Foisy teaches an execution trace mechanism circuitry HW circuit corresponding to the execution trace mechanism circuitry description and an execution trace mechanism common circuitry HW circuit corresponding to the execution trace mechanism common circuitry description; Foisy [0068] discloses: "FPGA 901 includes core 903, core 905, PCIe controller 907, 10G MAC+network stack 909, backing store 911 (on FPGA 901) and the inventive tool 913."
It would have been obvious to one of ordinary skill in the art to combine Barve and Sumeet to schedule and bind the graph into a plurality of control states and a state control machine, with a reasonable expectation of success as both references address high-level synthesis of hardware.
It would have been obvious to one of ordinary skill in the art to combine Barve, Sumeet, and Foisy to implement the behavioral, trace-extension state machine, trace mechanism, and common circuitry as hardware circuits in the FPGA, with a reasonable expectation of success as the references address hardware implementation of synthesized designs.
Conclusion
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/ANWER AHMED ALAWDI/Examiner, Art Unit 2851 /JACK CHIANG/ Supervisory Patent Examiner, Art Unit 2851
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