Prosecution Insights
Last updated: April 19, 2026
Application No. 18/290,144

ZERO VOLTAGE SWITCHING IN A BUCK CONVERTER

Non-Final OA §102§103
Filed
Nov 09, 2023
Examiner
ROSARIO BENITEZ, GUSTAVO A
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Power Integrations Inc.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
597 granted / 733 resolved
+13.4% vs TC avg
Strong +25% interview lift
Without
With
+25.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
39 currently pending
Career history
772
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
49.3%
+9.3% vs TC avg
§102
28.1%
-11.9% vs TC avg
§112
21.0%
-19.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 733 resolved cases

Office Action

§102 §103
DETAILED ACTION This office action is in response to the application filed on 11/09/2023. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 11/09/2023, 09/19/2024 and 09/20/2024 has been considered by the examiner. Specification The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-8, 10-15 and 17-22 is/are rejected under 35 U.S.C. 102(a)(2) as being unpatentable by Cohen US 2021/0013807. Regarding Claim 1, Cohen teaches (Figures 4-6 and 10) A BUCK converter (Fig. 10) comprising: a high side switch (1004) electrically coupled to an inductor (1010) and configured to energize the inductor during a first subinterval of a switching cycle (on state of 1004); a freewheeling diode (1006) electrically coupled to de-energize the inductor during a second subinterval of the switching cycle (off state of 1004); and a current reversing path (with 1020) electrically coupled in parallel with the freewheeling diode and configured to reverse energize the inductor during a third subinterval of the switching cycle (when 1020 is on). (For Example: Par. 71-80) Regarding Claim 2, Cohen teaches (Figures 4-6 and 10) wherein the BUCK converter is a high voltage BUCK converter (par. 25). Regarding Claim 3, Cohen teaches (Figures 4-6 and 10)wherein the high side switch comprises a field effect transistor (par. 64). Regarding Claim 4, Cohen teaches (Figures 4-6 and 10)wherein the FET is an N-channel FET (par. 64). Regarding Claim 5, Cohen teaches (Figures 4-6 and 10) wherein the FET comprises a body diode (Fig. 10). Regarding Claims 6 and 19, Cohen teaches (Figures 4-6 and 10) wherein the freewheeling diode (1006) is further coupled to de-energize the inductor such that the BUCK converter operates in a discontinuous conduction mode (DCM, par. 19) during the switching cycle. Regarding Claims 7 and 20, Cohen teaches (Figures 4-6 and 10) wherein the freewheeling diode (1006) is further coupled to de-energize the inductor such that the BUCK converter operates in a boundary conduction mode during the switching cycle (TM, par. 19 and 21). Regarding Claim 8, Cohen teaches (Figures 4-6 and 10) wherein the current reversing path (with 1020) is configured to sink a reverse current during the switching cycle (when 1020 is turn on). (For Example: Par. 71-80) Regarding Claim 10-14, Cohen teaches (Figures 4-6 and 10)wherein the current reversing path comprises a bipolar junction transistor (par, 64); wherein the current reversing path comprises a gallium nitride (GaN) cascode switch; wherein the current reversing path comprises a field effect transistor (FET); wherein the FET is a GaN FET; wherein the FET is an N-channel FET (NFET). (See par. 64 for the different options that the switch 1004 can be.) Regarding Claim 15, Cohen teaches (Figures 4-6 and 10) wherein the NFET comprises a body diode (Fig. 10). Regarding Claim 17, Cohen teaches (Figures 4-6 and 10) a method of controlling a BUCK converter (1000) during a switching cycle, the method comprising: energizing an inductor (1010) during a first subinterval by using a high side switch (1004, on state); de-energizing the inductor during a second subinterval by using a freewheeling diode (1006, conducting); and reverse energizing the inductor during a third subinterval (1020 on state) by using a low side circuit path (with 1020) electrically coupled in parallel with the freewheeling diode (1006). (For Example: Par. 71-80) Regarding Claim 18, Cohen teaches (Figures 4-6 and 10) wherein the switching cycle is a steady state switching cycle (normal operation). (For Example: Par. 71-80) Regarding Claim 21-22, Cohen teaches (Figures 4-6 and 10) wherein the second subinterval (diode conducting) is subsequent to the first subinterval (1004 conducting); wherein the third subinterval (1020) is subsequent to the second subinterval (diode conducting, see fig. 4). (For Example: Par. 71-80) Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 9 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cohen in view of Jovanovic US 2005/0226012. Regarding Claim 9, Cohen teaches (Figures 4-6 and 10) the converter. Cohen does not teach wherein the current reversing path is configured to operate as a single quadrant switch. Jovanovic teaches (Figure 18) wherein the current reversing path is configured to operate as a single quadrant switch (S1 and D1). (For Example: Par. 79) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Nishida to include wherein the current reversing path is configured to operate as a single quadrant switch, as taught by Jovanovic so that switching losses are reduced with beneficial effects on conversion efficiency and EMC performance. Regarding Claim 16, Cohen teaches (Figures 4-6 and 10) the converter. Cohen does not teach wherein the current reversing path further comprises a diode electrically coupled in series with the FET. Jovanovic teaches (Figure 18) wherein the current reversing path (d1 and S1) further comprises a diode (d1) electrically coupled in series with the FET (108, par. 63). (For Example: Par. 63 and 79) It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Nishida to include wherein the current reversing path is configured to operate as a single quadrant switch, as taught by Jovanovic so that switching losses are reduced with beneficial effects on conversion efficiency and EMC performance. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached at 5712721838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GUSTAVO A ROSARIO-BENITEZ/ Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Nov 09, 2023
Application Filed
Sep 05, 2025
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+25.3%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 733 resolved cases by this examiner. Grant probability derived from career allow rate.

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