DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The amendment filed on 11/13/2023 has been entered. In the amendment, Applicant amended claim 20. Currently claims 1-20 are pending.
Claim Objections
Claim 4 is objected to because of the following informalities: “a vial hole” in last line should be changed to “a via hole”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-3, 7 and 12-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites the element “a plurality of the pixel driving circuits” in ll. 2. There is insufficient antecedent basis for this element in the claim. It appears that Applicant attempt to mean “a plurality of pixel driving circuits, wherein each of the plurality of pixel driving circuits is the same as the pixel driving circuit”, if the element “a pixel driving circuit” recited in parent claim 1 and an assumption that each pixel driving circuit of the display panel is the same are taken into consideration. Furthermore, the element “the pixel driving circuit” recited in the instant claim appears to mean “each of the plurality of pixel driving circuits”, because only in such an interpretation, the element “the second conductive parts” recited in ll. 3 from the bottom of page 3 is definite.
Claim 3 is rejected because it depends on claim 2.
Claim 7 recites the element “the third initial signal line”. There is insufficient antecedent basis for this element in the claim. It is also unclear the third initial signal line is connected to which one of the transistors in claim 1. In view of Fig. 1 as originally filed, the third initial signal line is connected to transistor T9, which should be included in the instant claim.
Claim 12 is rejected for substantially the same rationale as applied to claim 2. Furthermore, claim 12 recites in last line of page 7 “a plurality of electrode parts” and “the electrode part”, the latter being indefinite because it is unclear it refers to which one of the “plurality of electrode parts”.
Claim 13 is rejected because it depends on claim 12.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-6, 8-11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Dai et al. (US 2024/0046862) in view of Zeng et al. (US 2024/0038161).
Regarding claim 1, Dai teaches a display panel ([0005]-[0006]) comprising a base substrate (Fig. 1: substrate 11) and a pixel driving circuit (Fig. 1; Fig. 4: pixel circuit layout 200) provided on a side of the base substrate (Fig. 3: pixel circuit disposed on substrate 11), wherein the pixel driving circuit comprises:
a driving transistor (Fig. 1: driving transistor T1: Fig. 4: driving transistor T1 with layout illustrated);
an eighth transistor (Fig. 1: first restoring transistor T8: Fig. 4: first restoring transistor T8 with layout illustrated) having a first electrode (Fig. 1: upper electrode of T8; Figs. 4 and 8: source electrode T8S of T8) connected to a gate electrode (Fig. 1: gate of T1; Figs. 4, 6: gate electrode T1G) of the driving transistor;
a first transistor (Fig. 1: second restoring transistor T4; Fig. 4: second restoring transistor T4 with layout illustrated) having a first electrode (Fig. 1: lower electrode of T4; Figs. 4-5: drain electrode T4D of the second restoring transistor T4D) connected to a first initial signal line (Figs. 1, 4: first restoring signal source VI1) and a second electrode (Fig. 1: upper electrode of T4; Figs. 4-5: source electrode T4S of the second restoring transistor T4) connected to a second electrode (Fig. 1: lower electrode of T8; Figs. 4 and 8: drain electrode T8D of T8) of the eighth transistor; and
a second transistor (Fig. 1: compensation transistor T3; Fig. 4: compensation transistor T3 with layout illustrated) having a first electrode (Fig. 1: left electrode of T3; Figs. 4-5: drain electrode T3D of the compensation transistor T3D) connected to the second electrode of the eighth transistor and a second electrode (Fig. 1: right electrode of T3; Figs. 4-5: Figs. 4-5: source electrode T3S of the compensation transistor T3D) connected to a second electrode (Fig. 1: lower electrode of driving transistor T1; Figs. 4-5: drain electrode T1D of driving transistor T1D) of the driving transistor.
Dai does not further teach the pixel driving circuit comprise:
a ninth transistor having a first electrode connected to a third initial signal line and a second electrode connected to a first electrode of the driving transistor.
In the same field of endeavor, Zeng teaches in Fig. 1 a pixel driving circuit that uses such a ninth transistor in the circuit to periodically apply a reset power to the source electrode of the driving transistor in order to reduce or eliminate image motion blur due to hysteresis deviation ([0062],[0063]), the pixel driving circuit comprises:
a ninth transistor (Fig. 1: second transistor T2) having a first electrode (Fig. 1: right electrode of T2) connected to a third initial signal line (Fig. 1: signal line supplying reset power VEH) and a second electrode (Fig. 1: left electrode of T2) connected to a first electrode (Fig. 1: upper electrode of T1) of the driving transistor.
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to combine Zeng’s technique with Dai’s technique by including Zeng’s second transistor to Dai’s pixel driving circuit with the same arrangement as taught by Zeng to mitigate motion blur (Zeng: [0062]-[0063]).
Regarding claim 5, Dai further teaches the display panel according to claim 1, wherein the display panel further comprises a light-emitting unit (Fig. 1: light-emitting element OL), the pixel driving circuit further comprises a seventh transistor (Fig. 1: reset transistor T7) having a first electrode (Fig. 7: left electrode of T7) connected to a second initial signal line (Fig. 1: signal line connected to second restoring signal source VI2) and a second electrode (Fig. 1: right electrode of T7) connected to a first electrode of the light-emitting unit, and the display panel further comprises:
a second conductive layer (Fig. 1: necessarily existing conductive layer on which signal line connected to second restoring signal source VI2 is disposed) provided on a side of the base substrate (Fig. 3: any conductive layer necessarily provided on upper side of substate 11) and comprising the second initial signal line, an orthographic projection of the second initial signal line on the base substrate extending in a first direction (Fig. 1: direction of inherent signal line connected to second restoring signal source VI2); and
a sixth conductive layer (Fig. 9: third metal layer on which connection lines connected to second restoring signal source VI2 are disposed) provided on a side of the second conductive layer away from the base substrate (Fig. 3: any conductive layer necessarily provided on upper side of substate 11) and comprising a second initial connection line (Fig. 9: connection lines connected to second restoring signal source VI2)
Dai in view of Zeng does not further teach the second initial connection line being connected to the second initial signal line with the orthographic projection on the base substrate intersected with an orthographic projection of the second initial connection line on the base substrate.
The differentiating limitation indicates the second initial connection line and the second initial connection line intersect with each other.
Examiner takes Official Notice that it is common in the related art to arrange the second initial connection line and the second initial connection line such that they intersect with each other.
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to arrange the second initial connection line and the second initial connection line such that they intersect with each other.
Because an arrangement of the second initial connection line and the second initial connection line is either parallel or intersecting with each other, one ordinary skill in the art would try either one to suit a real condition of real estate of the display panel.
Regarding claim 6, Dai further teaches the display panel according to claim 1, wherein the display panel further comprises:
a second conductive layer (Figs. 3 and 7: second metal layer 17) provided on a side of the base substrate and comprising the first initial signal line, an orthographic projection of the first initial signal line on the base substrate extending in a first direction (Figs. 3 and 7: horizontal direction); and
a sixth conductive layer (Figs. 3 and 10: fourth metal line 23) provided on a side of the second conductive layer away from the base substrate and comprising a first initial connection line (Figs. 4 and 10: first connection electrode 201), the first initial connection line being connected to the first initial signal line with the orthographic projection on the base substrate intersected with an orthographic projection of the first initial connection line on the base substrate (Fig. 4: first connection electrode 201 connected to first restoring signal source VI1).
Regarding claim 8, Dai further teaches the display panel according to claim 1, wherein the display panel further comprises:
a first conductive layer (Figs. 3 and 6: first metal layer 15) provided on a side of the base substrate (any conductive layer necessarily provided on upper side of substate 11) and comprising a first conductive part (Fig. 6: gate electrode T1G of the driving transistor T1) configured to form the gate electrode of the driving transistor;
a second active layer (Figs. 3 and 8: second active layer 19) provided on a side of the first conductive layer away from the base substrate and comprising a sub-active part (Fig. 8: active layer T8B, source electrode T8S and drain electrode T8D of the first restoring transistor T8), the sub-active part comprising an eighth active part (Fig. 8: active layer T8B) and a twentieth active part (Fig. 8: source electrode T8S of the first restoring transistor T8) connected to the eighth active part, and the eighth active part being configured to form a channel region of the eighth transistor; and
a fourth conductive layer (Figs. 3 and 10: fourth metal layer 23) provided on a side of the second active layer away from the base substrate and comprising a fourth bridging part (Figs. 4 and 10: third connection electrode 203), the fourth bridging part being connected to the twentieth active part through a first via hole (Fig. 4: via 3) and to the first conductive part through a second via hole (Fig. 4: via 4).
Regarding claim 9, Dai further teaches the display panel according to claim 8, wherein the display panel further comprises:
a first active layer (Figs. 3, 5: first active layer 13) provided between the base substrate and the first conductive layer and comprising a second active part (Figs. 4-5: active layer T3B), the second active part being configured to form a channel region of the second transistor,
the first conductive layer further comprises:
a first gate line (Figs. 4 and 6: first scanning line Sn), an orthographic projection of the first gate line on the base substrate extending in a first direction (Figs. 4 and 6: horizontal direction) and covering an orthographic projection of the second active part on the base substrate (Figs. 4 and 6), and a portion of the first gate line being configured to form a gate electrode of the second transistor (Figs. 4 and 6); and
a third conductive part (Figs. 4 and 8: source electrode T8S of first restoring transistor T8) connected to the first gate line, an orthographic projection of the third conductive part on the base substrate being located at a side, facing an orthographic projection of the first conductive part on the base substrate, of the orthographic projection of the first gate line on the base substrate,
wherein the orthographic projection of the third conductive part on the base substrate is at least partially overlapped with an orthographic projection of the first via hole on the base substrate (Fig. 4: source electrode T8S of first restoring transistor T8 is overlapped with via3).
Regarding claim 10, Dai further teaches the display panel according to claim 8, wherein the display panel further comprises a fifth transistor (Figs. 1 and 4: first light-emitting control transistor T5) having a first electrode (Fig. 1: upper electrode of T5; Fig. 4: source electrode T5S of first light-emitting control transistor T5) connected to a first power line (Fig. 1: VDD power line) and a second electrode (Fig. 1: lower electrode of T5; Fig. 4: drain electrode T5D of first light-emitting control transistor T5) connected to the first electrode of the driving transistor,
the display panel further comprises:
a fifth conductive layer (Figs. 3, 11: fifth metal layer 25) provided on a side of the fourth conductive layer (Figs. 3: fourth metal layer 23) away from the base substrate and comprising the first power line, an orthographic projection of the first power line on the base substrate extending in a second direction (Figs. 4, 11: VDD power line extending in vertical direction), and covering an orthographic projection of the sub-active part on the base substrate and an orthographic projection of the fourth bridging part on the base substrate (Fig. 4: orthographic projection of VDD power line covering orthographic projection of drain electrode T8D, source electrode T8S of first restoring transistor T8 and third connection electrode 203).
Regarding claim 11, Dai further teaches the display panel according to claim 10, wherein the display panel further comprises a fourth transistor (Figs. 1, 4: data writing transistor T2) having a first electrode (Fig. 1: left electrode of T2, Fig. 4: source electrode T2S of the data writing transistor T2) connected to a data line (Fig. 2 Data line; Fig. 4: Data line) and a second electrode (Fig. 1: right electrode of T2, Fig. 4: drain electrode T2D of the data writing transistor T2) connected to the first electrode of the driving transistor,
the display panel further comprises:
a first active layer (Figs. 3, 5: first active layer 13) provided between the base substrate (Fig. 3: substrate 11) and the first conductive layer (Fig. 1: first metal layer 15) and comprising a second active part (Figs. 4-5: active layer T3B of compensation transistor T3) and a fourth active part (Figs. 4-5: active layer T2B of data writing transistor T2), the second active part being configured to form a channel region of the second transistor, and the fourth active part being configured to form a channel region of the fourth transistor,
in a first direction (Figs. 4-5: horizontal direction), an orthographic projection of the eighth active part (Figs. 4 and 8: active layer T8B of first restoring transistor T8) on the base substrate is located between an orthographic projection of the second active part on the base substrate and an orthographic projection of the fourth active part on the base substrate (Fig. 4).
Claim 20 is rejected for substantially the same rationale as applied to claim 1.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Dai et al. (US 2024/0046862) in view of Zeng et al. (US 2024/0038161), and further in view of Sun et al. (US 2021/0043713).
Regarding claim 4, Dai further teaches the display panel according to claim 1, wherein the display panel further comprises a light-emitting unit (Fig. 1: light-emitting element OL), and the pixel driving circuit is connected to a first electrode (Fig. 1: anode/first electrode O11 of the light-emitting element OL) of the light-emitting unit,
the display panel further comprises:
a sixth conductive layer (Figs. 1 and 3: a necessarily existing conductive layer, not shown, on which power supplying line connected to second power source VSS is disposed) provided on a side of the base substrate (Fig. 3: power supplying line, not shown, connected to second power source VSS is necessarily provided on upper side of substrate 11) and comprising a third power line (Fig. 1: power line connected to second power source VSS), an orthographic projection of the third power line on the base substrate extending in a second direction (any direction along which the necessary VSS power line is extended); and
a common electrode layer (Figs. 1 and 3: inherent common electrode layer on which second electrode O12 of light-emitting element OL is disposed) (Fig. 1: second electrode O12 of the light-emitting element OL) of the light-emitting unit,
Dai in view of Zeng does not further teach the common electrode layer provided on a side of the sixth conductive layer away from the base substrate, wherein the third power line is at least partially provided in a display area of the display panel, and the third power line is connected to the common electrode layer through a via hole.
The differentiating limitation indicates that the sixth conductive layer on which the third power (VSS) line is located and the common electrode layer are different layers and the third power line is connected to the common electrode layer through a via hole. The technique is not new, however.
Sun, for instance, teaches in Fig. 1 a conductive layer on which the third power (VSS) line (i.e., conductive layer including first cathode connection line 2) is located and the common electrode layer (i.e., conductive layer with cathode 33) are different layers and the third power line is connected to the common electrode layer through a via hole (i.e., via hole 61).
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to further modify the technique of Dai in view of Zeng with Sun’s technique arranging the sixth conductive layer on which the third power (VSS) line is located and the common electrode layer as different layers and having the third power line connected to the common electrode layer through a via hole.
The motivation/suggestion would have been to arranging a layout of the pixel driving circuit according to available real estate condition of the display panel.
Allowable Subject Matter
Claim 14-19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 14: layout of the ninth transistor relative to other elements of the display is not taught by Dai and not obvious to be achieved by modification of Dai’s technique.
Claim 19: “a square resistance of the first conductive layer is greater than a square resistance of the fourth conductive layer” is not taught by Dai and not obvious to be achieved by modification of Dai’s technique.
Claims 2-3, 7 and 12-13 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
WO 2023159503 (Figs. 4b, 8-26) by the same Applicant is related art to this application, but is not eligible as prior art.
US 2023/0267888 (Fig. 3) by the same Applicant is related art to this application, but is not eligible as prior art.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XUEMEI ZHENG whose telephone number is (571)272-1434. The examiner can normally be reached Monday-Friday: 9:30 pm-6:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin Lee can be reached at 571-272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/XUEMEI ZHENG/Primary Examiner, Art Unit 2629