DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The Preliminary Amendment filed on 11/14/2024 has been entered. In the amendment, Applicant amended claims 3, 5, 7-8, 10, 12, 14, 19-20, 22-25 and 28, cancelled claims 4, 6, 9, 11, 13, 15, 21, 26. Currently claims 1-3, 5, 7-8, 10, 12, 14, 16-20, 22-25 and 27-28 are pending. As for the submission of claims filed on 1/28/2025, Applicant asserts in the response to Non-Compliant Amendment submitted on 10/15/2025 that it is a translation rather than an amendment.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Feng et al. (CN 113793570 A, machine translation of which is used in this examination).
Regarding claim 1, Feng teaches a shift register (Figs. 24-25: exemplary shift register in different embodiments), comprising:
a voltage regulating circuit (Figs. 24-25: entire circuit of illustrated shift register circuit except output circuit consisting of T9, T10a, T10b, T20a, T20b and two capacitors directly connected to T9, T10a, T10b and T20a) electrically connected to a light-emitting signal input terminal (Figs. 24-25: first signal terminal S1), a first clock signal terminal (Figs. 24-25: first clock signal terminal CKA), a second clock signal terminal (Figs. 24-25: second clock signal terminal CKB), a first node (Figs. 24-25: node N1), and a second node (Figs. 24-25: node N2), and configured to adjust voltages at the first node and the second node in response to control of signals provided by the light-emitting signal input terminal, the first clock signal terminal, and the second clock signal terminal (Figs. 24-25: first signal terminal S1, first clock signal terminal CKA and second clock signal terminal CKB are involved in adjusting voltages at node N1 and node N2);
a light-emitting cascade output circuit (Figs. 24-25: output circuit consisting of T9, T10a, T10b, capacitor directly connected to T9 and capacitor directly connected to T10a and T10b functions as a “light-emitting cascade output circuit”, which is evidenced in Figs. 24-25 where previous-stage output signal OUT<N-1> is a cascade output and input to current shift register; Examiner’s Note: it is implied that current-stage output signal OUT<N> is a cascade output and input to the next stage shift register) electrically connected to a first power terminal (Figs. 24-25: second voltage signal terminal VGL), a second power terminal (Figs. 24-25: first voltage signal terminal VGH), a light-emitting cascade signal output terminal (Figs. 24-25: output signal terminal OUT<N>), the first node (Figs. 24-25: node N1), and the second node (Figs. 24-25: node N2), and configured to write a second operating voltage (Figs. 24-25: second voltage provided by second voltage signal terminal VGH) provided by the second power terminal to the light-emitting cascade signal output terminal in response to control of the voltage at the first node (Figs. 24-25: control of node N1 causes second voltage signal terminal VGH to provide second voltage to output signal terminal OUT<N>), and write a first operating voltage (Figs. 24-25: first voltage provided by first voltage signal terminal VGL) provided by the first power terminal to the light-emitting cascade signal output terminal in response to control of the voltage at the second node (Figs. 24-25: control of node N2 causes first voltage signal terminal VGL to provide first voltage to output signal terminal OUT<N>);
a light-emitting driving output circuit (Figs. 24-25: “light-emitting driving output circuit” is the same as “light-emitting cascade output circuit”, which consists of T9, T10a, T10b, capacitor directly connected to T9 and capacitor directly connected to T10a, T10b) electrically connected to a fifth power terminal (Figs. 24-25: firt voltage signal terminal VGL), a third power terminal (Figs. 24-25: second voltage signal terminal VGH), a light-emitting control driving signal output terminal (Figs. 24-25: output signal terminal OUT<N>), the second node (Figs. 24-25: Node N1), the first node (Figs. 24-25: Node N1), and configured to write a third operating voltage (Figs. 24-25: third operating voltage provided by second voltage signal terminal VGH) provided by the third power terminal to the light-emitting control driving signal output terminal in response to control of the voltage at the first node (Figs. 24-25: control of node N1 causes second voltage signal terminal VGH to provide second voltage to output signal terminal OUT<N>), and to write a fifth operating voltage (Figs. 24-25: fifth operating voltage provided by first voltage signal terminal VGL) provided by the fifth power terminal to the light-emitting control driving signal output terminal in response to control of the voltage at the second node (Figs. 24-25: control of node N2 causes first voltage signal terminal VGL to provide first voltage to output signal terminal OUT<N>); and
a first anti-leakage circuit (Figs. 24-25: T20a, T20b and T26) electrically connected to the light-emitting cascade output circuit at a first anti-leakage node (Figs. 24-25: first leakage-proof node OFF1), and further electrically connected to the first node (Figs. 24-25: upper terminal of T20b is connected to node N1 via the capacitor connected to gate of T9 and OUT<N>), the second node (Figs. 24-25: lower terminal of T20a is connected to node N2 via the capacitor connected to gate of T10b and terminal VGL), the second power terminal (Figs. 24-25: T20b is connected to VGH via T9), and a fourth power terminal (Figs. 24-25: first voltage signal end terminal VGL), and configured to write a fourth operating voltage (Figs. 24-25: voltage provided by first voltage signal end terminal VGL) provided by the fourth power terminal to the first anti-leakage node in response to control of the voltage at the second node (Figs. 24-25: when node N2 is at a high level, VGL is transmitted to first leakage-proof node OFF1).
Regarding claim 16, Feng further teaches the shift register according to claim 1, wherein the light-emitting driving output circuit comprises an eleventh transistor (Figs. 24-25: T10b), a second capacitor (Figs. 24-25: capacitor directly connected to gate of T10b and VGL), a first capacitor (Figs. 24-25: capacitor directly connected to gate of T9 and terminal OUT<N>), and a sixth transistor (Figs. 24-25: T9);
a control electrode (Figs. 24-25: gate of T10b) of the eleventh transistor is electrically connected to the first node, a first electrode (Figs. 24-25: lower terminal of T10b) of the eleventh transistor is electrically connected to the third power terminal (Figs. 24-25: lower terminal of T10b connected to power terminal VGH via first leakage-proof node OFF1), and a second electrode (Figs. 24-25: upper terminal of T10b) of the eleventh transistor is electrically connected to the light-emitting control driving signal output terminal (Figs. 24-25: lower terminal of T10b connected to output terminal OUT<N>);
a first terminal (Figs. 24-25: lower terminal of capacitor directly connected to gate of T9 and OUT<N>) of the second capacitor is electrically connected to the third power terminal, and a second terminal (Figs. 24-25: upper terminal of capacitor directly connected to gate of T9 and OUT<N>) of the second capacitor is electrically connected to the first node;
a control electrode (Figs. 24-25: gate of T9) of the sixth transistor is electrically connected to the second node, a first electrode (Figs. 24-25: lower terminal of T9) of the sixth transistor is electrically connected to the light-emitting control driving signal output terminal, and a second electrode (Figs. 24-25: upper terminal of T9) of the sixth transistor is electrically connected to the fifth power terminal; and
a first terminal (Figs. 24-25: lower terminal of capacitor that is connected to T10b and VGL) of the first capacitor is electrically connected to the light-emitting control driving signal output terminal, and a second terminal (Figs. 24-25: upper terminal of capacitor that is connected to T10b and VGL) of the first capacitor is electrically connected to the second node.
Allowable Subject Matter
Claims 2-3, 5, 7-8, 10, 12, 14, 17-20, 22-25 and 27-28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2: “a control electrode of the thirteenth transistor is electrically connected to the first node”;
Claim 3: detailed structure of the claimed “second anti-leakage circuit”;
Claim 5: detailed structure of the claimed “second anti-leakage circuit”;
Claim 17: “the fourth operating voltage provided by the fourth power terminal is higher than the first operating voltage provided by the first power terminal”;
Claim 18: “the second operating voltage provided by the second power terminal is lower than the third operating voltage provided by the third power terminal”;
Claim 19: “the light-emitting signal input terminal of the first shift register at a first stage is electrically connected to a light-emitting start signal line, and the first shift registers at stages other than the first stage are electrically connected to light-emitting cascade signal output terminals of the first shift registers at respective previous stages”;
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
CN 120032595, made of record by the same Applicant, discloses in Fig. 6 the same second anti-leakage circuit of this instant application, which is not eligible prior art, however.
US 2021/0335203, made of record by the same Applicant, discloses in Figs. 12A-12C a shift-register unit includes a common anti-leak circuit, a first anti-leak circuit and a second anti-leak circuit, none of which, however, teaches the first anti-leakage circuit or the second anti-leakage circuit.
US 2021/0158744, made of record by Kang et al., discloses in Fig. 5 a shift register includes separate cascade output terminal CRi and driving output terminal Gi.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XUEMEI ZHENG whose telephone number is (571)272-1434. The examiner can normally be reached Monday-Friday: 9:30 pm-6:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin Lee can be reached at 571-272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/XUEMEI ZHENG/Primary Examiner, Art Unit 2629