Prosecution Insights
Last updated: April 19, 2026
Application No. 18/290,785

SOLID ELECTROLYTIC CAPACITOR AND METHOD FOR PRODUCING SOLID ELECTROLYTIC CAPACITOR

Non-Final OA §102§103
Filed
Jan 21, 2024
Examiner
SINCLAIR, DAVID M
Art Unit
2848
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Panasonic Intellectual Property Management Co., Ltd.
OA Round
1 (Non-Final)
68%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
87%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allow Rate
833 granted / 1232 resolved
At TC average
Strong +20% interview lift
Without
With
+19.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
42 currently pending
Career history
1274
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
49.6%
+9.6% vs TC avg
§102
30.0%
-10.0% vs TC avg
§112
12.8%
-27.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1232 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Email Communication Applicant is encouraged to authorize the Examiner to communicate with applicant via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.03, 502.05. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Objections Claim 13 is objected to because of the following informalities: from 2 µm 50 µm should read from 2 µm to 50 µm. Appropriate correction is required. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2 & 13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kato et al. (US 2004/0113242). In regards to claim 1, Kato ‘242 discloses A solid electrolytic capacitor comprising: a capacitor element (2 – fig. 1; [0029]) including an anode part and a cathode part ([0029]); an anode lead frame (9 – fig. 1; [0029]) electrically connected to the anode part; a cathode lead frame (90 – fig. 1; [0029]) electrically connected to the cathode part; and an exterior body (7 – fig. 1; [0029]) covering the capacitor element, wherein: the anode lead frame includes a first buried part that is a part of the anode lead frame, the first buried part being buried in the exterior body (seen in fig. 1), the cathode lead frame includes a second buried part that is a part of the cathode lead frame, the second buried part being buried in the exterior body (seen in fig. 1), and a plurality of recesses (8, 6, or 60 – fig. 1-9; [0031], [0035], & [0037]) are formed on a surface of at least one of the first buried part or the second buried part. In regards to claim 2, Kato ‘242 discloses The solid electrolytic capacitor according to Claim 1, wherein the plurality of recesses are formed on a surface of the first buried part and a surface of the second buried part (fig. 1; [0044]). In regards to claim 10, Kato ‘242 discloses The solid electrolytic capacitor according to any one of claim 1, wherein a side surface of the at least one of the first buried part or the second buried part is processed to have irregularities (fig. 5 & 7-9 – side surfaces have indentations formed from recess extending width of the lead and thus have irregularities). In regards to claim 13, Kato ‘242 discloses The solid electrolytic capacitor according to claim 1, wherein a depth of each of the plurality of recesses is from 2 µm to 50 µm, inclusive ([0035]). Claim(s) 17 & 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ueda et al. (US 2019/0214199). In regards to claim 17, Ueda ‘199 discloses A solid electrolytic capacitor comprising: a capacitor element (10 – fig. 1; [0027]) including an anode part and a cathode part ([0027]); an anode lead frame (7 – fig. 1; [0027]) electrically connected to the anode part; a cathode lead frame (9 – fig. 1; [0027]) electrically connected to the cathode part via a conductive adhesive layer including conductive particles ([0028]); and an exterior body (11 – fig. 1; [0027]) covering the capacitor element, wherein: the anode lead frame includes a first buried part that is a part of the anode lead frame, the first buried part being buried in the exterior body (seen in fig. 1), the cathode lead frame includes a second buried part that is a part of the cathode lead frame, the second buried part being buried in the exterior body (seen in fig. 1), at least one of the first buried part or the second buried part includes a first surface that is in contact with the exterior body (seen in fig. 1), the second buried part includes a second surface that is in contact with the conductive adhesive layer (seen in fig. 1), a plurality of first recesses (7g – fig. 2-3; [0033]) are formed on the first surface, the exterior body includes a resin and an insulating filler ([0036]), and an average diameter D1 of openings of the plurality of first recesses and an average particle diameter P1 of the insulating filler satisfy 0 <P1/D1< 1 (fig. 6B; [0037]). In regards to claim 19, Ueda ‘199 discloses The solid electrolytic capacitor according to Claim 17, wherein the average diameter D1 is in a range from 10 µm to 100 µm, inclusive ([0024]). In regards to claim 20, Ueda ‘199 discloses The solid electrolytic capacitor according to Claim 17, wherein a plurality of second recesses are formed on the second surface (seen in fig. 3). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 9, 11-12, 14-15 & 25-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kato ‘242 in view of Trinh (US 2015/0296623). In regards to claim 9, Kato ‘242 fails to discloses wherein the plurality of recesses are recesses formed by irradiation with laser light. Trinh '623 disclose wherein the plurality of recesses are recesses formed in a lead frame for a capacitor are formed by irradiation with laser light ([0024]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the recesses of Kato ‘242 using a laser as taught by Trinh '623 as such a method of is a known method of forming recess in a lead frame and based on the manufacturing equipment available. In regards to claim 11, Kato ‘242 fails to discloses wherein: at least one of the anode lead frame or the cathode lead frame includes a base material and a plating layer formed on a surface of the base material, the plating layer is not present in each of the plurality of recesses, and the plating layer is present in a region between the plurality of recesses on the surface of the at least one of the first buried part or the second buried part. Trinh '623 disclose wherein: at least one of the anode lead frame or the cathode lead frame includes a base material and a plating layer formed on a surface of the base material, the plating layer is not present in each of the plurality of recesses, and the plating layer is present in a region between the plurality of recesses on the surface of the at least one of the first buried part or the second buried part ([0024] & [0029]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the lead of Kato ‘242 to have a base and plating layer and to form the recess of Kato ‘242 in the plated lead (i.e. the recess penetrate the plating layer) as taught by Trinh '623 to obtain leads that are easily soldered. In regards to claim 12, Kato ‘242 as modified by Trinh '623 further discloses wherein: the plurality of recesses are formed on a surface of the first buried part and a surface of the second buried part (fig. 1; [0044] of Kato ‘242), and the region where the plurality of recesses are not formed in the surface of the at least one of the first buried part or the second buried part is covered with the plating layer ([0024] & [0029] of Trinh '623). In regards to claim 14, Kato ‘242 as modified by Trinh '623 further discloses wherein the base material is exposed from the plating layer at a bottom of each of the plurality of recesses ([0024] & [0029] of Trinh '623). In regards to claim 15, Kato ‘242 as modified by Trinh '623 further discloses wherein the plurality of recesses include a recess having a circular opening (fig. 2 of Kato ‘242). In regards to claim 25, Kato ‘242 discloses a method for producing a solid electrolytic capacitor, the solid electrolytic capacitor comprising a capacitor element (2 – fig. 1; [0029]) including an anode part and a cathode part ([0029]), an anode lead frame (9 – fig. 1; [0029]) electrically connected to the anode part, and a cathode lead frame (90 – fig. 1; [0029]) electrically connected to the cathode part, the anode lead frame including a first buried part that is a part of the anode lead frame, the cathode lead frame including a second buried part that is a part of the cathode lead frame, the method comprising: a step (i) of forming a plurality of recesses (8, 6, or 60 – fig. 1-9; [0031], [0035], & [0037]) on a surface of at least one of the first buried part or the second buried part; a step (ii) of electrically connecting the first buried part to the anode part of the capacitor element and electrically connecting the second buried part to the cathode part of the capacitor element (fig. 1); and a step (iii) of covering the first buried part, the second buried part, and the capacitor element with an exterior body (7 – fig. 1; [0029]). Kato ‘242 fails to disclose the recesses formed by irradiating at least one of the first buried part or the second buried part with laser light a plurality of times; the step (i) includes: a step (i-a) of preparing at least one of the anode lead frame or the cathode lead frame including a base material and a plating layer formed on the base material, and a step (i-b) of irradiating the plating layer on at least one of the first buried part or the second buried part with the laser light a plurality of times to form the plurality of recesses while the plating layer remains in a region between the plurality of recesses. Trinh '623 disclose recesses formed by irradiating the lead frame with laser light a plurality of times; the step (i) includes: a step (i-a) of preparing the lead frame including a base material and a plating layer formed on the base material, and a step (i-b) of irradiating the plating layer on the lead frame with the laser light a plurality of times to form the plurality of recesses while the plating layer remains in a region between the plurality of recesses ([0024] & [0029]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the lead of Kato ‘242 to have a base and plating layer and to form the recess of Kato ‘242 in the plated lead (i.e. the recess penetrate the plating layer) as taught by Trinh '623 to obtain leads that are easily soldered. In regards to claim 26, Kato ‘242 as modified by Trinh '623 further discloses wherein in the step (i-b), the plurality of recesses are formed so that the base material is exposed from the plating layer at a bottom of each of the plurality of recesses ([0024] & [0029] of Trinh '623). Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kato ‘242 as modified by Trinh '623 as applied to claim 11 above, and further in view of JP2020072186A hereafter referred to as Ogata. In regards to claim 16, Kato ‘242 as modified by Trinh '623 fails to disclose wherein a proportion (S1/S0) of an area S1 covered with the plating layer in the surface of the at least one of the first buried part or the second buried part in an area S0 of the surface of at least one of the first buried part or the second buried part is from 10% to 90%, inclusive. Ogata disclose at least one of the anode lead frame or the cathode lead frame includes a base material and a plating layer formed on a surface of the base material, the plating layer is not present in each of the plurality of recesses, and the plating layer is present in a region between the plurality of recesses on the surface of the at least one of the first buried part or the second buried part (fig. 3b-3C & [0072] & [0077-0078] – Au plated copper layer has holes punched therein (i.e. punching is done after forming recess and thus will not be present in holes but will be present in between holes)), wherein a proportion (S1/S0) of an area S1 covered with the plating layer in the surface of the at least one of the first buried part or the second buried part in an area S0 of the surface of at least one of the first buried part or the second buried part is from 10% to 90%, inclusive ([0077-0078]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the lead of Kato ‘242 as modified by Trinh '623 to have an area ratio as taught by Ogata to obtain enhance the effect of suppressing the positional deviation of the lead terminal while suppressing the reduction in the strength of the lead terminal. Claim(s) 25-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kato ‘242 in view of JP2008135460A hereafter referred to as Kawakatsu. In regards to claim 25, Kato ‘242 discloses a method for producing a solid electrolytic capacitor, the solid electrolytic capacitor comprising a capacitor element (2 – fig. 1; [0029]) including an anode part and a cathode part ([0029]), an anode lead frame (9 – fig. 1; [0029]) electrically connected to the anode part, and a cathode lead frame (90 – fig. 1; [0029]) electrically connected to the cathode part, the anode lead frame including a first buried part that is a part of the anode lead frame, the cathode lead frame including a second buried part that is a part of the cathode lead frame, the method comprising: a step (i) of forming a plurality of recesses (8, 6, or 60 – fig. 1-9; [0031], [0035], & [0037]) on a surface of at least one of the first buried part or the second buried part; a step (ii) of electrically connecting the first buried part to the anode part of the capacitor element and electrically connecting the second buried part to the cathode part of the capacitor element (fig. 1); and a step (iii) of covering the first buried part, the second buried part, and the capacitor element with an exterior body (7 – fig. 1; [0029]). Kato ‘242 fails to disclose the recesses formed by irradiating at least one of the first buried part or the second buried part with laser light a plurality of times; the step (i) includes: a step (i-a) of preparing at least one of the anode lead frame or the cathode lead frame including a base material and a plating layer formed on the base material, and a step (i-b) of irradiating the plating layer on at least one of the first buried part or the second buried part with the laser light a plurality of times to form the plurality of recesses while the plating layer remains in a region between the plurality of recesses. Kawakatsu disclose a lead frame for a solid electrolytic capacitor wherein the lead frame has a recess formed by irradiating the lead frame with laser light; the step (i) includes: a step (i-a) of preparing the lead frame including a base material and a plating layer formed on the base material, and a step (i-b) of irradiating the plating layer on the lead frame with the laser light to form the recess while the plating layer remains in the unirradiated portion (fig. 2-3; [0027]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the lead of Kato ‘242 to have a base and plating layer and to form the recesses of Kato ‘242 in the plated lead (i.e. the recesses penetrate the plating layer) as taught by Kawakatsu to obtain leads that are easily soldered. In regards to claim 26, Kato ‘242 as modified by Kawakatsu further discloses wherein in the step (i-b), the plurality of recesses are formed so that the base material is exposed from the plating layer at a bottom of each of the plurality of recesses (fig. 3 of Kawakatsu). In regards to claim 27, Kato ‘242 as modified by Kawakatsu disclose all the claimed limitations discussed above with respect to claim 27, except for a wavelength of the laser light is in a range from 300nm to 600 nm, inclusive. However, Kawakatsu discloses that the laser intensity (i.e. wavelength) is a result effective variable, particularly for controlling the depth of a groove ([0027]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to construct the capacitor of Kato ‘242 as modified by Kawakatsu using a laser light with a wavelength in a range from 300nm to 600 nm, inclusive to control the depth of the groove, as taught by Kawakatsu. Where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Claim(s) 17-18, 20, & 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over JP2006237195A hereafter referred to as Ini in view of Kawakatsu. In regards to claim 17, Ini discloses a solid electrolytic capacitor comprising: a capacitor element (15 – fig. 1; [0014]) including an anode part and a cathode part ([0014]); an anode lead frame (61 – fig. 1; [0014]) electrically connected to the anode part; a cathode lead frame (62 – fig. 1; [0014]) electrically connected to the cathode part via a conductive adhesive layer including conductive particles; and an exterior body (7 – fig. 1; [0014]) covering the capacitor element, wherein: the anode lead frame includes a first buried part that is a part of the anode lead frame, the first buried part being buried in the exterior body (seen in fig. 1), the cathode lead frame includes a second buried part that is a part of the cathode lead frame, the second buried part being buried in the exterior body (seen in fig. 1), at least one of the first buried part or the second buried part includes a first surface (20a) that is in contact with the exterior body (seen in fig. 1; [0015]), the second buried part includes a second surface (20) that is in contact with the conductive adhesive layer (seen in fig. 1; [0015]), a plurality of first recesses (21a – fig. 1; [0015]) are formed on the first surface, the exterior body includes a resin ([0014]), and an average diameter D1 of openings of the plurality of first recesses ([0015]) Ini fails to disclose the exterior body includes an insulating filler and an average diameter D1 of openings of the plurality of first recesses and an average particle diameter P1 of the insulating filler satisfy 0 <P1/D1< 1. Kawakatsu disclose an insulating filler and an average diameter D1 of openings of the plurality of first recesses and an average particle diameter P1 of the insulating filler satisfy 0 <P1/D1< 1 (fig. 2-3; [0026-0027]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the capacitor of Ini using an exterior resin as taught by Kawakatsu to obtain an exterior resin with improved characteristics (e.g. strength, thermal characteristics, moisture protection) obtained from the filler. In regards to claim 18, Ini as modified by Kawakatsu further disclose wherein the average diameter D1 and the average particle diameter P1 satisfy 0.5≤P1/D1≤0.8 ([0026-0027] of Kawakatsu 100/200=0.5). In regards to claim 20, Ini as modified by Kawakatsu further disclose wherein a plurality of second recesses (20a – fig. 1; [0015] of Ini) are formed on the second surface. In regards to claim 24, Ini as modified by Kawakatsu further disclose wherein each of the plurality of first recesses and each of the plurality of second recesses are recesses formed by irradiation with laser light ([0027] of Kawakatsu). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form the recess of Ini using a laser as taught by Kawakatsu to obtain precisely formed recess and based on the equipment available. Claim(s) 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ini as modified by Kawakatsu as applied to claim 17 above, and further in view of Vivcova (US 2011/0205689). In regards to claim 21, Ini as modified by Kawakatsu fails to disclose wherein an average diameter D2 of openings of the plurality of second recesses and an average particle diameter P2 of the conductive particles satisfy 1.2≤D2/P2. Vivcova ‘689 discloses an average particle diameter P2 of the conductive particles is 10-100 microns and 0.1-3 microns ([0016-0018]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use the conductive adhesive of Vivcova ‘689 as the conductive adhesive of Ini as modified by Kawakatsu thus obtaining 1.2≤D2/P2 (200/100=2) to obtain ensure the degree to which the adhesive is compressed during manufacture, thereby ensuring that it will have the minimum thickness needed to achieve a reliable mechanical connection to the desired part. In regards to claim 22, Ini as modified by Kawakatsu and Vivcova ‘689 further discloses wherein the average diameter D2 is in a range from 5 µm to 500 µm, inclusive ([0027] of Kawakatsu). Allowable Subject Matter Claim(s) 3-8 & 23 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not teach or suggest (in combination with the other claim limitations) wherein the plurality of recesses include at least one first recess having a groove shape and a plurality of second recesses not each having a groove shape (claims 3-8) & wherein the average diameter D2 is larger than the average diameter D1 (claim 23). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2016/0118197 – fig. 6 US 2022/0084750 – fig. 7-8 US 2017/0320247 – fig. 3-4 US 2005/0057889 – fig. 1-2 US 8,390,990 – fig. 3 WO2019065077A1 – fig. 2C Communication Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID M SINCLAIR whose telephone number is (571)270-5068. The examiner can normally be reached M-TH from 8AM-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /David M Sinclair/Primary Examiner, Art Unit 2848
Read full office action

Prosecution Timeline

Jan 21, 2024
Application Filed
Jan 27, 2026
Non-Final Rejection — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
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Grant Probability
87%
With Interview (+19.6%)
2y 7m
Median Time to Grant
Low
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