DETAILED ACTION
1. This Office Action is responsive to claims filed for No. 18/290,883 on December 17, 2025. Please note Claims 1-3, 7-11 and 15-20 are pending. Please note Claims 2, 7-9, 17 and 20 have been withdrawn in light of an earlier restriction requirement.
America Invents Act
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 1, 3, 10, 11, 15, 16, 18 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Byun et al. ( US 2024/0135876 A1 ).
Byun teaches in Claim 1:
A pixel circuit, comprising a light-emitting element, a compensation control circuit, a data writing circuit, a driving circuit, and a first energy storage circuit ( Figure 2, [0059]+ disclose these components, detailed below ), wherein
the compensation control circuit is electrically connected to a first scanning end, a reference voltage end, and a control end of the driving circuit, and is configured to write a reference voltage from the reference voltage end into the control end of the driving circuit under control of a first scanning signal from the first scanning end ( Figure 2, [0067] disclose a transistor T3 with a control terminal connected to scan signal GR, a terminal connected to VREF and another terminal connected to the gate of T1 (read as a driving circuit) );
the data writing circuit is electrically connected to a second scanning end, a data line, and the control end of the driving circuit, and is configured to write a data voltage from the data line into the control end of the driving circuit under control of a second scanning signal from the second scanning end ( Figure 2, [0066] disclose a transistor T2 with a control terminal connected to scan signal GW, a terminal connected to data line Vdata and another terminal connected to the gate of T1 );
the first energy storage circuit is electrically connected to the control end of the driving circuit and is configured to store electric energy ( Figure 2, [0064] discloses a storage capacitor Cst connected to the gate of T1 );
the driving circuit is configured to generate a current for driving the light-emitting element under control of a potential at the control end of the driving circuit ( Figure 2, [0065] discloses a transistor T1 which can supply a driving current to the light emitting element LD from the first power line PL1/VDD );
a display period of the pixel circuit comprises an initialization stage, a compensation stage and a data writing stage independent of each other and sequentially set ( Figure 3, [0083] discloses P1 is an initialization period with transistors T4, T7, etc, being turned on. [0087] discloses P2 is a compensation period with transistor T3 being turned on. [0090] discloses P3 is a data writing period with T1 and T2 being turned on. Please note these periods are independent and sequentially set, as shown in Figure 3 );
the data writing circuit comprises a fifth transistor ( Figure 2, [0066] discloses the interpreted data writing circuit comprises transistor T2 ), only the second scanning signal controls the fifth transistor to turn on at the data writing stage, to write the data voltage from the data line into the control end of the driving circuit ( Figure 2, [0066] discloses first scan signal GW is the only scanning signal which not only controls transistor T2, but GW does not control any other transistor shown. Under the application of GW, the data signal Vdata may be transferred to the first node N1 and on to transistor T1. Please note this is done during P3, as detailed in Figure 3, [0090] )
the pixel circuit further comprises a first initialization circuit and a second initialization circuit;
the first initialization circuit is electrically connected to a third scanning end, a first initial voltage end and the first end of the driving circuit, and is configured to, only at the initialization stage, write a first initial voltage from the first initial voltage end into the first end of the driving circuit under control of a third scanning signal from the third scanning end ( Figure 2 discloses transistor T7 is connected to scan signal GI and writes VINT to transistor T1. Figure 3, [0083] discloses details on P1 and how T7 is turned on. Only during P1 is this first initial voltage is written, as shown by GI[N] in P1. To clarify, it is during this period, i.e. only this period, in which T4 and T7 are both turned on to provide initialization aspects. During P2, P3 and P4, there is no initializing aspects ) and
the second initialization circuit is electrically connected to the third scanning end, a second initial voltage end and the first electrode of the light-emitting element, and is configured to write a second initial voltage from the second initial voltage end into the first electrode of the light-emitting element under control of the third scanning signal. ( Figure 2 discloses transistor T4 is also connected to scan signal GI and writes VAINT to the first terminal of light emitting element LD. Figure 3, [0083] discloses details on P1 and how T4 is turned on. Only during P1 is this first initial voltage is written, as shown by GI[N] in P1. To clarify, it is during this period, i.e. only this period, in which T4 and T7 are both turned on to provide initialization aspects. During P2, P3 and P4, there is no initializing aspects )
Byun teaches in Claim 3:
The pixel circuit according to claim 1, further comprising a first light-emission control circuit ( Figure 2, [0061] discloses a transistor T6 with connections to EMB/EBL (read as a first light-emission control circuit), first initialization power voltage VINT (along with transistor T7) and a second initialization power voltage VAINT (along with transistor T4) ), wherein
the first light-emission control circuit is electrically connected to a first light-emission control end, a first end of the driving circuit and a first electrode of the light-emitting element, and is configured to control the first end of the driving circuit to be electrically connected to, or electrically disconnected from, the first electrode of the light-emitting element under control of a first light-emission control signal from the first light-emission control end; a second electrode of the light-emitting element is electrically connected to a first voltage end ( Figure 2 discloses transistor T6 connected to EMB, a first end of transistor T1 and a first electrode of light emitting element LD );
Byun teaches in Claim 10:
The pixel circuit according to Claim 1, further comprising a second light-emission control circuit ( Figure 2, [0069] discloses a transistor T5 connected to a first emission light control signal EM ), wherein
the second light-emission control circuit is electrically connected to a second light-emission control end, a power source voltage end and a second end of the driving circuit, and is configured to control the power source voltage end to be electrically connected to, or electrically disconnected from, the second end of the driving circuit under control of a second light-emission control signal from the second light-emission control end. ( Figure 2 discloses T5 is connected to EM, VDD and to a second end of transistor T1 )
Byun teaches in Claim 11:
The pixel circuit according to claim 3, wherein the first light-emission control circuit comprises a first transistor, the first initialization circuit comprises a second transistor, and the second initialization circuit comprises a third transistor ( Figure 2 discloses transistor T6 for the first light-emission control circuit, transistor T7 for the first initialization circuit, and transistor T4 for the second initialization circuit );
a gate electrode of the first transistor is electrically connected to the first light-emission control end, a first electrode of the first transistor is electrically connected to the first end of the driving circuit, and a second electrode of the first transistor is electrically connected to the first electrode of the light-emitting element ( Figure 2 shows a gate electrode of transistor T6 is connected to EMB, a first electrode is connected to the first end of transistor T1 and a second electrode is connected to the first electrode of the light emitting element LD );
a gate electrode of the second transistor is electrically connected to the third scanning end, a first electrode of the second transistor is electrically connected to the first initial voltage end, and a second electrode of the second transistor is electrically connected to the first end of the driving circuit ( Figure 2 shows a gate electrode of transistor T7 is connected to scan signal GI, a first electrode is connected to VINT, and a second electrode is connected to transistor T1 ); and
a gate electrode of the third transistor is electrically connected to the third scanning end, a first electrode of the third transistor is electrically connected to the second initial voltage end, and a second electrode of the third transistor is electrically connected to the first electrode of the light emitting element. ( Figure 2 shows a gate electrode of transistor T4 is connected to scan signal GI, a first electrode is connected to VAINT, and a second electrode is connected to a first electrode of the light emitting element LD )
Byun teaches in Claim 15:
The pixel circuit according to claim 10, wherein the compensation control circuit comprises a fourth transistor ( Figure 2 discloses transistor T3 for the interpreted compensation control circuit );
a gate electrode of the fourth transistor is electrically connected to the first scanning end, a first electrode of the fourth transistor is electrically connected to the reference voltage end, and a second electrode of the fourth transistor is electrically connected to the control end of the driving circuit ( Figure 2 discloses a gate electrode of transistor T3 is connected to scan signal GR, a first electrode is connected to VREF and a second electrode is connected to transistor T1 ); and
a gate electrode of the fifth transistor is electrically connected to the second scanning end, a first electrode of the fifth transistor is electrically connected to the data line, and a second electrode of the fifth transistor is electrically connected to the control end of the driving circuit. ( Figure 2 discloses a gate electrode of transistor T2 is connected to scan signal GW, a first electrode is connected to data line Vdata and a second electrode is connected to transistor T1 )
Byun teaches in Claim 16:
The pixel circuit according to claim 10, wherein the driving circuit comprises a driving transistor, and the second light-emission control circuit comprises a sixth transistor ( Figure 2 discloses transistor T1 for the interpreted driving circuit and transistor T5 for the interpreted second light-emission control circuit );
a gate electrode of the sixth transistor is electrically connected to the second light-emission control end, a first electrode of the sixth transistor is electrically connected to the power source voltage end, and a second electrode of the sixth transistor is electrically connected to the second end of the driving circuit ( Figure 2 discloses a gate electrode of T5 is connected to EM, a first electrode is connected to VDD and a second electrode is connected to transistor T1 ); and
a gate electrode of the driving transistor is electrically connected to the control end of the driving circuit, a first electrode of the driving transistor is electrically connected to a first end of the driving circuit, and a second electrode of the driving transistor is electrically connected to the second end of the driving circuit. ( Figure 2 discloses a gate electrode of T1 is the interpreted driving circuit (please see Applicant’s Figures 6 and 10 for reference), a first electrode of T1 is the first end and a second electrode of T1 is the second end )
Byun teaches in Claim 18:
A pixel driving method, applied to the pixel circuit according to claim 1, with the display period comprising a compensation stage and a data writing stage independent of each other ( Figure 3, [0085], [0087] discloses second period P2 is for compensation. Figure 3, [0089] discloses a third period P3 is for transistor T2 to be turned on for data signal Vdata to be transferred ), wherein the pixel driving method comprises:
at the compensation stage, writing, by the compensation control circuit, a reference voltage from the reference voltage end into the control end of the driving circuit under the control of a first scanning signal from the first scanning end ( Figure 3, [0085], [0087] discloses during period P2, reference power VREF is applied to compensate transistor T1. This is done through transistor T3 and its scan signal GR ); and
at the data writing stage, writing, by the data writing circuit, a data voltage from the data line into the control end of the driving circuit under the control of a second scanning signal from the second scanning end. ( Figure 3, [0089] discloses Vdata is transferred to node N1 and passed on to transistor T1. This is done through transistor T2 and its scan signal GW )
Byun teaches in Claim 19:
A display device, comprising the pixel circuit according to claim 1. ( Figure 1, [0002] discloses a display device )
Response to Arguments
5. Applicant’s arguments considered, but are respectfully not persuasive.
Please note the updated rejection in light of the claim amendments. However, these limitations are incorporated from dependent claims. Byun clearly teaches of a first and second initialization circuits which are designed to be turned on by GI and controls transistors T4 and T7. Figure 3, [0083] discloses details on P1, which is an initialization period. It is during this period, i.e. only this period, in which T4 and T7 are both turned on to provide initialization aspects. During P2, P3 and P4, there is no initializing aspects.
Conclusion
6. All claims are either identical to or patentably indistinct from the claims in the application prior to the entry of the submission under 37 CFR 1.114 (that is, restriction would not be proper) and all claims could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the application prior to entry under 37 CFR 1.114. Accordingly, THIS ACTION IS MADE FINAL even though it is a first action after the filing of a request for continued examination and the submission under 37 CFR 1.114. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DENNIS P JOSEPH/Primary Examiner, Art Unit 2621