CTNF 18/291,159 CTNF 78883 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Examiner’s Note The prior art rejection below cites particular paragraphs, columns, and/or line numbers in the references for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on . The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1, 4 – 6, 8, 10, 12, 15 – 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Iyer et al., (US PUB 2015/0301831 hereinafter Iyer) in view of Arimilli et al., (US PUB 2009/0064166 hereinafter Arimilli) . As to claim 1 Iyer teaches a compiler system for reconfiguration of compute resources (“A processing device comprises select logic to schedule a plurality of instructions for execution. The select logic calculates a reconstructed program order (RPO) value for each of a plurality of instructions that are ready to be scheduled for execution...” abstract) and (“...The processing device implements a multi-strand architecture which allows out-of-order fetching and execution of instructions arranged by the compiler into multiple strands. The processing device may implement a complex instruction set computing (CISC) architecture, a reduced instruction set computer (RISC) architecture, a very long instruction word (VLIW) architecture, or other instruction sets, or a combination of instruction sets, through translation of binary codes in the abovementioned instruction sets into the multi-strand architecture by a compiler...” para. 0063) , comprising: a scheduler (“...scheduler....” title, abstract and para. 0006) and (“...scheduling of instructions in a multi-strand out-of-order processor using a delayed reconstructed program order...” para. 0018) ; and a reconfigurable architecture array (“Processing device 802 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. The processing device implements a multi-strand architecture which allows out-of-order fetching and execution of instructions arranged by the compiler into multiple strands. The processing device may implement a complex instruction set computing (CISC) architecture, a reduced instruction set computer (RISC) architecture, a very long instruction word (VLIW) architecture, or other instruction sets, or a combination of instruction sets, through translation of binary codes in the abovementioned instruction sets into the multi-strand architecture by a compiler. Processing device 802 may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA),...” para. 0063) comprising a plurality of hardware resources (“...The processor 100 shown in FIG. 1 is logically divided into a front end unit 110, an instruction scheduling unit 120, an execution unit ...” para. 0026) and (“...execution unit 130 includes a number of execution ports 132, 134, 136, to which operand-ready instructions stored in the instruction scheduling unit 120 are dispatched...” para. 0031) and (“FIG. 5 is a block diagram illustrating a hardware arrangement 500 for reconstructing a program order in a multi-strand out-of-order processor, according to an embodiment of the present invention. The arrangement 500 may be implemented as part of an instruction scheduling unit (ISU), such as ISU 120 within a multi-strand out-of-order processor, such as processor 100...” para. 0044) ; wherein the schedular dynamically reconfigures the reconfigurable architecture array (“...store instructions for scheduling instructions in a processor based on a delayed reconstructed processing order, as described herein...” para. 0066) by: determining a plurality of programs comprising a first program and a second program that require execution on the reconfigurable architecture array (“..To be able to fully make use of the ILP and maintain a high sustained execution width, it is essential to be able to select the right strands (and therefore instructions), which might be on the critical path to dispatch from the available ready to dispatch strands in the scheduler...” para. 0020 – 0021. Note: strands would comprise first and second programs) and (“...determines when instructions are ready to be sent for execution...” para. 0029) at a particular time n (“...The number of entries selected as being scheduled for execution in any given clock cycle may vary from cycle to cycle but could be a maximum up to x...” para. 0046) and (“...instructions that have selected to be scheduled for execution in a given cycle.” Para. 0048) , wherein each program comprises a plurality of functions (“...Since the PO value of the next PO instruction in the strand has been calculated by the previous PO instruction (i.e., by adding the IPO of the previous PO instruction dispatched with the strand PO value), the PO value of the next PO instruction in the strand can be set equal to the PO value of non-PO instructions when dispatched. ...” para. 0045); determining hardware resources required by the first program and the second program (“...the instruction scheduling unit 120 may further include select logic 170. Select logic 170 may take as its input one or more instructions stored in SSF2 160 and determine the availability of execution ports for those stored instructions. For example, if there are n strands of instructions and x execution ports, select logic 170 may select up to x out of the n stored instructions to designate to the x execution ports 132, 134, 136...” para. 0030) ; and a set of functions from the plurality of functions (“...instructions within strand ... para. 0022). While Iyer determines availability of hardware resources to execute the strands programs (para. 0030), Iyer does not but Arimilli teaches allocate [a set of functions from the plurality of functions of] the first program and the second program to different hardware resources from the plurality of hardware resources [of the reconfigurable architecture array] based on the determined hardware resources required by the first program and the second program (“...shift workloads from the slowest processor to one or more of the faster processors” abstract, para. 0014 and 0066. Note: workloads would include first and second workloads) and (“...In effect, this causes a shift of data from the slowest processor 424 to the fastest processor 420...” para. 0077) and (“..Therefore, moving a task from a slowest processor to a fastest processor will only have the effect of slowing down the faster processor by providing it twice as much work to do...” para. 0090 - 0092). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Iyer by applying the teachings of Arimilli because Arimilli would balance workloads in processors to process loads without significantly negatively affecting the overall operation of the parallel execution system (abstract and para. 0014). Iyer would apply shifting technique to balance tasks or programs on hardware resources of the reconfigurable architecture array since reconfigurable architecture array is also processor based. As to claim 4, Iyer and Arimilli teaches The compiler system of claim 1, Iyer does not but Arimilli teaches further comprising: determining that there is sufficient available hardware resources from the plurality of hardware resources of the reconfigurable architecture array to accommodate the first program and the second program; and allocating the first program and the second program on the reconfigurable architecture array (“Another option is to allocate additional tasks to the faster processor for it to run concurrently. This essentially increases the amount of useful work being done by the faster processor, slows the faster processor down because of the additional load on its resources, and thereby makes the faster processor complete its MPI tasks at a timeframe closer to that of the other processors...” para. 0092). See motivation for claim 1 above. As to claim 5, Iyer and Arimilli teaches The compiler system of claim 1, Iyer does not but Arimilli teaches further comprising: determining that there is insufficient available resources from the plurality of resources of the reconfigurable architecture array to accommodate the first program and the second program (“...Thus, in order to rebalance the system, it is important to be able to provide more work to the faster processor, thereby essentially slowing it down, and optionally less work to the slower processor(s) so that they are able to perform their MPI task faster...” para. 0091) ; and allocating the entire first program and a reduced subset of functions from the plurality of functions of the second program on the reconfigurable architecture array (“...reducing the size of the portion of data the slower processor(s) must process...” para. 0091) and (“...for balancing a Message Passing Interface (MPI) workload across a plurality of processors...modifying a second amount of data to be processed by the second processor in executing the second associated MPI task in the next computation cycle to thereby decrease the amount of data.” Claims 1 - 2) . See motivation for claim 1 above. As to claim 6, Iyer and Arimilli teaches The compiler system of claim 1, Iyer teaches further comprising: determining that a third program requires execution on the reconfigurable architecture array (“..different strands of a multi-strand program representation generated by the compiler...” Note: third program would be one of multi-strand, para. 0005 ; Iyer does not but Arimilli teaches determining that there is insufficient available resources from [the plurality of resources of the reconfigurable architecture array] to accommodate the first program, the second program, and the third program (“...Thus, in order to rebalance the system, it is important to be able to provide more work to the faster processor, thereby essentially slowing it down, and optionally less work to the slower processor(s) so that they are able to perform their MPI task faster...” para. 0091) ; and evicting at least one program from the plurality of programs from the [reconfigurable architecture array] (“...reducing the size of the portion of data the slower processor(s) must process...” para. 0091) and (“...for balancing a Message Passing Interface (MPI) workload across a plurality of processors...modifying a second amount of data to be processed by the second processor in executing the second associated MPI task in the next computation cycle to thereby decrease the amount of data.” Claims 1 - 2) . See motivation for claim 1 above. As to claim 8, Iyer and Arimilli teaches The compiler system of claim 1, Iyer does not but Arimilli teaches further comprising: determining a priority of each of the plurality of programs; and allocating hardware resources of the reconfigurable architecture array to the plurality of programs based on the priority (“..As another example, individual processors in the system performing the MPI job may execute jobs of different priorities. Thus, a processor may execute a job having a high priority and a job having a lower priority at the same time. In such a case, the job with the higher priority may temporarily "steal" resources from the job with the lower priority based on the priority policy utilized by the processor....” para. 0006) . See motivation for claim 1 above. As to claim 10, Iyer and Arimilli teaches The compiler system of claim 1, Iyer does not but Arimilli teaches further comprising: detecting a defective hardware resource from the plurality of hardware resources of the reconfigurable architecture array (“...The method may further comprise identifying a second processor, in the plurality of processors, having a slowest time of completion of a computation phase of a second associated MPI task based on the received one or more MPI synchronization operation calls....” para. 0017); and allocate the set of functions from the plurality of functions of the first program and the second program to different hardware resources that avoids the defective hardware resource of the reconfigurable architecture array (“...Moreover, the method may comprise modifying a first amount of data to be processed by the first processor in executing the first associated MPI task in a next computation cycle to thereby increase the amount of data.” Para. 0017) and (“The method may further comprise modifying a second amount of data to be processed by the second processor in executing the second associated MPI task in the next computation cycle to thereby decrease the amount of data....” para. 0018) and (“...reducing the size of the portion of data the slower processor(s) must process...” para. 0091) . See motivation for claim 1 above. As to claim 12, this is a method claim of claim 1. See rejection for claim 1 above. As to claim 15 – 17 and 19 , these claims recite similar scope with claims 4 – 6 and 8 above respectively. See rejection for claims 4 – 6 and 8 above . 07-21-aia AIA Claim 2 – 3, 7, 13 – 14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Iyer in view of Arimilli, as applied to claims 1 and 12, and further in view of Ryu et al., (US PUB 2021/0160820 hereinafter Ryu) . As to claim 2, Iyer and Arimilli teaches The compiler system of claim 1, further comprising: Iyer and Arimilli do not but Ryu teaches using at least one transformation to allocate the set of functions to the different of hardware resources of the plurality of hardware resources of the reconfigurable architecture array (“...a rotation schedule...” para. 0083) and (“...rotating schedule for slot allocation...” para. 0167). It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Iyer and Arimilli by applying the teachings of Ryu because Ryu would provide a rotation schedule for allocation to optimize the execution units. As to claim 3, Iyer and Arimilli teaches The compiler system of claim 1, Iyer and Arimilli do not but Ryu wherein the at least one transformation is a transformation selected from the group consisting of a translation, an affine transform, a vertical flip, a horizontal flip, and a rotation (“...a rotation schedule...” para. 0083) and (“...rotating schedule for slot allocation...” para. 0167). See motivation for claim 2 above. As to claim 7, Iyer and Arimilli teaches The compiler system of claim 6, Iyer teaches further comprising: placing the evicted at least one program on a temporal waitlist; and reallocating the evicted at least one program to the reconfigurable architecture array at a later time period n+1 (“...At block 320, method 300 creates an ordered list of instructions based on the delayed RPO values (i.e. delayed RPO values are used to determine which instructions should be dispatched for scheduling). In one embodiment, select logic 170 may create an ordered list of instructions based on the RPO values that were calculated Z cycles (e.g., 2 or 3 cycles) previously. For example, if the RPO values are updated for dispatched instructions in cycle T, those updated RPO values may be used for scheduling instructions Z cycles later. Normally the system would expect that if the RPO is updated in cycle T, the select logic would use this updated RPO to create an ordered list in cycle T+1 (in order to satisfy the 1-cycle schedule). In the delayed RPO approach, however, the updated RPO will be used in the cycle (T+1)+Z. This removes part of the select logic (i.e., the creation of the ordered list based on the RPO values) from the critical path without a significant loss in performance...” para. 0038) . As to claims 13 - 14 and 18 , these claims recite similar scope with claims 2 – 3 and 7 above respectively. See rejection for claims 2 – 3 and 7 above . 07-21-aia AIA Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Iyer in view of Arimilli, as applied to claim 1, and further in view of AL-AGHBARI et al., (US PUB 2020/0241899 hereinafter AL-AGHBARI) . As to claim 11, Iyer and Arimilli teaches The compiler system of claim 1, Iyer and Arimilli do not but AL-AGHBARI teaches further comprising virtualizing hardware resources of the reconfigurable architecture array over a plurality of programs and a plurality of functions (“An FPGA virtualization platform including a network controller configured to provide an interface to an external network; a static logic section coupled to the network controller, and one or more reconfigurable regions each having a virtualized field programmable gate array vFPGA)...” title, abstract) . It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Iyer and Arimilli by applying the teachings of AL-AGHBARI would implement virtualized programmable gate arrays (FPGA) which is also an accelerator similar to reconfigurable architecture array. Therefore, it can be implemented on the reconfigurable architecture array . 07-21-aia AIA Claim 9 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Iyer in view of Arimilli, as applied to claims 1 and 12, and further in view of Jones et al., (US PUB 2018/0089355 hereinafter Jones) . As to claim 9, Iyer and Arimilli teaches The compiler system of claim 1, Iyer and Arimilli do not but Jones teaches further comprising: randomizing physical locations of the set of functions on the reconfigurable architecture array; and executing a power noisy program (NP) on the reconfigurable architecture array (“..Present embodiments relate to software programs, methods, and devices for reducing noise in a power distribution network using control logic that reduces the number or impact of substantially simultaneous events that draw power from the power distribution network. This may result in less noise on the power distribution network in the form of fewer or less powerful voltage transients. In some cases, the control logic may be inserted into a circuit design and any connections between the control logic and circuitry components may be established without user intervention. The control logic may effectively reduce noise in the power distribution network by scheduling or staggering the events so that they do not occur simultaneously...” title, abstract and para. 0006) and (“...An integrated circuit device comprising: a memory storing compilation software; and a processor that executes the compilation software to: receive a first circuit design for a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC); identify each reset endpoint instantiated in the first circuit design; generate reset sequencing logic included in a reset sequencer when at least one instantiated reset endpoint is identified, wherein the reset sequencing logic reduces noise in a power distribution network shared by one or more circuitry components of the FPGA or ASIC by scheduling...” claim 37) . It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Iyer and Arimilli by applying the teachings of Jones because Jones provides noise program to reduce noise in a power distribution shared by the one or more circuitry components of the FPGA which is also a type of accelerator with reconfigurable architecture (title and claim 37). As to claim 20 , this claim recites similar scope with claim 9. See rejection for claim 9 above. Conclusion 07-96 The prior art made of record but not relied upon request is considered to be pertinent to applicant’s disclosure. Karoubalis, (US PUB 2007/0283311), methods for executing operations using a field programmable gate array (FPGA) (title, abstract and figures 1- 14). Radhika et al., (US PUB 2016/0246602 hereinafter Radhika), discloses path selection for Coarse Grain Reconfigurable Arrays (CGRAs) (title, abstract and figures 1 – 13). Lee et al., (US PUB 2015/0149747 hereinafter Lee), discloses a method of scheduling execution for functional units of a coarse-grained reconfigurable array (CGRA) processor. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHUONG N HOANG whose telephone number is (571)272-3763. The examiner can normally be reached 9:5-30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, KEVIN YOUNG can be reached at 571-270-3180. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PHUONG N HOANG/Examiner, Art Unit 2194 /KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194 Application/Control Number: 18/291,159 Page 2 Art Unit: 2194 Application/Control Number: 18/291,159 Page 3 Art Unit: 2194 Application/Control Number: 18/291,159 Page 4 Art Unit: 2194 Application/Control Number: 18/291,159 Page 5 Art Unit: 2194 Application/Control Number: 18/291,159 Page 6 Art Unit: 2194 Application/Control Number: 18/291,159 Page 7 Art Unit: 2194 Application/Control Number: 18/291,159 Page 8 Art Unit: 2194 Application/Control Number: 18/291,159 Page 9 Art Unit: 2194 Application/Control Number: 18/291,159 Page 10 Art Unit: 2194 Application/Control Number: 18/291,159 Page 11 Art Unit: 2194 Application/Control Number: 18/291,159 Page 12 Art Unit: 2194 Application/Control Number: 18/291,159 Page 13 Art Unit: 2194 Application/Control Number: 18/291,159 Page 14 Art Unit: 2194 Application/Control Number: 18/291,159 Page 15 Art Unit: 2194
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