DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 01/23/24 and 06/16/25 have been considered by the examiner.
Drawings
The drawings received on 01/23/24 are acceptable.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Nosaka et al. (EP 3832864 A1).
Nosaka et al. disclose a driving circuit for switching element, and switching circuit in Figures 1-10.
Nosaka et al. describes a gate driving circuit 100 (corresponding to "gate drive circuit connected to a gate terminal and source terminal of a first switching element and configured to turn the first switching element on and off") that turns a switching element 1 on and off, the gate terminal of the switching element 1 is connected to one end of a capacitor 11, a resistance 13 is connected in parallel to the capacitor 11, the other end of the capacitor 111 is connected to a Vout terminal 123 of a drive circuit 12 from which an output voltage Vout is outputted (corresponding to "first resistance and first capacitor having one end connected to the gate terminal and the other end connected to the first terminal, and being connected to each other in parallel"), one end of a capacitor 14 is connected to the source terminal of the switching element 1, the other end of the capacitor 14 is connected to a Vee terminal 124 of the drive circuit 12 (corresponding to "second capacitor having one end connected to the source terminal and the other end connected to the second terminal"), the drive circuit 12 includes MOSFETS 121, 122 connected in series between a Vdd terminal 125 connected to a voltage source Vdd and the Vee terminal 124 (corresponding to "second terminal connected to the source terminal"), an intermediate point between the MOSFETS 121, 122 is connected to the other end of the capacitor 11 as the Vout terminal 123 (corresponding to "first terminal connected to the gate terminal") (corresponding to "control unit having a first terminal connected to the gate terminal and a second terminal connected to the source terminal, and having a first switch provided between the first terminal and a voltage source and a second switch provided between the first terminal and the second terminal, the control unit being configured to control on and off of the first switching element by switching the first and second switches"), wherein the capacitor 14 is connected to a Zener diode 15 in parallel (corresponding to "first Zener diode connected in parallel to the second capacitor"), and a gate voltage of the switching element 1 is defined by a breakdown voltage of the Zener diode 15 and does not drop below Vec (paragraph 36-38).
Nosaka et al. does not have a clear description that the Zener diode 15 has "a cathode terminal connected to the source terminal and an anode terminal connected to the second terminal". However, the "Zener diode 15" in the invention described in DI is provided to realize the function that the "gate voltage of the switching element 1 is defined by a breakdown voltage of the Zener diode 15 and does not drop below Vee"
(paragraphs 36-38). Further, as described in FIG. 2, Vcc is a negative bias voltage applied to the switching element 1, thus it is apparent that the aforementioned function will not be realized even if the Zener diode 15 is connected in the orientation shown in
FIG. 1. Thus, in order to realize the aforementioned function in the invention described in D1, connecting the cathode terminal of the Zener diode 15 to the source terminal and the anode terminal thereof to the Vee terminal 124 is a matter which a person skilled in the art could easily have done.
With regard to claim 2. Nosaka et al. (especially paragraphs 43-47 and FIGS. 3 and 4) also describes that a switching element 16 that functions as a mirror clamp circuit is connected between the gate terminal of the switching element 1, and one end of the capacitor 11 and the resistance 13, and between it and the other end of the capacitor 14, such that the switching element 16 is turned on when a gate voltage Vgs becomes equal to or lower than a Vmirror voltage SO that Vgs-Va is achieved.
With regard to claim 6. Nosaka et al. (especially paragraphs 64-67 and FIG. 9) describes that a Schottky diode 21 is connected in parallel to the switching element 1 as well as the Zener diode 15 and the capacitor 14 that are connected in parallel with each other.
With regard to claim 7. Nosaka et al. (especially paragraphs 56-59 and FIG. 7) also describes that a Zener diode 19 (corresponding to "second Zener diode") is connected in parallel between the gate and source of the switching element 1.
With regard to claim 8. Nosaka et al. (especially paragraphs 68-72 and FIG. 10) describes a synchronous rectifying boost chopper circuit 10 (corresponding to "switching circuit") having gate drive circuits 100a, 100b respectively connected to two switching elements la, 1b that are connected in series.
Allowable Subject Matter
Claims 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3 is allowed because the prior art of record fails to disclose or suggest including the limitation “ wherein the mirror clamp circuit comprises a second switching element that is turned on when a voltage vqs between the gate terminal as one side and the one end of the first resistor and the one end of the first capacitor together as another side, and between the second terminal as one side and the other end of the second capacitor and the anode terminal of the first Zener diode together as another side becomes equal to or lower than a threshold voltage Vth, and when the first switching sequentially transitions through a plurality of modes that include a first mode during which an input capacitance of the first switching element is charged and the first switching element is turned on, and a second mode during which the first switch is turned off, the second switch is turned on, and the first switching element is turned off“ in addition to other limitations recited therein.
With regard to Claim 4 is allowed because the prior art of record fails to disclose or suggest including the limitation “further comprising a second resistor having one end connected between the source terminal as one side and the one end of the second capacitor and the cathode terminal of the first Zener diode together as another side, the second resistor having the other end connected to a third terminal of the controller that is directly connected to the voltage source “ in addition to other limitations recited therein.
Claim 5 is allowed because the prior art of record fails to disclose or suggest including the limitation “ further comprising: a third resistor having one end connected to the other end of the first capacitor, and the other end connected to the other end of the first resistor; and a fourth resistor and a first diode connected in series, wherein the fourth resistor has one end connected to the other end of the first capacitor, the other end connected to an anode terminal of the first diode, and the first diode has a cathode terminal connected to the other end of the first resistor “ in addition to other limitations recited therein.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nosaka et al. (US 12,272,941 B2) disclose an overcurrent protection circuit and power converter.
Fukumoto et al. (US 11,482,933 B2) disclose a switching power supply device.
Arisawa et al. ((US 11,398,820 B2) disclose a switching circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADOLF D BERHANE whose telephone number is (571)272-2077. The examiner can normally be reached 7 AM - 10 PM.
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/ADOLF D BERHANE/Primary Examiner, Art Unit 2838
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